HYMP264U64(L)8/HYMP264U72(L)8
IDD Meauarement Conditions
Symbol
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCH-
ING;Data bus inputs are SWITCHING
IDD0
IDD1
mA
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
t
t
t
t
t
t
t
t
CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD) ; CKE is HIGH, CS is
mA
HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as
IDD4W
t
t
Precharge power-down current ; All banks idle ; CK = CK(IDD) ; CKE is LOW ; Other control and
IDD2P
IDD2Q
IDD2N
mA
mA
address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH; Other
control and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other con-
trol and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
mA
t
t
Active power-down current; All banks open; CK = CK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
IDD3P
IDD3N
IDD4W
Slow PDN Exit MRS(12) = 1
t
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);
CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
mA
mA
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL
t
t
t
t
t
t
= 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL =
t
t
t
t
t
t
CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as
IDD4W
IDD4R
mA
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
ING; Data bus inputs are SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control
and address bus inputs are FLOATING; Data bus inputs are
FLOATING
Normal
Low Power
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL =
t
t
t
t
t
t
t
t
t
CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD
IDD7
t
mA
= 1* CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STA-
BLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed
timing conditions
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control sig-
nals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not
including masks or strobes.
Rev. 0.2/ April. 2004
12
