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HYMR19616H-653

型号：

HYMR19616H-653

品牌：

HYNIX[ HYNIX SEMICONDUCTOR ]

页数：

17 页

PDF大小：

247 K

下载PDF手册
Direct Rambus RIMM™  
with 128/144Mbit RDRAMs Preliminary  
Overview  
Key Timing Parameters/Part Numbers  
®
TM  
The Rambus RIMM module is a general purpose high- The following table lists the frequency and latency bins  
performance memory subsystem suitable for use in a broad available from RIMM modules. An optional -LP designator  
range of applications including computer memory, personal is used to indicate low power modules.  
computers, workstations, and other applications where high  
bandwidth and low latency are required.  
Table 1: RIMM Module Frequency and Latency  
The Rambus RIMM module consist of 128Mb/144Mb  
Direct Rambus DRAM devices. These are extremely high-  
speed CMOS DRAMs organized as 8M words by 16 or 18  
bits. The use of Rambus Signaling Level (RSL) technology  
permits 600MHz ,711MHz or 800MHz transfer rates while  
using conventional system and board design technologies.  
Direct RDRAM devices are capable of sustained data  
transfers at 1.25 ns per two bytes (10ns per 16 bytes).  
I/O Freq.  
MHz  
t rac (Row Access  
Time) ns  
Organization  
x16  
x16  
x16  
x16  
x18  
x18  
x18  
x18  
600  
711  
800  
800  
600  
711  
800  
800  
53  
45  
45  
40  
53  
45  
45  
40  
The RDRAM architecture enables the highest sustained  
bandwidth for multiple, simultaneous randomly addressed  
memory transactions. The separate control and data buses  
with independent row and column control yield over 95%  
bus efficiency. The Direct RDRAM's 16-banks architecture  
supports up to four simultaneous transactions per device.  
Features  
Form Factor  
wHigh speed 800,711 and 600 MHz RDRAM storage  
w184 edge connector pads with 1 mm pad spacing  
wMaximum module PCB size: 133.5mm x 31.75mm x  
1.37mm(5.21” x 1.25” x 0.05”)  
wEach RDRAM has 32 banks, for a total of 512, 384, 256,  
192 or 128 banks on each 256MB, 192MB, 128MB,  
96MB, or 64MB module respectively  
The Rambus RIMM modules are offered in a 184-pad 1mm  
edge connector pad pitch from factor suitable for either 184  
or 168 contact RIMM connectors. The RIMM module is  
suitable for desktop and other system applications. Figure 1  
shows an eight device Rambus RIMM module without heat  
spreader.  
wGold plated edge connector pad contacts  
wSerial Presence Detect(SPD) support  
¾¡  
wOperates from a 2.5 volt supply ( 5%)  
wLow power and powerdown self refresh modes  
wSeparate Row and Column buses for higher  
efficiency  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 1.0/Dec.99  
1
RIMM with 128/144Mb RDRAM  
Table 2: Module Pad Number and Signal Names  
Pin  
A1  
Pin Name  
Gnd  
Pin  
B1  
Pin Name  
Gnd  
Pin  
Pin Name  
NC  
Pin  
Pin Name  
NC  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
A63  
A64  
A65  
A66  
A67  
A68  
A69  
A70  
A71  
A72  
A73  
A74  
A75  
A76  
A77  
A78  
A79  
A80  
A81  
A82  
A83  
A84  
A85  
A86  
A87  
A88  
A89  
A90  
A91  
A92  
B47  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
B63  
B64  
B65  
B66  
B67  
B68  
B69  
B70  
B71  
B72  
B73  
B74  
B75  
B76  
B77  
B78  
B79  
B80  
B81  
B82  
B83  
B84  
B85  
B86  
B87  
B88  
B89  
B90  
B91  
B92  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
LDQA8  
Gnd  
LDQA6  
Gnd  
LDQA4  
Gnd  
LDQA2  
Gnd  
LDQA0  
Gnd  
LCTMN  
Gnd  
LCTM  
Gnd  
NC  
Gnd  
LROW1  
Gnd  
LCOL4  
Gnd  
LCOL2  
Gnd  
LCOL0  
Gnd  
LDQB1  
Gnd  
LDQB3  
Gnd  
LDQB5  
Gnd  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
LDQA7  
Gnd  
LDQA5  
Gnd  
LDQA3  
Gnd  
LDQA1  
Gnd  
LCFM  
Gnd  
LCFMN  
Gnd  
NC  
Gnd  
LROW2  
Gnd  
LROW0  
Gnd  
LCOL3  
Gnd  
LCOL1  
Gnd  
LDQB0  
Gnd  
LDQB2  
Gnd  
LDQB4  
Gnd  
LDQB6  
Gnd  
NC  
NC  
NC  
Vref  
Gnd  
SCL  
Vdd  
SDA  
SVdd  
SWP  
Vdd  
RSCK  
Gnd  
RDQB7  
Gnd  
RDQB5  
Gnd  
RDQB3  
Gnd  
RDQB1  
Gnd  
RCOL0  
Gnd  
RCOL2  
Gnd  
RCOL4  
Gnd  
RROW1  
Gnd  
NC  
Gnd  
RCTM  
Gnd  
RCTMN  
Gnd  
RDQA0  
Gnd  
RDQA2  
Gnd  
RDQA4  
Gnd  
RDQA6  
Gnd  
RDQA8  
Gnd  
NC  
NC  
NC  
Vref  
Gnd  
SA0  
Vdd  
SA1  
SVdd  
SA2  
Vdd  
RCMD  
Gnd  
RDQB8  
Gnd  
RDQB6  
Gnd  
RDQB4  
Gnd  
RDQB2  
Gnd  
RDQB0  
Gnd  
RCOL1  
Gnd  
RCOL3  
Gnd  
RROW0  
Gnd  
RROW2  
Gnd  
NC  
Gnd  
RCFMN  
Gnd  
RCFM  
Gnd  
RDQA1  
Gnd  
RDQA3  
Gnd  
RDQA5  
Gnd  
RDQA7  
Gnd  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
LDQB7  
Gnd  
LDQB8  
Gnd  
LCMD  
Vcmos  
SIN  
Vcmos  
NC  
Gnd  
NC  
Vdd  
Vdd  
NC  
LSCK  
Vcmos  
SOUT  
Vcmos  
NC  
Gnd  
NC  
Vdd  
Vdd  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
2
Rev.1.0Dec.99  
RIMM with 128/144Mb RDRAM  
Table 3: Module Connector Pad Description  
Signal  
Module Connector Pads  
I/O Type Description  
Gnd  
A1, A3, A5, A7, A9, A11, A13, A15,  
A17, A19, A21, A23, A25, A27, A29,  
A31, A33, A39, A52, A60, A62, A64,  
A66, A68, A70, A72, A74, A76, A78,  
A80, A82, A84, A86, A88, A90, A92,  
B1, B3, B5, B7, B9, B11, B13, B15,  
B17, B19, B21, B23, B25, B27, B29,  
B31, B33, B39, B52, B60, B62, B64,  
B66, B68, B70, B72, B74, B76, B78,  
B80, B82, B84, B86, B88, B90, B92  
Ground reference for RDRAM core and interface.  
72 PCB connector pads.  
LCFM  
B10  
Clock from master. Interface clock used for receiv-  
ing RSL signals from the Channel. Positive polarity.  
RSL  
RSL  
VCMOS  
RSL  
RSL  
RSL  
I
I
LCFMN  
LCMD  
B12  
Clock from master. Interface clock used for receiv-  
ing RSL signals from the Channel. Negative polarity.  
B34  
Serial Command used to read from and write to the  
control registers. Also used for power management.  
I
LCOL4..  
LCOL0  
A20, B20, A22, B22, A24  
A14  
Column bus. 5-bit bus containing control and add-  
ress information for column accesses.  
I
I
I
LCTM  
Clock to master. Interface clock used for transmit-  
ting RSL signals to the Channel. Positive polarity.  
LCTMN A12  
Clock to master. Interface clock used for transmit-  
ting RSL signals to the Channel. Negative polarity.  
LDQA8.. A2, B2, A4, B4, A6, B6, A8, B8, A10  
LDQA0  
Data bus A. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
LDQA8 is non-functional on x16 RDRAM devices.  
I/O RSL  
I/O RSL  
LDQB8.. B32, A32, B30, A30, B28, A28, B26,  
Data bus B. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
LDQB8 is non-functional on x16 RDRAM devices.  
LDQB0  
A26, B24  
LROW2.. B16, A18, B18  
LROW0  
Row bus. 3-bit bus containing control and address  
information for row accesses.  
I
I
RSL  
LSCK  
A34  
Serial Clock input. Clock source used to read from  
and write to the RDRAM control registers.  
VCMOS  
NC  
A16, B14, A38, B38, A40, B40, A77,  
B79  
These pads are not connected. These 8 connector  
pads are reserved for future use.  
NC  
A43, B43, A44, B44, A45, B45, A46,  
B46, A47, B47, A48, B48, A49, B49,  
A50, B50  
These pads are not connected. These 16connector  
pads art reserved for future use. The 168 contact  
RIMM connector does not connect to these PCB  
pads.  
RCFM  
B83  
B81  
Clock from master. Interface clock used for receiv-  
ing RSL signals from the Channel. Positive polarity.  
RSL  
RSL  
I
I
RCFMN  
Clock from master. Interface clock used for receiv-  
ing RSL signals from the Channel. Negative polar-  
ity.  
Rev.1.0 Dec.99  
3
RIMM with 128/144Mb RDRAM  
Signal  
Module Connector Pads  
I/O Type Description  
RCMD  
B59  
Serial Command Input used to read from and write  
VCMOS to the control registers. Also used for power  
management.  
I
RCOL4.. A73, B73, A71, B71, A69  
RCOL0  
Column bus. 5-bit bus containing control and  
RSL  
I
I
I
address information for column accesses.  
RCTM  
A79  
Clock to master. Interface clock used for transmit-  
RSL  
ting RSL signals to the Channel. Positive polarity.  
RCTMN  
A81  
Clock to master. Interface clock used for transmit-  
RSL  
ting RSL signals to the Channel. Negative polarity.  
RDQA8..  
RDQA0  
A91, B91, A89, B89, A87, B87, A85,  
B85, A83  
Data bus A. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
RDQA8 is non-functional on x16 RDRAM devices.  
RSL  
I/O  
I/O  
RDQB8..  
RDQB0  
B61, A61, B63, A63, B65, A65, B67,  
A67, B69  
Data bus B. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
RSL  
RDQB8 is non-functional on x16 RDRAM devices.  
RROW2..  
RROW0  
B77, A75, B75  
A59  
Row bus. 3-bit bus containing control and address  
RSL  
I
I
information for row accesses.  
RSCK  
Serial Clock input. Clock source used to read from  
VCMOS  
and write to the RDRAM control registers.  
SA0  
SA1  
SA2  
SCL  
SDA  
SIN  
B53  
B55  
B57  
A53  
A55  
B36  
Serial Presence Detect Address 0.  
Serial Presence Detect Address 1.  
Serial Presence Detect Address 2.  
Serial Presence Detect Clock.  
SVDD  
SVDD  
SVDD  
SVDD  
SVDD  
I
I
I
I
Serial Presence Detect Data (Open Collector I/O)  
I/O  
Serial I/O for reading from and writing to the control  
registers. Attaches to SIO0 of the first RDRAM on  
the module.  
I/O VCMOS  
SOUT  
A36  
Serial I/O for reading from and writing to the control  
registers. Attaches to SIO1 of the last RDRAM on  
the module.  
I/O VCMOS  
SVDD  
SWP  
VCMOS  
Vdd  
A56, B56  
SPD Voltage. Used for signals SCL, SDA, SWE,  
SA0, SA1 and SA2.  
A57  
Serial Presence Detect Write Protect (active high).  
When low, the SPD can be written as well as read.  
I
I
SVDD  
A35, B35, A37, B37  
CMOS I/O Voltage. Used for signals CMD, SCK,  
SIN, SOUT.  
A41, A42, A54, A58, B41, B42, B54,  
B58  
Supply voltage for the RDRAM core and interface  
logic.  
Vref  
A51, B51  
Logic threshold reference voltage for RSL signals.  
4
Rev.1.0Dec.99  
RIMM with 128/144Mb RDRAM  
SIO0  
SIO1  
SCK  
CMD  
Vref  
Direct RDRAM (128/144Mb) U1  
SIO0  
SIO1  
SCK  
CMD  
Vref  
Direct RDRAM (128/144Mb) U2  
Direct RDRAM (128/144Mb) U3  
SIO0  
SIO1  
SCK  
CMD  
Vref  
SIO0  
SIO1  
SCK  
CMD  
Vref  
Direct RDRAM (128/144Mb) UN  
Vdd  
Module  
Capacity  
Serial Presence Detect  
N
VCMOS  
2 per  
RDRAM  
0.1Þ§  
1 per  
2 RDRAMs  
0.1Þ§  
SVDD  
256MB  
192MB  
128MB  
96MB  
16  
12  
8
Vcc  
Gnd  
VREF  
Gnd  
SCL  
SWP  
SCL  
WP  
SDA  
SDA  
SVDD  
1 per  
A0A1A2  
2 RDRAMs  
Plus one  
Near Connector  
0.1Þ§  
0.1  
Þ§  
6
SA0  
SA1  
SA2  
64MB  
4
Gnd  
Gnd  
Note 1: Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.  
Note 2: See Serial Presence Detection Specification for information on the SPD device and its contents  
Figure 2: RIMM Module Functional Diagram  
Rev.1.0 Dec.99  
5
RIMM with 128/144Mb RDRAM  
Absolute Maximum Ratings  
Signal  
Parameter  
Min  
Max  
Unit  
VI,ABS  
Voltage applied to any RSL or CMOS pin with respect to Gnd  
Voltage on VDD with respect to Gnd  
Storage temperature  
V
V
V DD + 0.3  
V DD + 1.0  
100  
- 0.3  
- 0.5  
- 50  
VDD,ABS  
TSTORE  
º C  
DC Recommended Electrical Conditions  
Signal  
VDD  
Parameter and Conditions  
Min  
Max  
Unit  
Supply voltage  
V
2.50 - 0.13  
2.50 + 0.13  
VCMOS  
CMOS I/O power supply at pad for 2.5V controllers:  
CMOS I/O power supply at pad for 1.8V controllers:  
V
V
2.5 - 0.13  
1.8 - 0.1  
2.5 + 0.25  
1.8 + 0.2  
VREF  
VIL  
Reference voltage  
V
V
V
V
V
V
V
§Ë  
1.4 - 0.2  
VREF - 0.5  
VREF + 0.2  
- 0.3  
1.4 + 0.2  
VREF - 0.2  
VREF + 0.5  
0.5VCMOS - 0.25  
VCMOS + 0.3  
0.3  
RSL input low voltage  
RSL input high voltage  
CMOS input low voltage  
VIH  
VIL,CMOS  
VIH,CMOS CMOS input high voltage  
VOL,CMOS  
0.5VCMOS + 0.25  
CMOS output low voltage @ IOL,CMOS = 1mA  
VOH,CMOS CMOS output high voltage @ IOH,CMOS = -0.25mA  
VCMOS - 0.3  
-10 x no. RDRAMsa 10 x no. RDRAMsa  
-10 x no. RDRAMsa 10 x no. RDRAMsa  
IREF  
VREF current @ VREF,MAX  
ISCK,CMD  
ISIN,SOUT  
CMOS input leakage current @ (0 £ VCMOS £ VDD  
CMOS input leakage current @ (0 £ VCMOS £ VDD  
)
)
§Ë  
§Ë  
-10.0  
10.0  
a. The tale below shows the number of 128Mb or 144Mb RDRAM devices contained in a RIMM module of listed memory storage capacity  
RIMM Module Capacity:  
256MB  
192MB  
128MB  
96MB  
64MB  
Number of 128Mb or 144Mb RDRAM devices:  
16  
12  
8
6
4
6
Rev.1.0Dec.99  
RIMM with 128/144Mb RDRAM  
RIMM Module Current Profile  
256/288MB 192/216MB  
RIMM Module Capacity:  
No. of 128/144Mb RDRAMs:  
128/144MB 96/108MB 64/72MB  
16  
12  
8
6
4
IDD  
Unit  
RIMM module power conditionsa  
Max  
Max  
Max  
Freq.  
Max  
Max  
One RDRAM in Readb, balance  
in NAP mode  
800  
711  
600  
800  
711  
600  
800  
711  
600  
800  
711  
600  
800  
711  
600  
800  
711  
600  
690/658  
633/605  
556/532  
675/641  
618/589  
541/516  
660/625  
603/572  
527/500  
652/616  
596/564  
520/492  
645/608  
589/556  
512/484  
mA  
mA  
mA  
mA  
mA  
mA  
IDD1  
IDD2  
IDD3  
IDD4  
IDD5  
IDD6  
One RDRAM in Readb, balance  
in Standby mode  
2302/2354 1857/1885 1412/1416 1189/1181 967/947  
2142/2199 1725/1757 1307/1316 1099/1095 890/874  
1928/2005 1547/1596 1167/1188 977/983  
787/779  
One RDRAM in Readb, balance  
in Active mode  
3506/3560 2740/2769 1974/1979 1591/1583 1208/1188  
3222/3318 2517/2578 1811/1838 1459/1468 1106/1098  
2889/3006 2253/2331 1616/1655 1297/1317 979/979  
794/766  
765/705  
668/625  
778/750  
750/688  
654/609  
763/733  
735/672  
639/594  
756/724  
728/663  
632/586  
748/716  
720/655  
625/578  
One RDRAM in Write, balance  
in NAP mode  
2405/2462 1960/1993 1515/1524 1293/1290 1070/1055  
2273/2298 1856/1857 1439/1415 1230/1195 1022/974  
2040/2098 1660/1690 1280/1281 1090/1077 900/872  
3609/3668 2843/2878 2077/2087 1694/1692 1311/1296  
3353/3418 2648/2678 1943/1938 1590/1568 1238/1198  
3002/3100 2365/2424 1729/1748 1410/1410 1092/1073  
One RDRAM in Read, balance  
in Standby mode  
One RDRAM in Read, balance  
in Active mode  
a. Specifications in this table are maximum guidelines. Actual power will depend on individual RDRAM component specifications, memory controller  
and usage patterns. Please refer to specific RIMM module vendor data sheets for additional information. Max current computed for x18 144Mb RDRAMs.  
X16 128Mb RDRAMs use 8mA less current per RDRAM in Read.  
b. I/O current is a function of the % of 1’ s, to add I/O power for 50% 1’ s for a X16 need to add 257mA or 290mA for X18ECC module for the following  
: VDD = 2.5V, VTERM = 1.8V, VREF = 1.4V and VDIL = VREF - 0.5V.  
Rev.1.0 Dec.99  
7
RIMM with 128/144Mb RDRAM  
AC Electrical Specifications  
Symbol  
Parameter and Condition  
Min  
25.2  
-
Typ  
Max  
Unit  
§Ù  
Z
Module Impedance  
28  
30.8  
See  
Tablea  
TPD  
Average clock delay form finger to finger of all RSL clock nets  
(CTMN, CFM, and CFMN)  
ns  
b,c  
¥Ä  
TPD  
Propagation delay variation of RSL signals with respect to TPD  
for 4, 6, 8, and 12 device modules  
-21  
-24  
21  
24  
ps  
ps  
ps  
%
%
%
b,c  
Propagation delay variation of RSL signals with respect to TPD  
for 16 device modules  
¥Ä  
TPD-CMOS Propagation delay variation of SCK and CMD signals with  
respect to an average clock delayb  
-100  
100  
See  
Tablea  
V¥á /VIN  
VXF /VIN  
VXB /VIN  
Attenuation Limit  
See  
Tablea  
Forward crosstalk coefficient (300ps input rise time 20%-80%)  
Backward crosstalk coefficient (300ps input rise time 20%-80%)  
See  
Tablea  
a. Table below lists parameters and specifications for different storage capacity RIMM Modules that use 128Mb or 144Mb RDRAM devices.  
b. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN)  
c. If the RIMM module meets the following specification , then it is compliant to the specification. If the RIMM module does not meet these  
specification. Then the specification can be adjusted by the “ Adjusted ¥Ä TPD Specification ” table  
Adjusted ¥Ä TPD Specification  
Asolute  
Min/Max  
Symbol  
Parameter and Conditions  
Adjusted Min/Max  
Unit  
ns  
¥Ä TPD  
Propagation delay variation of RSL signals with respect  
to TPD for 4,6 and 8 device modules  
a
+/-[17+(18*N*Ä¥ Z0)]  
-30  
-40  
-50  
30  
40  
50  
Propagation delay variation of RSL signals with respect  
to TPD for 12 device modules  
a
+/-[20+(18*N*Ä¥ Z0)]  
ps  
Propagation delay variation of RSL signals with respect  
to TPD for 16 device modules  
a
+/-[24+(18*N*Ä¥ Z0)]  
ps  
a. Where : N =Number of RDRAM devices installed on the RIMM module  
¥Ä Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0)  
(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)  
8
Rev.1.0Dec.99  
Direct Rambus RIMM™  
with 128/144Mbit RDRAMs Preliminary  
AC Electrical Specifications for RIMM Modules  
256/288MB 192/216MB  
RIMM Module Capacity:  
128/144MB 96/108MB 64/72MB  
16  
12  
8
6
4
No. of 128/144Mb RDRAMs:  
Symbol  
Unit  
Parameter and Condition for -800 & -600  
RIMM Module  
Max  
Max  
Max  
Max  
Max  
Propagation Delay, all RSL signals -800,-711  
Propagation Delay, all RSL signals -600  
Attenuation Limit -800,-711  
2.06  
2.10  
25  
1.76  
1.76  
20  
1.50  
1.60  
16  
1.4  
1.40  
14  
1.25  
1.25  
12  
ns  
ns  
%
%
TPD  
V¥á /VIN  
Attenuation Limit -600  
21  
18  
10  
9
8
Forward crosstalk coefficient (300ps input  
rise time @ 20%-80%) -800,-711  
8
6
4
3
3
2
2
%
%
%
%
VXF /VIN  
Forward crosstalk coefficient (300ps input  
rise time @ 20%-80%) -600  
8
6
4
Backward crosstalk coefficient (300ps input  
rise time @ 20%-80%) -800,-711  
2.5  
2.5  
2.3  
2.3  
2.0  
2.0  
1.8  
1.8  
1.5  
1.5  
VXB /VIN  
Backward crosstalk coefficient (300ps input  
@
rise time 20%-80%) -600  
DC Resistance Limit -800,-711  
DC Resistance Limit -600  
1.2  
1.2  
1.1  
1.1  
0.8  
0.8  
0.7  
0.7  
0.6  
0.6  
§Ù  
§Ù  
RDC  
Rev. 1.0/Dec.99  
9
RIMM with 128/144Mb RDRAM  
Physical Dimensions  
The following defines the RIMM module dimensions. All units are in millimeters. The height of the module  
is 31.75mm.  
133.35 ¾¡ 0.15  
1.27 ¡¾ 0.1  
3.0  
4.0  
¡¾  
0.15  
Top Area - N Components  
Detail A  
31.75  
R 2.0  
17.78  
Detail B  
A1  
A92  
5.675  
11.5  
4.5  
45.0  
27.5  
Max. 7.37  
55.175 ¾¡ 0.08  
Including  
Heat spreader  
B92  
B1  
0.8 ¾¡ 0.1  
1.0  
2.99 ¾¡ 0.05  
R 1.0  
3.0 ¾¡ 0.1  
2.0 ¾¡ 0.1  
0.15 ¾¡ 0.1  
Detail A  
Detail B  
Note 1.Tolerances on all dimensions ¾¡ 0.127mm unless otherwise specified.  
2.Thickness(* Mark) includes plating and/or metallization.  
Figure 3: RIMM Module PCB Physical Description  
Module Weight  
The maximum RIMM Module weight is 75gm(2.625oz) with a center of mass 35mm (1.378 in.) upwards  
from bottom edge.  
10  
Rev.1.0Dec.99  
RIMM with 128/144Mb RDRAM  
modules are installed in their system. In the diagram,  
a label is shown attached to the RIMM module’ s heat  
spreader. This label contains suggested vendor specific  
information. Information contained on the label is  
specific to the RIMM module and provides RDRAM  
information without requiring removal of the RIMM  
module’ s heat spreader.  
Standard RIMM Module Marking  
The RIMM modules available from RIMM module  
manufacturers will be marked per Figure 4 below. This  
industry standard marking will help OEMs and users  
identify the Rambus RIMM modules for use in specific  
system application. This marking also assists OEMs  
or users to specify and verify if the correct RIMM  
I
F
A
B
C
HYMR16416H-745 G100  
KOREA YWWDVXX S100  
128MB/ 8  
R A M B U S  
711-45  
H
D
J
K
G
E
Label Field  
Description  
Marked Text  
Unit  
Module Memory  
capacity  
Number of 8-bit or 9-bit Mbytes of RDRAM  
storage in RIMM module  
256MB, 192MB, 128MB,  
96MB, 64MB  
A
B
C
MBytes  
Number of  
DRDRAMs  
Number of RDRAM devices contained in the  
RIMM module  
RDRAM  
devices  
/16, /12, /8, /6, /4  
Indicates whether the RIMM module supports  
8-bit (no ECC) or 9-bit (ECC) Bytes  
Blank = 8-bit Byte  
ECC = 9-bit Byte  
ECC support  
D
E
Memory Speed  
tRAC  
Data transfer speed for RDRAM RIMM module  
Row Access Time (Optional field)  
800, 711, 600  
MHz  
ns  
-40, -45, -50, -53  
PCB Gerber file revision used on RIMM Module  
(Optional field)  
F
Gerber Version  
Rev 1.00 = G100  
G
H
I
SPD Version  
Country  
SPD Code Version (Optional field)  
Country Area  
Rev 1.00 = S100  
Korea  
Vendor  
HME specific RIMM module Information  
HME specific Date code, Ass’y Vender  
Device Mask Revision(XX)  
Product Part No  
YWWDV  
J
Vendor  
K
Device Version  
E5,E6,E7 … ….  
Figure 4: Standard RIMM Module Marking  
Rev.1.0 Dec.99  
11  
Serial Presence Detect  
Serial Presence Detect Contents  
The following table lists the contents of the serial presence detect device.  
Byte  
(Dec)  
Value  
(HEX)  
Description  
Option  
Entry  
Symbol  
0
1
2
3
4
SPD revision level  
2
256  
02  
08  
01  
01  
96  
Total number of bytes in the SPD  
Device type  
DRDRAM  
RIMM  
9,6  
Module type  
Row address bits, Column address bits  
16d  
(4 bank bits)  
Bank address bits and byte  
72M  
84  
5
32d  
(5 bank bits)  
128/144M  
C5  
72M  
9,6  
5
04  
05  
20  
02  
-
6
Refresh Bank Bits  
128/144M  
7
8
9
tREF - Refresh interval  
32  
2
tREF  
Protocol version  
-LP  
Miscellaneous device configuration field  
1 tSCK  
tDQS,Min  
no -LP  
01  
-LP  
S28IECO  
-
no -LP  
S28IECO  
05  
-40-800  
-45-800  
-45-711  
-53-600  
-40-800  
-45-800  
-45-711  
-53-600  
-40-800  
-45-800  
-45-711  
-53-600  
-40-800  
-45-800  
-45-711  
-53-600  
8cycles  
8cycles  
8cycles  
8cycles  
20cycles  
20cycles  
20cycles  
20cycles  
8cycles  
10cycles  
8cycles  
8cycles  
8cycles  
8cycles  
8cycles  
8cycles  
tRP-R,Min  
tRP-R,Min  
tRP-R,Min  
tRP-R,Min  
tRAS-R,Min  
tRAS-R,Min  
tRAS-R,Min  
tRAS-R,Min  
tRCD-R,Min  
tRCD-R,Min  
tRCD-R,Min  
tRCD-R,Min  
tRR-R,Min  
tRR-R,Min  
tRR-R,Min  
tRR-R,Min  
08  
08  
08  
08  
14  
14  
14  
14  
08  
0A  
08  
08  
08  
08  
08  
08  
10  
11  
12  
13  
tRP-R,Min  
tRAS-R,Min  
tRCD-R,Min  
tRR-R,Min  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 1.0/Dec.99  
1
Serial Presence Detect  
Byte  
(Dec)  
Value  
Description  
Option  
Entry  
Symbol  
(HEX)  
08  
08  
08  
08  
13  
13  
15  
1A  
1E  
1E  
1E  
1E  
59  
59  
59  
59  
AA  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
04  
8D  
32  
28  
11  
11  
11  
-40-800  
-45-800  
-45-711  
-53-600  
-40-800  
-45-800  
-45-711  
-53-600  
-40-800  
-45-800  
-45-711  
-53-600  
-40-800  
-45-800  
-45-711  
-53-600  
8cycles  
8cycles  
8cycles  
8cycles  
2.50 ns  
2.50 ns  
2.80 ns  
3.33 ns  
3.83 ns  
3.83 ns  
3.83 ns  
3.83 ns  
5 - 9  
tPP-R,Min  
tPP-R,Min  
tPP-R,Min  
tPP-R,Min  
tCYCLE  
14  
15  
16  
17  
tPP-R,Min  
Min tCYCLE for range A  
Max tCYCLE for range A  
tCDLY range for range A  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
5 - 9  
tCYCLE  
5 - 9  
tCYCLE  
5 - 9  
2tCYCLE for  
tCYCLE & tCYCLE  
tCYCLE  
tCYCLE  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
tCLS and tCAS range for range A  
Min tCYCLE for range B  
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
tPDNXA,Max  
tPDNXB,Max  
tNAPXA,Max  
tNAPXB,Max  
Max tCYCLE for range B  
tCDLY range for range B  
tCLS and tCAS range for range B  
Min tCYCLE for range C  
Max tCYCLE for range C  
tCDLY range for range C  
tCLS and tCAS range for range C  
Min tCYCLE for range D  
Max tCYCLE for range D  
tCDLY range for range D  
tCLS and tCAS range for range D  
tPDNXA,Max  
0
0
0
0
0
0
0
0
0
0
0
4 Á§  
tPDNXB,Max  
9000 cylces  
50 ns  
tNAPXA,Max  
tNAPXB,Max  
40 ns  
261MHz,  
400MHz  
261MHz,  
357MHz  
261MHz,  
300MHz  
-800  
-711  
-600  
fIMIN[11:8],  
fIMAX[11:8]  
fIMIN  
fIMAX  
2
Rev.1.0Dec.99  
Serial Presence Detect  
Byte  
(Dec)  
Value  
(HEX)  
Description  
Option  
-800  
Entry  
Symbol  
261MHz  
261MHz  
261MHz  
400MHz  
357MHz  
300MHz  
05  
36  
fIMIN [7:0]  
fIMIN  
-711  
-600  
-800  
-711  
-600  
05  
05  
90  
37  
fIMAX [7:0]  
fIMAX  
65  
2C  
00  
Reserved  
38  
39  
Max. time between Current Control  
Max. time between Temp. Calibration  
100 ms  
100 ms  
tCCTRL,MAX  
tTEMP,MAX  
tTCEN,MIN  
64  
64  
40  
Max. time between Temp. Calibration Enable and Command  
Maximum RAS to Precharge time  
Maximum time that a Device can stay in Nap Mode  
ACTREFPT, PCHREFPT  
150 tCYCLE  
64Á§  
96  
41  
tRAS-R, MAX  
tNLIMIT, MAX  
40  
42  
10Á§  
0A  
66  
43  
6, 6 tCYCLE  
5, 5 tCYCLE  
5, 13 tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
44  
CPCHREFPT_DC, RDREFPT_DC  
RETREFPT_DC, WRREFPT_DC  
Reserved  
55  
45  
5D  
00  
46  
47~49  
50  
-800  
01  
01  
fRAS  
fRAS[11:8]  
-711  
01  
01  
01  
-600  
01  
-800  
-711  
-600  
-800  
-711  
-600  
-800  
90  
90  
51  
52  
53  
fRAS[7:0]  
fRAS  
65  
65  
2C  
2C  
24  
0,0,(100-64)  
0,0,(100-64)  
0,0,(100-64)  
1,(100-64)  
PMAX, HI, PMAX, LO, Tj  
(assumes active-write current is max, Tj = 100)  
É¡  
É¡  
24  
24  
A4  
Heat Spreader, Tplate  
(assumes heat spreader present, Tplate = 100)  
-711  
-600  
1,(100-64)  
1,(100-64)  
TBD  
A4  
A4  
-
54  
55  
56  
57  
58  
59  
60  
61  
PSTBY,HI  
PACTI,HI  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
-
TBD  
-
TBD  
-
PACTRW,HI  
PSTBY,LO  
PACTI,LO  
PACTRW,LO  
TBD  
-
TBD  
-
TBD  
-
TBD  
-
PNAP  
PRESA  
Reserved  
-
Rev.1.0 Dec.99  
3
Serial Presence Detect  
Byte  
(Dec)  
Value  
(HEX)  
Description  
Option  
Entry  
Symbol  
PRESB  
Reserved  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
4
-
-
-
-
62  
63  
-
Checksum for locations 0 - 62  
Manufacturer ID code  
Module manufacturing location  
Module part number  
-
-
64 - 71  
72  
-
-
-
-
-
-
-
-
73 - 90  
91 - 92  
93  
Module revision code  
Module Manufacturing Year  
Module manufacturing week  
-
-
94  
Module serial number  
-
95 - 98  
99  
Number of devices on module  
4D  
04  
06  
08  
0C  
10  
10  
12  
0F  
3F  
FF  
FF  
FF  
00  
00  
00  
Ea  
6D  
6
8D  
8
12D  
16D  
x16  
x18  
4D  
12  
16  
16  
100  
101  
Number of devices on module  
Device enables  
Bit  
Bit  
18  
All 4  
All 6  
All 8  
All 16  
All 16  
-
6D  
8D  
12D  
16D  
4D  
102  
Device enables  
Bit  
Bit  
6D  
-
8D  
-
Device Enables  
-
00  
103~104  
105  
Module Vdd, Module Voltage Interface Level  
2.5V, 1.8V VDD, VTERM  
10  
106  
Module VDD tolerance  
5% DC,  
2% AC  
52  
Reserved  
107-113  
114  
CDLY0/1 for tCDLY = 3  
CDLY0/1 for tCDLY = 4  
CDLY0/1 for tCDLY = 5  
CDLY0/1 for tCDLY = 6  
CDLY0/1 for tCDLY = 7  
CDLY0/1 for tCDLY = 8  
CDLY0/1 for tCDLY = 9  
-
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
00  
20  
30  
31  
32  
42  
52  
2/0  
3/0  
3/1  
3/2  
4/2  
5/2  
115  
116  
117  
118  
119  
120  
4
Rev.1.0Dec.99  
Serial Presence Detect  
Byte  
(Dec)  
Value  
(HEX)  
Description  
Option  
Entry  
Symbol  
CDLY0/1 for tCDLY = 10  
CDLY0/1 for tCDLY = 11  
CDLY0/1 for tCDLY = 12  
CDLY0/1 for tCDLY = 13  
CDLY0/1 for tCDLY = 14  
CDLY0/1 for tCDLY = 15  
Checksum for bytes 99 - 126  
Open for Customer Use  
-
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
tCYCLE  
TBD  
00  
121  
122  
123  
124  
125  
126  
127  
128+  
-
00  
-
00  
00  
-
-
00  
-
TBD  
-
00  
Undefined  
Undefined  
-
EEPROM Component AC and DC Characteristics  
Symbol  
Parameter  
Test Condition  
Min  
Max  
Unit  
SVDD  
ISVdd  
ISVdd1  
ISLI  
power supply  
2.2  
3.6  
5.0  
V
mA  
§Ë  
Active power supply current  
standby current  
fSCL = 100 KHz  
VIN = GND or SVDD  
VIN = GND or SVDD  
VOUT = GND or SVDD  
100  
Input leakage current  
Output leakage current  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
10  
§Ë  
ISLO  
10  
§Ë  
VSIL  
VSIH  
VSOL  
-0.3  
SVDD x 0.3  
SVDD + 0.3  
0.4  
V
SVDD x 0.7  
V
ISOL = 3.0 mA  
V
Rev.1.0 Dec.99  
5
Serial Presence Detect  
EEPROM Component AC Timing Parameters  
Symbol  
Parameter and Conditions  
Min  
Max  
Unit  
fSCL  
T1  
SCL frequency  
100  
100  
0.7  
KHz  
ns  
Á§  
Noise suppression time constant for SCL, SDA  
SCL Low to SDA Data Out Valid  
Time bus must be free before a new transmission can start  
Start Condition Hold Time  
Clock Low Time  
tSAA  
0.3  
6.7  
4.5  
6.7  
4.5  
6.7  
0
tSBUF  
Á§  
tSHD:STA  
tSLOW  
tSHIGH  
tSSU:STA  
tSHD:DAT  
tSSU:DAT  
tSR  
Á§  
Á§  
Clock High Time  
Á§  
Start Condition Setup Time  
Data In Hold Time  
Á§  
Á§  
Data In Setup Time  
500  
ns  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
Stop Condition Setup Time  
Data Out Hold Time  
1
Á§  
tSF  
300  
ns  
Á§  
tSSU:STO  
tSDH  
6.7  
300  
ns  
ms  
tSWR  
EEPROM Write Cycle Time  
15  
SPD Timing Diagram  
6
Rev.1.0Dec.99  
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