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UZNBG3211Q20

型号:

UZNBG3211Q20

品牌:

ZETEX[ ZETEX SEMICONDUCTORS ]

页数:

16 页

PDF大小:

385 K

FET BIAS CONTROLLER WITH POLARISATION  
SWITCH AND TONE DETECTION  
ISSUE 2 - FEBRUARY 2000  
ZNBG3210  
ZNBG3211  
DEVICE DESCRIPTION  
The ZNBG series of devices are designed to  
meet the bias requirements of GaAs and  
HEMT FETs commonly used in satellite  
receiver LNBs, PMR cellular telephones etc.  
with a minimum of external components.  
is achieved with the addition of a single  
resistor. The series also offers the choice of  
FET drain voltage, the 3210 gives 2.2 volts  
drain whilst the 3211 gives 2 volts.  
These devices are unconditionally stable  
over the full working temperature with the  
FETs in place, subject to the inclusion of the  
recommended gate and drain capacitors.  
These ensure RF stability and minimal  
injected noise.  
With the addition of two capacitors and a  
resistorthedevices provide drainvoltageand  
current control for three external grounded  
source FETs, generating the regulated  
negative rail required for FET gate biasing  
whilst operating from a single supply. This  
negative bias, at -3 volts, can also be used to  
supply other external circuits.  
It is possible to use less than the devices full  
complement of FET bias controls, unused  
drain and gate connections can be left open  
circuit without affecting operation of the  
remaining bias circuits.  
The ZNBG3210/11 includes bias circuits to  
drive up to three external FETs. A control  
input to the device selects either one of two  
FETs as operational using 0V gate switching  
methodology, the third FET is permanently  
active. This feature is particularly used as an  
LNB polarisation switch. Also specific to LNB  
applications is the enhanced 22kHz tone  
detection and logic output feature which is  
used to enable high and low band frequency  
switching. The detector has been specifically  
designed to reject inerference such as low  
frequency signals and DiSEqC tone bursts  
- without the use of additional external  
components.  
In order to protect the external FETs the  
circuits have been designed to ensure that,  
under any conditions including power  
up/down transients, the gate drive from the  
bias circuits cannot exceed the range -3.5V  
to 1V. Furthermore if the negative rail  
experiences a fault condition, such as  
overload or short circuit, the drain supply to  
the FETs will shut down avoiding excessive  
current flow.  
The ZNBG3210/11 are available in QSOP20  
for the minimum in device size. Device  
operating temperature is -40 to 70°C to suit  
a wide range of environmental conditions.  
Drain current setting of the ZNBG3210/11 is  
user selectable over the range 0 to 15mA, this  
FEATURES  
APPLICATIONS  
Provides bias for GaAs and HEMT FETs  
Satellite receiver LNBs  
Drives up to three FETs  
Private mobile radio (PMR)  
Dynamic FET protection  
Cellular telephones  
Drain current set by external resistor  
Regulated negative rail generator  
requires only 2 external capacitors  
Choice in drain voltage  
Wide supply voltage range  
Polarisation switch for LNBs -  
supporting zero volt gate switching  
topology.  
22kHz tone detection for band switching  
Compliant with ASTRA control  
specifications  
QSOP surface mount package  
67-1  
ZNBG3210  
ZNBG3211  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage  
Supply Current  
Input Voltage (VPOL  
-0.6V to 12V  
100mA  
25V Continuous  
0 to 15mA  
Power Dissipation (Tamb= 25°C)  
QSOP20 500mW  
)
Drain Current (per FET)  
(set by RCAL  
)
Operating Temperature  
Storage Temperature  
-40 to 70°C  
-50 to 85°C  
ELECTRICAL CHARACTERISTICS. TEST CONDITIONS  
(Unless otherwise stated):T = 25°C,V =5V,I =10mA (R  
=33k)  
CAL  
amb CC  
D
LIMITS  
SYMBOL PARAMETER  
CONDITIONS  
UNITS  
V
MIN. TYP. MAX.  
VCC  
ICC  
Supply Voltage  
Supply Current ID1 to ID3=0  
5
10  
6
15  
35  
35  
25  
25  
mA  
mA  
mA  
mA  
mA  
ID1=0,ID2 to ID3=10mA, VPOL=14V  
ID2=0,ID1 to ID3=10mA, VPOL=15.5V  
ID1 to ID3=0, ILB=10mA  
25  
25  
16  
16  
ID1 to ID3=0, IHB=10mA  
VSUB  
Substrate  
Voltage  
(Internally generated) ISUB=0  
-3.5  
200  
-3.0  
350  
-2.5  
-2.4  
V
V
I
SUB=-200µA  
Output Noise  
Drain Voltage  
Gate Voltage  
END  
ENG  
CG=4.7nF, CD=10nF  
CG=4.7nF, CD=10nF  
0.02  
0.005 Vpkpk  
Vpkpk  
fO  
Oscillator  
Frequency  
800 kHz  
67-2  
ZNBG3210  
ZNBG3211  
LIMITS  
SYMBOL PARAMETER  
CONDITIONS  
UNITS  
MIN. TYP. MAX.  
GATE CHARACTERISTICS  
IGO  
Output Current  
Range  
-30  
2000  
µA  
IDx  
(mA)  
VPOL  
(V)  
IGOx  
(µA)  
Output Voltage  
VG1O  
VG1L  
VG1H  
Gate 1  
Off  
ID1=0 VPOL=14 IGO1=0  
Low ID1=12 VPOL=15.5 IGO1=-10  
High ID1=8 VPOL=15.5 IGO1=0  
-0.05  
-2.7  
0.4  
0
-2.4  
0.75  
0.05  
-2.0  
1.0  
V
V
V
Output Voltage  
Gate 2 Off  
VG2O  
VG2L  
VG2H  
ID2=0 VPOL=15.5 IGO2=0  
-0.05  
-2.7  
0.4  
0
-2.4  
0.75  
0.05  
-2.0  
1.0  
V
V
V
Low ID2=12 VPOL=14 IGO2=-10  
High ID2=8 VPOL=14 IGO2=0  
Output Voltage  
Gate 3 Low ID3=12  
High ID3=8  
VG3L  
VG3H  
IGO3=-10  
IGO3=0  
-3.5  
0.4  
-2.9  
0.75  
-2.0  
1.0  
V
V
DRAIN CHARACTERISTICS  
ID  
Current  
8
10  
12  
mA  
Current Change  
with VCC VCC= 5 to 10V  
0.5  
0.05  
%/V  
%/°C  
IDV  
IDT  
with Tj  
Tj=-40 to +70°C  
Drain 1 Voltage:  
High  
ZNBG3210  
ZNBG3211  
VD1  
VD2  
VD3  
ID1=10mA, VPOL=15.5V  
ID1=10mA, VPOL=15.5V  
2.0  
1.8  
2.2  
2.0  
2.4  
2.2  
V
V
Drain 2 Voltage:  
High  
ZNBG3210  
ZNBG3211  
ID2=10mA, VPOL=14V  
ID2=10mA, VPOL=14V  
2.0  
1.8  
2.2  
2.0  
2.4  
2.2  
V
V
Drain 3 Voltage:  
High  
ZNBG3210  
ZNBG3211  
ID3=10mA  
ID3=10mA  
2.0  
1.8  
2.2  
2.0  
2.4  
2.2  
V
V
Voltage Change  
with VCC VCC= 5 to 10V  
0.5  
50  
%/V  
ppm  
VDV  
VDT  
with Tj  
Tj=-40 to +70°C  
Leakage Current  
Drain 1  
IL1  
IL2  
VD1=0.5V, VPOL=14V  
VD2=0.5V, VPOL=15.5V  
10  
10  
µA  
µA  
Drain 2  
67-3  
ZNBG3210  
ZNBG3211  
SYMBOL PARAMETER  
LIMITS  
CONDITIONS  
UNITS  
MIN. TYP. MAX.  
TONE DETECTION CHARACTERISTICS  
Filter Amplifier  
IB  
Input Bias Current  
Output Voltage 5  
Output Current 5 VOUT=1.96V, VFIN=2.1V  
0.02  
1.75  
400  
0.07  
1.95  
520  
46  
0.25  
2.05  
650  
R
F1=150kΩ  
µA  
V
VOUT  
IOUT  
GV  
RF1=150kΩ  
µA  
dB  
Voltage Gain  
f=22kHz,VIN=1mV  
Rejection  
Frequency  
8
fR  
V(AC)in=1V p/p sq.w6  
1.0  
7.5  
kHz  
Output Stage  
VLOV  
ILOV  
LOV Volt. Range IL=50mA(LB or HB)  
-0.5  
VCC-1.8 V  
LOV Bias Current  
LB Output Low  
VLOV=0  
0.02  
0.15  
1.0  
µA  
VLOV=0 IL=-10µA  
Enabled 6  
Enabled 7  
VLBL  
-3.5  
-0.01  
-2.75 -2.5  
V
V
0
0.01  
VLOV=3V IL=0  
VLBH  
VHBL  
VHBH  
LB Output High VLOV=0 IL=10mA  
VLOV=3V IL=50mA  
Disabled 6  
-0.025 0  
0.025  
3.1  
V
V
Disabled 7  
2.9  
3.0  
VLOV=0 IL=-10µA  
Disabled 6  
Disabled 7  
HB Output Low  
-3.5  
-2.75 -2.5  
V
V
-0.01  
0
0.01  
VLOV=3V IL=0  
HB Output High VLOV=0 IL=10mA  
VLOV=3V IL=50mA  
Enabled 6  
-0.025 0  
0.025  
3.1  
V
V
Enabled 7  
2.9  
3.0  
POLARITY SWITCH CHARACTERISTICS  
IPOL  
Input Current  
10  
14  
20  
40  
VPOL=25V (Applied via RPOL=10kΩ)  
µA  
VTPOL  
Threshold  
Voltage  
14.75 15.5  
V
VPOL=25V (Applied via RPOL=10kΩ)  
VPOL=25V (Applied via RPOL=10kΩ)  
TSPOL  
Switching Speed  
100  
ms  
NOTES:  
1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB, of  
47nF are required for this purpose.  
2. The characteristics are measured using an external reference resistor RCAL of value 33k wired from pins RCAL to ground.  
3. Noise voltage is not measured in production.  
4.NoisevoltagemeasurementismadewithFETsandgateanddraincapacitorsinplaceonalloutputs. CG, 4.7nF, are connected between  
gate outputs and ground, CD, 10nF, are connected between drain outputs and ground.  
5 . These parameters are linearly related to VCC  
6. These parameters are measured using Test Circuit 1  
7. These parameters are measured using Test Circuit 2  
8. The ZNBG32 series will also reject DiSEqC and other common switching bursts.  
67-4  
ZNBG3210  
ZNBG3211  
TEST CIRCUIT 1  
V2 Characteristics  
Type  
Frequency  
Voltage  
AC source  
22kHz  
350mV p/p enabled  
100mV p/p disabled  
TEST CIRCUIT 2  
V2 Characteristics  
Type  
AC source  
Frequency  
Voltage  
22kHz  
350mV p/p enabled  
100mV p/p disabled  
67-5  
ZNBG3210  
ZNBG3211  
TYPICAL CHARACTERISTICS  
16  
14  
12  
10  
8
Note:- Operation with loads > 200µA  
is not guaranteed.  
Vcc = 5V  
0.0  
-0.5  
-1.0  
-1.5  
-2.0  
-2.5  
-3.0  
Vcc = 5V  
6V  
8V  
10V  
6
4
2
0
0
20  
40  
Rcal (k)  
60  
80  
100  
0
0.2  
0.4  
0.6  
0.8  
1.0  
External Vsub Load (mA)  
JFET Drain Current v Rcal  
Vsub v External Load  
2.4  
2.3  
2.2  
2.1  
2.0  
2.2  
ZNBG3210 ONLY  
ZNBG3211 ONLY  
2.1  
2.0  
1.9  
1.8  
Vcc = 5V  
6V  
Vcc = 5V  
6V  
8V  
10V  
8V  
10V  
2
4
6
8
10  
12  
14  
16  
2
4
6
8
10  
12  
14  
16  
Drain Current (mA)  
Drain Current (mA)  
JFET Drain Voltage v Drain Current  
JFET Drain Voltage v Drain Current  
67-6  
ZNBG3210  
ZNBG3211  
TYPICAL CHARACTERISTICS  
70  
60  
50  
40  
30  
20  
10  
0
VCC = 5V  
VLOV = 0V  
Vcc = 5V  
4
Tamb = 70°C  
Tamb = 25°C  
Tamb = -40°C  
2
0
-2  
-4  
-6  
-8  
100  
1k  
10k  
100k  
1M  
10M  
10M  
1M  
0
10  
20  
30  
40  
50  
Frequency (Hz)  
Load Current (mA)  
Open Loop Gain v Frequency  
LB/HB Offset Voltage v Load Current  
2.0  
VCC = 5V  
180  
150  
120  
90  
1.9  
Tamb = -40 C  
1.8  
1.7  
1.6  
1.5  
60  
Tamb = 25°C  
30  
1.4  
Tamb = 70°C  
0
1.3  
VCC = 5V  
1.2  
100  
1k  
10k  
100k  
1M  
0
10  
20  
30  
40  
50  
Frequency (Hz)  
Load Current (mA)  
Open Loop Phase v Frequency  
LB/HB Dropout Voltage v Load Current  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
VCC = 5V  
VIN=0.1Vpkpk  
Test Circuit 1  
100  
1k  
10k  
100k  
Frequency (Hz)  
Filter Response  
67-7  
ZNBG3210  
ZNBG3211  
FUNCTIONAL DIAGRAM  
FUNCTIONAL DESCRIPTION  
The ZNBG devices provide all the bias requirements for external FETs, including the generation  
of the negative supply required for gate biasing, from the single supply voltage.The diagram  
above shows a single stage from the ZNBG series. The ZNBG3210/11 contains 3 such stages. The  
negative rail generator is common to all devices.  
The drain voltage of theexternal FET QN is set by the ZNBG device to its normal operating voltage.  
This is determined by the on board VD Set reference, for the ZNBG3210 this is nominally 2.2 volts  
whilst the ZNBG3211 provides nominally 2 volts.  
The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier  
driving the gate of the FET adjusts the gate voltage of QN so that the drain current taken matches  
the current called for by an external resistor RCAL  
.
Since the FET is a depletion mode transistor, it is often necessary to drive its gate negative with  
respect to ground to obtain the required drain current. To provide this capability powered from  
a single positive supply, the device includes a low current negative supply generator. This  
generator uses an internal oscillator and two external capacitors, CNB and CSUB  
.
67-8  
ZNBG3210  
ZNBG3211  
The following schematic shows the function of the VPOL input. Only one of the two external FETs  
numberd Q1 and Q2 are powered at any one time, their selection is controlled by the input VPOL  
.
This input is designed to be wired to the power input of the LNB via a high value (10k) resistor.  
With the input voltage of the LNB set at or below 14V, FET Q2 will be enabled. With the input  
voltage at or above 15.5V, FET Q1 will be enabled. The disabled FET has its gate driven to 0V and  
its drain terminal is switched open circuit. FET number Q3 is always active regardless of the  
voltage applied to VPOL  
.
Control Input Switch Function  
Input Sense Polarisation Select  
Vertical  
FET Q2  
14  
volts  
Horizontal  
FET Q1  
15.5 volts  
67-9  
ZNBG3210  
ZNBG3211  
For many LNB applications tone detection and band switching is required. The ZNBG3210/11  
includes the circuitry necessary to detect the presence of a 22kHz tone modulated on the supply  
input to the LNB. Referring to the following schematic diagram, themain elementsofthis detector  
are an op-amp enabling the construction of a Sallen Key filter, a rectifier/smoother and a  
comparator. Full control is given over the centre frequency and bandwidth of the filter by the  
selection of two external resistors and capacitors (one of these resistors, R2, shares the function  
of overvoltage protection of pin VPOL). The detector used in the ZNBG32 series has been  
specifically designed to reject low frequency signals, DiSEqC tone bursts and other common  
interference signals that may be present on the LNB supply input. This has been achieved without  
the need for any additional external components.  
67-10  
ZNBG3210  
ZNBG3211  
APPLICATIONS CIRCUIT  
APPLICATIONS INFORMATION  
The above is a partial application circuit for the ZNBG series showing all external components  
required for appropriate biasing. The bias circuits are unconditionally stable over the full  
temperature range with the associated FETs and gate and drain capacitors in circuit.  
Capacitors CD and CG ensure that residual power supply and substrate generator noise is not  
allowed to affect other external circuits which may be sensitive to RF interference. They also  
serve to suppress any potential RF feedthrough between stages via the ZNBG device. These  
capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are  
recommended however this is design dependent and any value between 1nF and 100nF could  
be used.  
The capacitors CNB and CSUB are an integral part of the ZNBGs negative supply generator. The  
negative bias voltage is generated on-chip using an internal oscillator. The required value of  
capacitors CNB and CSUB is 47nF. This generator produces a low current supply of approximately  
-3 volts. Although this generator is intended purely to bias the external FETs, it can be used to  
power other external circuits via the CSUB pin.  
Resistor RCAL sets the drain current at which all external FETs are operated. If any bias control  
circuit is not required, its related drain and gate connections may be left open circuit without  
affecting the operation of the remaining bias circuits.  
The ZNBG devices have been designed to protect the external FETs from adverse operating  
conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit  
can not exceed the range -3.5V to 1V under any conditions, including powerup and powerdown  
transients. Should the negative bias generator be shorted or overloaded so that the drain current  
of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid  
damage to the FETs by excessive drain current.  
67-11  
ZNBG3210  
ZNBG3211  
The following block diagram shows the main section of an LNB designed for use with the Astra  
series of satellites. The ZNBG3210/11 is the core bias and control element of this circuit. The  
ZNBG provides the negative rail, FET bias control, polarisation switch control, tone detection and  
band switching with the minimum of external components. Compared to other discrete  
component solutions the ZNBG circuit reduces component count and overall size required.  
Single Universal LNB Block Diagram  
Tone detection and band switching is provided on the ZNBG3210/11 devices. The following  
diagrams describes how this feature operates in an LNB and the external components required.  
The presence or absence of a 22kHz tone applied to pin FIN enables one of two outputs, LB and  
HB. A tone present enables HB and tone absent enables LB. The LB and HB outputs are designed  
to be compatible with both MMIC and discrete local oscillator applications, selected by pin LOV  
.
Referring to Figure 1 wiring pin LOV to ground will force LB and HB to switch between -2.6V  
(disabled) and 0V (enabled). Referring to Figure 2 wiring pin LOV to a positive voltage source (e.g.  
a potential divider across VCC and ground set to the required oscillator supply voltage, VOSC) will  
force the LB and HB outputs to provide the required oscillator supply, VOSC, when enabled.  
Tone Detection Function  
LOV  
FIN  
LB  
HB  
LB  
HB  
GND  
22kHz  
Disabled  
Enabled  
Disabled  
Enabled  
Enabled  
Disabled  
Enabled  
Disabled  
-2.6 volts  
GND  
GND  
-2.6 volts  
VOSC  
VOSC  
22kHz  
Note 1  
VOSC  
Note 1  
Note 1: 0 volts in typical LNB applications but dependent on extenal circuits.  
67-12  
ZNBG3210  
ZNBG3211  
APPLICATIONS INFORMATION(cont)  
Figure 1  
LOV grounded  
Figure 2  
LOV connected to VOSC  
67-13  
ZNBG3210  
ZNBG3211  
CONNECTION DIAGRAM  
ORDERING INFORMATION  
Part Number  
ZNBG3210Q20  
ZNBG3211Q20  
Package  
QSOP20  
QSOP20  
Part Mark  
ZNBG3210  
ZNBG3211  
67-14  
ZNBG3210  
ZNBG3211  
PACKAGE DIMENSIONS  
A
IDENTIFICATION  
RECESS  
C
B
FOR PIN 1  
D
PIN No.1  
K
PIN  
Millimetres  
Inches  
MIN  
8.55  
0.635  
1.42  
0.20  
3.81  
1.35  
0.10  
5.79  
0°  
MAX MIN  
MAX  
A
B
C
D
E
F
8.74  
0.337 0.344  
0.025 NOM  
1.52  
0.30  
3.99  
1.75  
0.25  
6.20  
8°  
0.056 0.06  
0.008 0.012  
0.15  
0.157  
0.053 0.069  
0.004 0.01  
0.228 0.244  
G
J
K
0°  
8°  
Zetex plc.  
Fields New Road, Chadderton, Oldham, OL9-8NP, United Kingdom.  
Telephone: (44)161 622 4422 (Sales), (44)161 622 4444 (General Enquiries)  
Fax: (44)161 622 4420  
Zetex GmbH  
Zetex Inc.  
Zetex (Asia) Ltd.  
These are supported by  
agents and distributors in  
major countries world-wide  
Zetex plc 2001  
Streitfeldstraße 19  
D-81673 München  
Germany  
47 Mall Drive, Unit 4  
Commack NY 11725  
USA  
3701-04 Metroplaza, Tower 1  
Hing Fong Road,  
Kwai Fong, Hong Kong  
Telephone:(852) 26100 611  
Fax: (852) 24250 494  
Telefon: (49) 89 45 49 49 0  
Fax: (49) 89 45 49 49 49  
Telephone: (631) 543-7100  
Fax: (631) 864-7630  
http://www.zetex.com  
This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied  
or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or  
services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of  
any product or service.  
DiSEqC is a trademark of EUTELSAT  
68  
ZNBG3210  
ZNBG3211  
This page intentionally left blank  
67-15  
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DIODES

UZNBG3110Q20 [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 15 页

ZETEX

UZNBG3110Q20TA [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 14 页

ZETEX

UZNBG3110Q20TC [ 暂无描述 ] 14 页

DIODES

UZNBG3111Q20 [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 15 页

ZETEX

UZNBG3111Q20TA [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 14 页

ZETEX

UZNBG3111Q20TC [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 14 页

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