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CYW20737S

型号：

CYW20737S

品牌：

CYPRESS[ CYPRESS ]

页数：

24 页

PDF大小：

1338 K

下载PDF手册
CYW20737S  
Bluetooth Low Energy  
System-in-Package (SiP) Module  
The CYW20737S is a compact, highly integrated Bluetooth Low Energy (BLE) system-in-package (SiP) module. The CYW20737S  
SiP includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so only a minimal set of external components is  
needed to create a standalone BLE device.  
The CYW20737S is designed to accelerate time to market. The Bluetooth stack and several application profiles are built into the  
module, allowing customers to focus on their core applications. To further reduce application development time, the CYW20737S  
includes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/load  
cycle. All this, coupled with an ultrasmall form factor and support for a wide voltage range, makes the CYW20737S well suited for  
virtually any Bluetooth Smart application.  
Cypress Part Numbering Scheme  
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,  
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides  
Cypress ordering part number that matches an existing IoT part number.  
Table 1. Mapping Table for Part Number between Broadcom and Cypress  
Broadcom Part Number  
Cypress Part Number  
BCM20737S  
CYW20737S  
Features  
Applications  
■ ARM Cortex-M3 microcontroller unit (MCU)  
■ Embedded 512 Kb EEPROM  
Profiles supported in ROM:  
■ Battery status  
■ Broadcom Serial Control (BSC), SPI, and UART interfaces  
■ FCC and CE compliant  
■ Blood pressure monitor  
■ Find me  
■ RoHS compliant, certified lead- and halogen-free  
■ Moisture Sensitivity Level (MSL) 3 compliant  
■ Heart rate monitor  
■ Proximity  
■ 6.5 mm × 6.5 mm × 1.2 mm Land Grid Array (LGA) 48-pin  
■ Thermometer  
package  
■ Weight scale  
■ Time  
■ Blood glucose monitor  
■ Support for RSA security library  
■ Support for LE Audio  
■ Support for pairing using NFC tags  
Additional profiles supported in RAM:  
■ Blood glucose monitor  
■ Temperature alarm  
■ Location  
■ Other custom profiles  
Cypress Semiconductor Corporation  
Document Number: 002-14888 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 21, 2017  
CYW20737S  
Figure 1. CYW20737S BLE SiP Block Diagram  
VBAT/VDDIO  
CYW20737S  
Antenna  
Bandpass  
Filter  
UART  
SPI/I2C  
CYW20737S  
Bluetooth Low Energy  
System-on-Chip with  
Infrared  
ARM ® Cortex™ M3-based  
Microprocessor Core  
ADC  
24 MHz  
XTAL  
GPIOs  
PWM  
32.768 kHz  
Oscillator  
(optional)  
EEPROM  
512 Kb I2C  
IoT Resources  
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your  
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of  
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software  
updates. Customers can acquire technical documentation and software from the Cypress Support Community website  
(http://community.cypress.com/).  
Document Number: 002-14888 Rev. *C  
Page 2 of 24  
CYW20737S  
Contents  
1. Functional Description .................................................4  
1.1 External Reset .......................................................4  
1.2 32.768 kHz Oscillator ............................................4  
2. Pin Map and Signal Descriptions ................................5  
3. Electrical Specifications ............................................10  
4. RF Specifications .......................................................11  
5. ADC Specifications ....................................................12  
6. Timing and AC Characteristics .................................13  
6.1 SPI Timing ...........................................................13  
6.2 BSC Interface Timing ..........................................14  
6.3 UART Timing .......................................................15  
7. PCB Design and Manufacturing Recommendations 16  
7.1 Pad and Solder Mask Opening Dimensions ........16  
7.2 PCB Layout Recommendations ..........................16  
7.3 PCB Stencil ............................................................... 17  
7.4 Solder Reflow ......................................................17  
8. Packaging and Storage Information .........................18  
9. Mechanical Information .............................................20  
10. Ordering Information ................................................22  
Document History ..........................................................23  
Document Number: 002-14888 Rev. *C  
Page 3 of 24  
CYW20737S  
1. Functional Description  
1.1 External Reset  
External reset timing for the CYW20737S is illustrated in Figure 2.  
Figure 2. External Reset Timing  
Pulse width  
>20 µs  
RESET_N  
Crystal  
warm‐up  
delay:  
~ 5 ms  
Baseband Reset  
Crystal Enable  
Start reading EEPROM and  
firmware boot  
1.2 32.768 kHz Oscillator  
The CYW20737S includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the output to  
create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold (~100 mV).  
The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input  
with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Table 2.  
Table 2. 32 kHz Crystal Oscillator Characteristics  
Parameter  
Output frequency  
Symbol  
Conditions  
Min.  
Typ.  
Max.  
Unit  
Foscout  
Ftol  
Tstartup  
Pdrv  
–
Crystal-dependent  
–
–
–
32.768  
–
–
kHz  
ppm  
µs  
Frequency tolerance  
Start-up time  
100  
–
–
500  
–
Crystal drive level  
For crystal selection  
For crystal selection  
For crystal selection  
0.5  
–
–
µW  
kΩ  
Crystal series resistance  
Crystal shunt capacitance  
Rseries  
Cshunt  
–
70  
1.3  
–
–
pF  
Document Number: 002-14888 Rev. *C  
Page 4 of 24  
 
 
CYW20737S  
2. Pin Map and Signal Descriptions  
The CYW20737S pin map is shown in Figure 3.  
Figure 3. CYW20737S (TOP View)  
The signal name, type, and description of each pin in the CYW20737S is listed in Table 3 on page 6. The symbols shown under  
I/O Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak  
internal pull-up resistor and PD = weak internal pull-down resistor), if any.  
Document Number: 002-14888 Rev. *C  
Page 5 of 24  
 
CYW20737S  
Table 3. Pin Descriptions  
Pin  
Name  
I/O Type  
Description  
Default direction: Input.  
After POR state: Input floating.  
Drain current: 16 mA  
GPIO: P27  
PWM1  
1
I
Alternate function: MOSI (master and slave) for SPI_2  
2
GND  
VBAT  
GND  
GND  
I
GND  
3
Battery supply input.  
4
GND  
GND  
GND  
GND  
GND  
GND  
–
GND  
5
GND  
GND  
6
GND  
GND  
7
GND  
GND  
8
GND  
GND  
9
GND  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Reserved  
GND  
Leave floating  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
I
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
UART_RX  
UART_TX  
GND  
UART_RX. This pin is pulled low through an internal 10 kΩ resistor.  
O, PU  
GND  
I/O, PU  
I/O, PU  
GND  
GND  
UART_TX  
GND  
SCL  
SCL I/O, PU clock signal for an external I2C device  
SDA  
SDA I/O, PU data signal for an external I2C device  
GND  
GND  
GND  
GND  
Default direction: Input.  
After POR state: Input floating.  
This pin is tied to the WP pin of the embedded EEPROM.  
Requires an external 10K pull-up  
25  
GPIO: P1  
I
Test mode control. Pull this pin high to invoke test mode; leave it floating if not used.  
This pin is connected to GND through an internal 10 kΩ resistor.  
26  
27  
TMC  
I
RESET_N  
I/O PU  
Active-low system reset with open-drain output  
Document Number: 002-14888 Rev. *C  
Page 6 of 24  
CYW20737S  
Table 3. Pin Descriptions (Cont.)  
Pin  
Name  
I/O Type  
Description  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
■ A/D converter input  
28  
GPIO: P0  
I
■ Peripheral UART TX (PUART_TX)  
■ MOSI (master and slave) for SPI_2  
■ IR_RX  
■ 60Hz_main  
29  
30  
GND  
GND  
I
GND  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
GPIO: P3  
■ Peripheral UART CTS (PUART_CTS)  
■ SPI_CLK (master and slave) for SPI_2  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
31  
GPIO: P2  
I
■ Peripheral UART RX (PUART_RX)  
■ SPI_CS (slave only) for SPI_2  
■ SPI_MOSI (master only) for SPI_2  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
32  
33  
GPIO: P4  
GPIO: P8  
I
I
■ Peripheral UART RX (PUART_RX)  
■ MOSI (master and slave) for SPI_2.  
■ IR_TX  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions: A/D converter input.  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
■ A/D converter input  
34  
GPIO: P33  
I
■ MOSI (slave only) for SPI_2  
■ Auxiliary clock output (ACLK1)  
■ Peripheral UART RX (PUART_RX)  
Document Number: 002-14888 Rev. *C  
Page 7 of 24  
CYW20737S  
Table 3. Pin Descriptions (Cont.)  
Pin  
Name  
I/O Type  
Description  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
■ A/D converter input  
35  
GPIO: P32  
I
■ SPI_CS (slave only) for SPI_2.  
■ Auxiliary clock output (ACLK0)  
■ Peripheral UART TX (PUART_TX)  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
36  
GPIO: P25  
I
I
■ MISO (master and slave) for SPI_2  
■ Peripheral UART RX (PUART_RX)  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
37  
38  
GPIO: P24  
NC  
■ SPI_CLK (master and slave) for SPI_2  
■ Peripheral UART TX (PUART_TX)  
No Connection (N/C).  
NC  
I
Default Direction: Input  
After POR State: Input Floating  
Drain current: 16 mA  
GPIO: P13  
PWM3  
Alternate function: A/D converter input  
Default direction: Input.  
After POR state: Input floating.  
Drain current: 16 mA  
39  
Alternate functions:  
GPIO: P28  
PWM2  
I
■ A/D converter input  
■ LED1  
■ IR_TX  
Default direction: Input.  
After POR state: Input floating.  
Alternate function: A/D converter input  
GPIO: P14  
PWM2  
I
I
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
40  
GPIO: P38  
GPIO: P15  
■ A/D converter input  
■ MOSI (master and slave) for SPI_2  
■ IR_TX  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
41  
I
■ A/D converter input  
■ IR_RX  
■ 60 Hz_main  
Document Number: 002-14888 Rev. *C  
Page 8 of 24  
CYW20737S  
Table 3. Pin Descriptions (Cont.)  
Pin  
Name  
I/O Type  
Description  
Default direction: Input.  
After POR state: Input floating.  
Drain current: 16 mA  
GPIO: P26  
PWM0  
42  
I
Alternate function: SPI_CS (slave only) for SPI_2  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
GPIO: P12  
XTALO32K  
GPIO: P11  
I
O
I
■ A/D converter input  
■ XTALO32K  
43  
Low-power oscillator (LPO) output.  
Alternate functions:  
P12  
P26  
Default direction: Input.  
After POR state: Input floating.  
Alternate functions:  
■ A/D converter input  
■ XTALI32K  
44  
Low-power oscillator (LPO) input.  
Alternate functions:  
XTALI32K  
I
■ P11  
■ P27  
GND  
45  
46  
47  
48  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
Document Number: 002-14888 Rev. *C  
Page 9 of 24  
CYW20737S  
3. Electrical Specifications  
Absolute maximum ratings are defined in Table 4.  
Table 4. Absolute Maximum Ratings  
Parameter  
Supply power  
Min.  
NA  
–40  
0
Max.  
3.63  
125  
±2  
Unit  
V
Storage temperature  
°C  
%
Voltage ripple  
Power supply (VBAT absolute maximum rating)  
1.62  
3.63  
V
Power for the CYW20737S module is provided by the host through the power pins.  
Table 5. Voltage  
Symbol  
Parameter  
Min.  
1.62  
Typ.  
Max.  
3.63  
Unit  
VBAT  
Battery voltage  
–
V
Table 6. Current Consumption  
Operating Mode  
Condition  
Nominal  
Maximum  
Unit  
Receive  
Transmit  
Sleep  
Receiver and baseband are both operating, 100%  
Transmitter and baseband are both operating, 100%  
Wake in < 5 ms  
24.0  
24.0  
55.0  
2.0  
28.0  
mA  
mA  
µA  
28.0  
60.0  
2.5  
Deep Sleep  
Wake on interrupt  
µA  
Note: All measurements taken at 25°C  
Based on the current measurements in Table 6 on page 10, CYW20737S peak power values are:  
■ RX: 101.6 mW  
■ TX: 101.6 mW  
■ Sleep mode: 217.8 µW  
■ Deep Sleep mode: 9.1 µW  
Document Number: 002-14888 Rev. *C  
Page 10 of 24  
 
 
CYW20737S  
4. RF Specifications  
CYW20737S receiver specifications are defined in Table 7.  
Table 7. Receiver Specifications  
Parameter  
Mode and Conditions  
Min.  
Typ.  
Max.  
Unit  
Frequency range  
–
2402  
–
2480  
MHz  
RX sensitivity (standard)  
Packets: 200  
–
–94  
–
dBm  
Payload: PRBS 9  
Length: 37 Bytes  
Dirty Transmitter: off.  
PER: 30.8%  
Maximum input  
–
–10  
–
–
dBm  
Note: All measurements taken at 3.0V (default voltage)  
RF transmitter specifications are defined in Table 8.  
Table 8. Transmitter Specifications  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Transmitter  
Frequency rangea  
2402  
–20  
–
–
–
2480  
MHz  
dBm  
dBm  
dB  
Output power adjustment range  
Output power  
4
–
–
2
Output power variation  
–
2.5  
LO Performance  
Frequency Drift  
Initial carrier frequency tolerance  
–
–
±150  
kHz  
Frequency drift  
Drift rate  
–
–
–
–
±50  
20  
kHz  
kHz/50 µs  
Frequency Deviation  
Average deviation in payload  
(sequence: 00001111)  
225  
185  
–
–
–
2
275  
–
kHz  
kHz  
MHz  
Average deviation in payload  
(sequence: 10101010)  
Channel spacing  
–
a. This parameter is taken from the Bluetooth 4.0 specification.  
Document Number: 002-14888 Rev. *C  
Page 11 of 24  
 
 
CYW20737S  
5. ADC Specifications  
CYW20737S ADC specifications are defined in Table 9.  
Table 9. ADC Specifications  
Parameter  
Symbol  
Conditions  
Min.  
Typ.  
Max.  
Unit  
Number of input channels  
Channel switching rate  
Input signal range  
–
fch  
Vinp  
–
–
–
–
–
–
9
–
–
133.33  
3.63  
–
-
Kch/s  
V
0
–
Reference settling time  
Input resistance  
Charging refsel  
7.5  
–
–
µs  
Rinp  
Cinp  
Fc  
Effective, single-ended  
500  
–
–
kꢀ  
pF  
Input capacitance  
–
–
–
–
–
5
Conversion rate  
5.859  
5.35  
–
187  
170.7  
kHz  
µs  
Conversion time  
Tc  
–
Resolution  
R
16  
±2  
Bits  
%
Absolute voltage measurement error  
–
Using on–chip ADC  
firmware driver  
–
–
Current  
I
P
Iavdd1p2 + Iavdd3p3  
–
–
–
1.5  
–
1
–
mA  
mW  
nA  
Power  
–
Leakage Current  
Power-up time  
Integral nonlinearity  
Ileakage  
Tpowerup  
INL  
T = 25°C  
–
–
100  
200  
1
–
–
µs  
LSBa  
In the guaranteed  
performance range  
–1  
–
Differential nonlinearity  
DNL  
In the guaranteed  
performance range  
–1  
–
1
LSBa  
a. LSBs are expressed at the 10-bit level.  
Document Number: 002-14888 Rev. *C  
Page 12 of 24  
 
CYW20737S  
6. Timing and AC Characteristics  
6.1 SPI Timing  
SPI interface timing is illustrated in Figure 4 and Figure 5 and defined in Table 10 on page 14.  
Figure 4. SPI Timing—Modes 0 and 2  
6
SPI_CSN  
SPI_CLK  
1
(Mode 0)  
SPI_CLK  
(Mode 2)  
2
3
‐
First Bit  
Second Bit  
Last bit  
Last bit  
‐
SPI_MOSI  
SPI_MISO  
4
5
First Bit  
Not Driven  
Second Bit  
Not Driven  
Figure 5. SPI Timing—Modes 1 and 3  
6
SPI_CSN  
SPI_CLK  
1
(Mode 1)  
SPI_CLK  
(Mode 3)  
2
3
‐
Invalid bit  
Invalid bit  
‐
First bit  
Last bit  
Last bit  
SPI_MOSI  
SPI_MISO  
4
5
Not Driven  
Not Driven  
First bit  
Document Number: 002-14888 Rev. *C  
Page 13 of 24  
 
 
CYW20737S  
Table 10. SPI Interface Timing Specifications  
Reference  
Characteristics  
Min.  
Typ.  
Max.  
1
2
3
4
5
6
Time from CSN asserted to first clock edge  
Master setup time  
1 SCK  
–
100  
∞
1/2SCK  
–
–
Master hold time  
1/2SCK  
–
-
Slave setup time  
1/2 SCK  
–
–
Slave hold time  
1/2 SCK  
SCK  
–
Time from last clock edge to CSN deasserted  
10 SCK  
100  
6.2 BSC Interface Timing  
BSC interface timing is illustrated in Figure 6 and is defined in Table 11.  
Figure 6. BSC Interface Timing  
Table 11. BSC Interface Timing Specifications  
Reference  
Characteristics  
Min.  
Max.  
Unit  
1
2
Clock frequency  
–
100, 400, 800, 1000  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
START condition setup time  
START condition hold time  
Clock low time  
650  
280  
650  
280  
0
–
–
3
4
–
5
Clock high time  
–
6
Data input hold time  
Data input setup time  
STOP condition setup time  
Output valid from clock  
Bus free time  
–
7
100  
280  
–
–
8
–
9
400  
–
10  
650  
Document Number: 002-14888 Rev. *C  
Page 14 of 24  
 
 
CYW20737S  
6.3 UART Timing  
UART timing is illustrated in Figure 7 and defined in Table 12.  
Figure 7. UART Timing  
Table 12. UART Timing Specifications  
Reference  
Characteristics  
Min.  
Max.  
24  
Unit  
Baudout cycles  
ns  
1
2
3
Delay time, UART_CTS_N low to UART_TXD valid  
Setup time, UART_CTS_N high before midpoint of stop bit  
Delay time, midpoint of stop bit to UART_RTS_N high  
–
–
–
10  
2
Baudout cycles  
Document Number: 002-14888 Rev. *C  
Page 15 of 24  
 
 
CYW20737S  
7. PCB Design and Manufacturing Recommendations  
7.1 Pad and Solder Mask Opening Dimensions  
CYW20737S pad and solder mask opening dimensions are defined in Table 13.  
Table 13. Pad and Solder Mask Dimensions  
Pad Type  
Type A  
Pad Dimensions  
0.6 × 0.25  
Solder Mask Opening Dimensions  
Unit  
0.7 × 0.35  
0.65 × 0.4  
0.5 × 0.5  
Type B  
Type C  
0.55 × 0.3  
mm  
0.4 × 0.4  
7.2 PCB Layout Recommendations  
The following layout recommendations are referenced to Figure 8 on page 16.  
■ Connect to system ground from side D of the module (pins 13–22).  
■ The L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape  
to accommodate trace routes.  
■ An L-shaped ground plane is required. If the L-shaped GND plane is located on the top layer of the PCB, do not place components  
on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer.  
■ Antenna efficiency of 31–41% can be achieved based on the layout in Figure 8 on page 16 and the dimensions listed below.  
Following these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommendations  
may reduce the range of the antenna.  
❐ D: 4.5 mm (typical)  
❐ G, H, S: 3 mm (typical)  
❐ L: 3 mm (minimum)  
❐ W: 0.4 mm (typical)  
■ Route signal traces out of the module from side C (between pins 27 and 30) or side D (between pins 16 and 19) of the module.  
Traces can be overlapped to avoid routing through the keep-out area.  
■ Do not route traces from side A or side B.  
Figure 8. PCB Layout Example  
Document Number: 002-14888 Rev. *C  
Page 16 of 24  
 
 
CYW20737S  
7.3 PCB Stencil  
The recommended PCB stencil is shown in Figure 9 (all measurements in mm). Use an unsolder mask to set the module footprint.  
Figure 9. CYW20737S Stencil (Bottom View)  
7.4 Solder Reflow  
The recommended solder reflow profile for the CYW20737S is defined in Figure 10.  
Figure 10. Solder Reflow Profile  
245°C  
217°C  
200°C  
150°C  
Pre‐Heating: 90~120 sec.  
Soldering: 60~90 sec.  
Ti  
Document Number: 002-14888 Rev. *C  
Page 17 of 24  
 
 
CYW20737S  
8. Packaging and Storage Information  
The CYW20737S is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown  
in Figure 11. The storage temperature range is –40°C to +125°C.  
Figure 11. CYW20737S ESD/Moisture Packaging  
The moisture sensitivity label on the CYW20737S shipping bag is shown in Figure 12 on page 19.  
Document Number: 002-14888 Rev. *C  
Page 18 of 24  
 
CYW20737S  
Figure 12. CYW20737S Moisture Sensitivity Label  
Figure 13 shows the location of pin 1 on the CYW20737S relative to its orientation on the tape packaging.  
Figure 13. CYW20737S Tape and Reel Pin 1 Location  
Document Number: 002-14888 Rev. *C  
Page 19 of 24  
 
CYW20737S  
9. Mechanical Information  
Package dimensions for the CYW20737S are shown in Figure 14.  
Figure 14. CYW20737S Package Dimensions  
Additional CYW20737S package dimensions are shown in Figure 15 on page 21.  
Document Number: 002-14888 Rev. *C  
Page 20 of 24  
 
CYW20737S  
Figure 15. CYW20737S Pin Dimensions (Bottom View)  
Document Number: 002-14888 Rev. *C  
Page 21 of 24  
CYW20737S  
10. Ordering Information  
Table 14. Ordering Information  
Part Number  
Package  
Operating Temperature  
Humidity  
CYW20737S  
48-pin LGA  
–40°C to +85°C  
95% max., noncondensing  
Document Number: 002-14888 Rev. *C  
Page 22 of 24  
CYW20737S  
Document History  
Document Title: CYW20737S Bluetooth Low Energy System-in-Package (SiP) Module  
Document Number: 002-14888  
Orig. of  
Change  
Submission  
Date  
Revision  
ECN  
Description of Change  
20737S-DS100-R:  
Initial release  
**  
–
–
09/26/2014  
20737S-DS101-R:  
Updated  
*A  
–
UTSV  
UTSV  
11/06/2015  
09/23/2016  
•
Table 5 on page 14  
Updated to Cypress Template  
Updated Cypress Logo and Copyright.  
*B  
*C  
5444054  
5688156  
AESATMP7 04/21/2017  
Document Number: 002-14888 Rev. *C  
Page 23 of 24  
CYW20737S  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at Cypress Locations.  
®
Products  
PSoC Solutions  
ARM® Cortex® Microcontrollers  
cypress.com/arm  
cypress.com/automotive  
cypress.com/clocks  
cypress.com/interface  
cypress.com/iot  
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6  
Automotive  
Cypress Developer Community  
Clocks & Buffers  
Interface  
Forums | WICED IoT Forums | Projects | Video | Blogs |  
Training | Components  
Internet of Things  
Memory  
Technical Support  
cypress.com/memory  
cypress.com/mcu  
cypress.com/support  
Microcontrollers  
PSoC  
cypress.com/psoc  
cypress.com/pmic  
cypress.com/touch  
cypress.com/usb  
Power Management ICs  
Touch Sensing  
USB Controllers  
Wireless Connectivity  
cypress.com/wireless  
24  
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,  
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries  
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other  
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress  
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to  
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users  
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as  
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation  
of the Software is prohibited.  
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE  
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent  
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any  
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is  
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products  
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or  
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the  
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably  
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,  
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other  
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.  
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in  
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.  
Document Number: 002-14888 Rev. *C  
Revised April 21, 2017  
Page 24 of 24  
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