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CYW3335

型号：

CYW3335

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

157 K

下载PDF手册
CYW3335  
Dual Serial Input PLL with 2.5-GHz Prescalers  
Features  
Applications  
• Operating voltage 2.7V to 5.5V  
• PLL1 and PLL2 operating frequency:  
— 2.5 GHz with prescaler ratios of 32/33 or 64/65  
• Lock detect feature  
The Cypress CYW3335 is a dual serial input PLL frequency  
synthesizer designed to combine the Transmit and Receive RF  
frequency sections of wireless communications systems. Two  
2.5-GHz prescalers, each with pulse swallow capability are in-  
cluded. The device operates from 2.7V and dissipates only  
38 mW.  
µA typical at 3.0V  
• Power-down mode I < 1  
CC  
• 20-pin TSSOP (Thin Shrink Small Outline Package)  
CYW3335 Dual Hi-Lo PLL Block Diagram  
GND (4)  
GND (7)  
V
CC1 (1)  
VCC2 (20)  
VP1 (2)  
FIN1 (5)  
Prescaler  
32/33 or  
64/65  
fp1  
Binary 7-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL1 (3)  
Phase  
Detector  
Charge  
Pump  
FIN1# (6)  
19-Bit  
Latch  
Pwr-dwn  
PLL1  
OSC_IN (8)  
fr fp  
fr1  
fr2  
15-Bit  
Monitor  
Output  
Selector  
Reference Counter  
FO/LD (10)  
20-Bit Latch  
Latch  
Selector  
LE (13)  
DATA (12)  
20-Bit Latch  
Power  
Control  
15-Bit  
Reference Counter  
22-Bit  
Shift  
Reg.  
Cntrl  
CLOCK (11)  
19-Bit  
Latch  
Pwr-dwn  
PLL2  
Phase  
Detector  
Charge  
Pump  
F
IN2 (16)  
Prescaler  
32/33 or  
64/65  
Binary 7-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL2 (18)  
fp2  
F
IN2# (15)  
GND (14)  
GND (9)  
GND (17)  
VP2 (19)  
Pin Configuration  
VCC  
1
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
VP2  
2
VP1  
DOPLL1  
GND  
3
DOPLL2  
GND  
4
FIN  
1
5
FIN2  
FIN1#  
GND  
6
FIN2#  
GND  
LE  
7
OSC_IN  
GND  
8
9
DATA  
CLOCK  
FO/LD  
10  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
February 14, 2000, rev. **  
CYW3335  
VP1  
VCC 2.7–5.5V  
VP2  
µF  
µF  
µF  
10  
10  
10  
µ
F
0.1  
µ
F
0.1  
(1)  
(20)  
VCC2  
VCC  
1
0.1 µF  
100 pF  
100 pF  
0.1 µF  
F
100 p  
100 pF  
(2)  
(19)  
VP1  
VP2  
µF  
F
F
µF  
0.1  
0.1  
100 p  
100 p  
(3)  
(18)  
22 kΩ  
22 kΩ  
2.5  
2.5  
GHz  
VCO  
GHz  
VCO  
DOPLL1  
GND  
DOPLL2  
GND  
3.3 kΩ  
µF  
3.3 KΩ  
F
F
µF  
µF  
µF  
68 p  
68 p  
0.01  
0.001  
0.001  
0.1  
(4)  
(5)  
(6)  
(17)  
(16)  
(15)  
18Ω  
18Ω  
F
18Ω  
51Ω  
18Ω  
1000 p  
F
1000 p  
FIN  
1
FIN2  
18Ω  
18Ω  
51Ω  
RF LO  
IF LO  
FIN1#  
GND  
FIN2#  
GND  
F
100 p  
F
100 p  
(7)  
(8)  
(14)  
(13)  
(12)  
(11)  
2 kΩ  
F
1000 p  
OSC_IN  
GND  
LE  
3 kΩ  
2 kΩ  
51Ω  
(9)  
DATA  
CLOCK  
3 kΩ  
2 kΩ  
(10)  
FO/LD  
3 kΩ  
Figure 1. Application Diagram Example - CYW3335 2.5-GHz Dual Hi/Hi PLL  
2
CYW3335  
Pin Definitions  
Pin  
No.  
Pin  
Pin Name  
Type  
Pin Description  
Power Supply Connection for PLL1 and PLL2: When power is removed from both  
V
1
2
3
P
P
O
CC  
the V 1 and V 2 pins, all latched data is lost.  
CC  
CC  
V 1  
PLL1 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with  
tuning voltages higher than the V of PLL1.  
P
CC  
D PLL1  
PLL1 Charge Pump Output: The phase detector gain is I /2π. Sense polarity can be  
O
P
reversed by setting the FC bit in software (via the Shift Register).  
Analog and Digital Ground Connection: This pin must be grounded.  
Input to PLL1 Prescaler: Maximum frequency 2.5 GHz.  
GND  
4
5
6
G
I
F 1  
IN  
F 1#  
I
Complementary Input to PLL1 Prescaler: A bypass capacitor should be placed as  
IN  
close as possible to this pin and must be connected directly to the ground plane.  
GND  
7
8
G
I
Analog and Digital Ground Connection: This pin must be grounded.  
OSC_IN  
GND  
Oscillator Input: This input has a V /2 threshold and CMOS logic level sensitivity.  
CC  
9
G
O
Reference Ground Connection: This pin must be grounded.  
F /LD  
10  
Lock Detect Pin of PLL1 Section: This output is HIGH when the loop is locked. It is  
multiplexed to the output of the programmable counters or reference dividers in the  
test program mode. (Refer to Table 3 for configuration.)  
O
CLOCK  
11  
I
Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge  
of this signal.  
DATA  
LE  
12  
13  
I
I
Serial Data Input  
Load Enable: On the rising edge of this signal, the data stored in the Shift Register  
is latched into the reference counter and configuration controls, PLL1 or PLL2 depend-  
ing on the state of the control bits.  
GND  
14  
15  
G
I
Analog and Digital Ground Connection: This pin must be grounded.  
F 2#  
Complementary Input to PLL2 Prescaler: A bypass capacitor should be placed as  
IN  
close as possible to this pin and must be connected directly to the ground plane.  
F 2  
16  
17  
18  
I
Input to PLL2 Prescaler: Maximum frequency 2.5 GHz.  
IN  
GND  
G
O
Analog and Digital Ground Connections: This pin must be grounded.  
D PLL2  
PLL2 Charge Pump Output: The phase detector gain is I /2π. Sense polarity can be  
O
P
reversed by setting the FC bit in software (via the Shift Register).  
V 2  
19  
20  
P
P
PLL2 Charge Pump Rail Voltage: This voltage accommodates VCO circuits with  
P
tuning voltages higher than the V of PLL2.  
CC  
V
2
Power Supply Connections for PLL1 and PLL2: When power is removed from both  
CC  
the V 1 and V 2 pins, all latched data is lost.  
CC  
CC  
3
CYW3335  
only. Operation of the device at these or any other conditions  
above those specified in the operating sections of this specifi-  
cation is not implied. Maximum conditions for extended peri-  
ods may affect reliability.  
Absolute Maximum Ratings  
Stresses greater than those listed in this table may cause per-  
manent damage to the device. These represent a stress rating  
Parameter  
or V  
Description  
Power Supply Voltage  
Rating  
Unit  
V
V
–0.5 to +6.5  
CC  
P
V
Output Voltage  
–0.5 to V +0.5  
V
OUT  
OUT  
CC  
I
Output Current  
±15  
+260  
mA  
°C  
°C  
T
T
Lead Temperature  
Storage Temperature  
L
–55 to +150  
STG  
Always turn off power before adding or removing devices from  
system.  
Handling Precautions  
Devices should be transported and stored in antistatic con-  
tainers.  
Protect leads with a conductive sheet when handling or trans-  
porting PC boards with devices.  
These devices are static sensitive. Ensure that equipment and  
personnel contacting the devices are properly grounded.  
If devices are removed from the moisture protective bags for  
more than 36 hours, they should be baked at 85°C in a mois-  
ture free environment for 24 hours prior to assembly in less  
than 24 hours.  
Cover workbenches with grounded conductive mats.  
Recommended Operating Conditions  
Parameter  
Description  
Power Supply Voltage  
Test Condition  
Rating  
Unit  
V
V
,
2.7 to 5.5  
V
CC1  
CC2  
V
Charge Pump Voltage  
Operating Temperature  
V
to +5.5  
V
P
CC  
T
Ambient air at 0 CFM flow  
–40 to +85  
°C  
A
4
CYW3335  
Electrical Characteristics: V = V = 2.7V to 5.5V, T = –40°C to +85°C, Unless otherwise specified  
CC  
P
A
Parameter  
Description  
Test Condition  
Pin  
Min.  
Typ.  
Max.  
Unit  
I
Power Supply Current  
PLL1 + PLL2  
V
1 = V 2 = 3.0V  
V
V
1, V  
2
2
14  
mA  
CC  
CC  
CC  
CC  
CC  
CC  
µA  
I
Power-down Current  
Power-down, V = 3.0V  
1, V  
1
25  
2500  
45  
PD  
CC  
CC  
F 1, F 2 Operating Frequency  
F 1, F 2  
100  
2
MHz  
MHz  
MHz  
IN  
IN  
IN  
IN  
F
Oscillator Input Frequency  
OSC_IN  
OSC  
Fφ  
Maximum Phase Detector  
Frequency  
10  
[1]  
[2]  
PF 1,  
Input Sensitivity  
V
V
V
= 2.7V  
F 1, F 2  
–15  
–10  
–15  
4
4
4
dBm  
dBm  
dBm  
IN  
CC  
CC  
CC  
IN  
IN  
PF 2  
IN  
= 5.5V  
PF 1,  
= 2.7V to 5.5V  
F 1, F 2  
IN IN  
IN  
PF 2  
IN  
V
Oscillator Input Sensitivity  
Oscillator Input Current  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
High level Output Voltage  
Low Level Output Voltage  
V
V
= 3.0V  
= 3.0V  
OSC_IN  
0.5  
V
P–P  
OSC  
CC  
CC  
I , I  
–100  
100  
µA  
V
IH IL  
V
DATA,  
CLOCK,  
LE  
V
V
* 0.8  
CC  
IH  
V
V
V
* 0.3  
CC  
V
IL  
µA  
µA  
V
I
I
–10  
–10  
* 0.8  
0.5  
0.5  
10  
10  
IH  
IL  
V
V
V
= 3.0V, V = 1 mA  
F /LD  
O
OH  
CC  
CC  
I
CC  
V
* 0.2  
CC  
V
OL  
ID  
ID  
ID  
ID  
ID High, Source Current  
= V = 3.0V,  
D PLL1  
–3.8  
–1  
3.8  
1
mA  
mA  
mA  
mA  
%
OH(SO)  
OL(SO)  
OH(SI)  
OL(SI)  
O
P
O
D
= V /2  
D PLL2  
O
P
O
ID Low, Source Current  
O
ID High, Sink Current  
O
ID Low, Sink Current  
O
∆ID  
ID Charge Pump Sink  
V
= V = 3.0V,  
3
15  
O
O
CC  
P
and Source Mismatch  
D = V /2  
O P  
[IID  
I – IID  
I]/  
O(SI)  
O(SO)  
[1/2*{IID  
]I+IID  
I}]*100%  
O(SI)  
O(SO)  
[3]  
%
ID vs T  
Charge Pump Current  
–40°C<T<85°C  
V
= V /2  
5
O
DO  
P
Variation vs Temperature  
nA  
I
High Impedance Leakage  
Current  
V
= V = 3.0V,  
±2.5  
OFF  
CC  
P
Loop locked, between reference  
spikes  
Notes:  
1. 2.0 GHz < FIN < 2.5 GHz.  
2. FIN < 2.0 GHz.  
3. IDOvs T; Charge pump current variation vs. temperature.  
[IIDO(SI)@TI - IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and  
[IIDO(SO)@TI - IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.  
5
CYW3335  
Timing Waveforms  
Key:  
FC Bit HIGH  
FC Bit LOW  
Increasing  
Voltage  
(Refer to  
for meaning of FC bit.)  
Table 2  
Increasing Frequency  
VCO Characteristics  
Phase Comparator Sense  
Phase Detector Output Waveform  
FR  
FP  
tw  
tw  
LD  
D
Charge Pump Output Current Waveform  
O
FR  
FP  
tw  
tw  
Do  
IDO  
Three-state  
6
CYW3335  
Timing Waveforms (continued)  
Serial Data Input Timing Waveform  
[4, 5, 6, 7]  
//  
//  
//  
//  
PD = MSB  
PRE  
B1  
A7  
CNT2  
CNT1 = LSB  
DATA  
CLOCK  
//  
//  
//  
t3  
t4  
t5  
t2  
t1  
LE  
//  
Serial Data Input  
Data is input serially using the DATA, CLOCK, and LE pins.  
Two control bits direct data into the locations given in Table 1.  
Table 1. Control Configuration  
CNT1  
CNT2  
Function  
0
0
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector  
polarity, set current in PLL2, set PLL2 three-state, set monitor selector to PLL2.  
0
1
1
1
0
1
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector  
polarity, set current in PLL1, set PLL1 three-state, set monitor selector to PLL1  
Program Counter for PLL2:A = 0 to 63, B = 3 to 2047, set PLL2 prescaler ratio, set power-  
down to PLL2.  
Program Counter for PLL1:A = 0 to 63, B = 3 to 2047, set PLL1 prescaler ratio, set power-  
down to PLL1.  
Notes:  
4. t1–t5 = 50 µs > t > 0.5 µs.  
5. CLOCK may remain HIGH after latching in data.  
6. DATA is shifted in with the MSB first.  
7. For DATA definitions, refer to Table 2.  
7
CYW3335  
[8]  
Table 2. Shift Register Configuration  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22  
Reference Counter and Configuration Bits  
CNT1CNT2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 FC IDO TS LD FO  
Programmable Counter bits  
CNT1CNT2 A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PRE PD  
Bit(s) Name  
CNT1, CNT2  
R1–R15  
FC  
Function  
Control Bits: Directs programming data to PLL1 or PLL2.  
Reference Counter Setting Bits: 15 bits, R = 3 to 32767.  
[9]  
Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function).  
Charge Pump Setting Bit: ID HIGH = 3.8 mA, ID LOW = 1 mA.  
IDO  
O
O
TS  
Three-state Bit: Three-states the D output for PLL2 and PLL1 when HIGH.  
O
LD  
Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when  
locked. When not locked, this pin is LOW.  
FO  
Frequency Out:This bit can be set to read out reference or programmable divider at the LD pin for test purposes.  
Prescaler Divide Bit: For PLL1 and PLL2: LOW = 32/33 and HIGH = 64/65.  
PRE  
PD  
Power-down:LOW = power-up and HIGH = power-down. F is at a high-impedance state, respective B counter  
IN  
is disabled, forces three-state at D outputs and phase comparators are disabled. The reference counter is  
O
disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be input and latched  
in the power-down state.  
A1–A7  
Swallow Counter Divide Ratio: A = 0 to 63 for both PLL1 and PLL2.  
[9]  
B1–B11  
Programmable Counter Divide Ratio: B = 3 to 2047.  
Table 3. F /LD Pin Truth Table  
O
FO (Bit 22)  
LD (Bit 21)  
PLL1  
PLL2  
PLL1  
PLL2  
F /LD Pin Output State  
O
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
0
0
1
1
X
X
X
X
0
1
1
0
1
0
1
0
0
1
1
1
0
1
Disable  
PLL2 Lock Detect  
PLL1 Lock Detect  
PLL1/PLL2 Lock Detect  
PLL2 Reference Divider Output  
PLL1 Reference Divider Output  
PLL2 Programmable Divider Output  
PLL1 Programmable Divider Output  
PLL2 Counter Reset  
PLL1 Counter Reset  
PLL1/PLL2 Counter Reset  
Notes:  
8. The MSB is loaded in first.  
9. Low count ratios may violate frequency limits of the phase detector.  
8
CYW3335  
[10]  
Table 4. 7-Bit Swallow Counter (A) Truth Table  
Divide Ratio A  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
PLL1  
0
X
X
:::  
X
X
0
0
0
0
0
0
0
0
0
0
0
1
1
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
62  
63  
PLL2  
0
1
1
1
1
1
1
X
X
:::  
X
X
0
0
0
0
0
0
0
0
0
0
0
1
1
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
62  
63  
1
1
1
1
1
1
[11]  
Table 5. 11-Bit Programmable Counter (B) Truth Table  
Divide Ratio B  
B11  
0
B10  
0
B9  
0
B8  
0
B7  
0
B6  
0
B5  
0
B4  
0
B3  
B2  
1
B1  
1
3
4
0
1
0
0
0
0
0
0
0
0
0
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
2046  
2047  
1
1
1
1
1
1
1
1
1
1
1
[11]  
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table  
Divide Ratio R  
R15 R14 R13 R12 R11 R10  
R9  
0
R8  
0
R7  
0
R6  
0
R5  
R4  
0
R3  
0
R2  
1
R1  
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
32766  
32767  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[12]  
Package  
Ordering Code  
CYW3335  
Name  
Package Type  
TR  
ZI  
20-pin TSSOP (0.173” wide) Tape and Reel Option  
Notes:  
10. B is greater than or equal to A.  
11. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:  
fvco = {(P * B) + A} * fosc / R where (A < B)  
fvco: Output frequency of the external VCO.  
fosc: The crystal reference oscillator frequency.  
A: Preset divide ratio of the 7-bit swallow counter (0 to 127).  
B: Preset ratio of the 11-bit programmable counter (3 to 2047).  
P: Preset divide ratio of the dual modulus prescaler (64/65 or 128/129).  
R: Preset ratio of the 14-bit programmable reference counter (3 to 16383).  
The divide ratio N = (P * B) + A.  
12. Operating temperature range: –40°C to +85°C.  
Document #: 38-00922  
9
CYW3335  
Package Diagram  
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)  
Physical Dimensions In Millimeters  
20 Lead (0.173" Wide) TSSOP Package Order Number X  
20" clear antistatic tubes, 76 units/tube  
JEDEC Outline MO-153  
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
厂商 型号 描述 页数 下载

CYPRESS

 		CYW134MOXC 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

CYPRESS

 		CYW134MOXCT 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

CYPRESS

 		CYW134SOXC 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

CYPRESS

 		CYW134SOXCT 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

SPECTRALINEAR

 		CYW137OXC FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ] 8 页

SPECTRALINEAR

 		CYW137OXCT FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ] 8 页

SILICON

 		CYW150 [ 440BX AGPset Spread Spectrum Frequency Synthesizer ] 15 页

SILICON

 		CYW150OXC [ 440BX AGPset Spread Spectrum Frequency Synthesizer ] 15 页

SILICON

 		CYW150OXCT [ 440BX AGPset Spread Spectrum Frequency Synthesizer ] 15 页

CYPRESS

 		CYW15G0101DXB 单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ] 39 页

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