ZXLD1601
APPLICATIONS
Setting output voltage
1) PWM output voltage adjustm ent (analogue m ode)
When connected as shown in the typical application During this m ode of operation the device operation is
circuit, the ZXLD1601 will produce a nom inal default continuous, providing a low ripple output voltage
output of between 26V and 28V. This is set by the (VOUT) directly proportional to the duty cycle (D) of the
internal potential divider com prising of resistors R1 logic signal applied to the EN pin according to the
and R2. (See device block diagram ).
relationship:
Th e in te rn a l p o te n tia l d ivid e r n e tw o rk R1/R2 is
accessible at the FB pin and can be shunted by m eans
of external resistors to set different nom inal output
voltages. The potential divider defines output voltage
according to the relationship:
V
OUT = D x VOUT(nom )
Square wave signals applied to the EN pin, for
exam ple, will turn the device on and produce a nom inal
regulated output of 13.5V.
The ZXLD1601 contains a tim ing circuit that switches
the device on a few m icroseconds after the application
of a rising edge to EN and turns it back off again
nom inally 120µs after the falling edge of EN. For
continuous PWM m ode operation, the frequency of the
control signal m ust therefore be m aintained above
10kHz at all tim es, to prevent the internal delay circuit
from tim ing out and switching the device into standby
m ode. The m axim um frequency applied to EN should
be lim ited to 100kHz to m inim ize errors due to internal
switching delays
R2
⎛
⎞
⎟
⎜
VOUT = VFB 1 +
⎝
R1⎠
where VFB = 1.025V.
When using external resistors, these should be chosen
with lower values than the internal resistors to
m inim ize errors caused by the device to device
variation in absolute value of the internal resistors
( 30% m ax). The internal resistors have high values in
order to m inim ize these errors.
2) PWM output voltage adjustm ent (gated m ode)
Re q u ire d
Ext e rn a l
Ext e rn a l re s is t o r
o u t p u t vo lt a g e re s is t o r a cro s s a cro s s R2
R1
This m ethod of adjustm ent can be used in applications
where the output ripple is less im portant than the
supply current. The m ethod of adjustm ent is the sam e
as in 1) above, however, during this m ode of operation,
the device is gated on and off, providing an average
output voltage (VOUT) directly proportional to the duty
cycle (D) of the logic signal applied to the EN pin
according to the relationship:
5V
43K⍀
130K⍀
487K⍀
649K⍀
649K⍀
620K⍀
1.07M⍀
12V
18V
21V
25V
28V
56K⍀
43K⍀
VOUT(AVG) = D x VOUT(nom )
34.8K⍀
27K⍀
The ripple on this voltage will be determ ined by the size
of the output capacitor.
The output voltage can be adjusted all the way down to
the input voltage by either m ethod of PWM control, but
for best results, the duty cycle range should be kept
within the specified range. Lower duty cycles will result
in increased output ripple and non-linearity in the
relationship between duty cycle and output voltage. If a
greater control range is required, the nom inal output
can be reduced by the use of external resistors before
the PWM signal is applied.
40.2K⍀
The following table gives suggested values for various
output voltages.
Once the nom inal output voltage has been set, it can be
adjusted to a lower value by applying a pulse width
m odulated (PWM) control signal to the EN pin, using
one of the two m ethods described below.
Minim izing output voltage ripple
PWM adjustm ent perm its the device to be turned on
and the output voltage set by a single logic signal
applied to the EN pin. No external resistors are
required and the am plitude of the control signal is not
critical, providing it conform s to the lim its defined in
the electrical characteristics.
For applications requiring lower output ripple it m ay be
necessary to add a sm all ceram ic capacitor in parallel
with R2. A value of 4.7pF is suitable for m ost output
ranges.
ISSUE 3 - AUGUST 2004
S E M IC O N D U C T O R S
8
