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CYWUSB6935

PRELIMINARY

WirelessUSB™ LR 2.4-GHz DSSS Radio SoC

1.0

Features

2.0

Functional Description

• 2.4-GHz radio transceiver

The CYWUSB6935 transceiver is a single-chip 2.4-GHz Direct

Sequence Spread Spectrum (DSSS) Gaussian Frequency

Shift Keying (GFSK) baseband modem radio that connects

directly to a microcontroller.

The CYWUSB6935 is offered in an industrial temperature

range 48-pin QFN, 28-pin SOIC, and a commercial temper-

ature range 48-pin QFN.

• Operates in the unlicensed Industrial, Scientific, and

Medical (ISM) band (2.4 GHz–2.483 GHz)

• –95-dBm receive sensitivity

• Up to 0dBm output power

• Range of up to 50 meters or more

• Data throughput of up to 62.5 kbits/sec

• Highly integrated low cost, minimal number of external

3.0

Applications

components required

• Building/Home Automation

— Climate Control

— Lighting Control

— Smart Appliances

— On-Site Paging Systems

— Alarm and Security

• Industrial Control

— Inventory Management

— Factory Automation

— Data Acquisition

• Dual DSSS reconfigurable baseband correlators

• SPI microcontroller interface (up to 2-MHz data rate)

• 13-MHz input clock operation

• Low standby current < 1 µA

• Integrated 32-bit Manufacturing ID

• Operating voltage from 2.7V to 3.6V

• Operating temperature from –40° to 85°C

• Offered in a small footprint 48 QFN or cost saving 28

SOIC

• Automatic Meter Reading (AMR)

• Transportation

— Diagnostics

— Remote Keyless Entry

• Consumer / PC

—Locator Alarms

— Presenter Tools

— Remote Controls

— Toys

DIOVAL

DIO

GFSK

DSSS

RFOUT

RFIN

SERDES

M odulator

IRQ

Baseband

A

SS

SCK

DSSS

Baseband

B

Digital

M ISO

M OSI

SERDES

B

GFSK

Dem odulator

RESET

PD

Synthesizer

Figure 3-1. CYWUSB6935 Simplified Block Diagram

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document 38-16008 Rev. **

Revised February 10, 2004

CYWUSB6935

PRELIMINARY

Channel 2x Oversampled, and 32 chips/bit Single Channel

Dual Data Rate (DDR).

3.1

Applications Support

The CYWUSB6935 is supported by both the CY3632

WirelessUSB Development Kit and the CY3635 WirelessUSB

N:1 Development Kit. The development kit provides all of the

materials and documents needed to cut the cord on multipoint

to point and point to point low bandwidth high node density

applications including four small form-factor sensor boards

and a hub board that connect to WirelessUSB LR RF module

boards, comprehensive WirelessUSB protocol code examples

and all of the associated schematics, gerber files and bill of

materials. The WirelessUSB N:1 Development Kit is also

supported by the WirelessUSB Listener Tool.

4.3.1

64 chips/bit Single Channel

The baseband supports a single data stream operating at

15.625 kbits/sec. The advantage of selecting this mode is its

ability to tolerate a noisy environment. This is because the

15.625 kbits/sec data stream utilizes the longest PN Code

resulting in the highest probability for recovering packets over

the air. This mode can also be selected for systems requiring

data transmissions over longer ranges.

4.3.2

32 chips/bit Dual Channel

4.0

Functional Overview

The baseband supports two non-simultaneous data streams

each operating at 31.25 kbits/sec.

The CYWUSB6935 provides a complete WirelessUSB LR SPI

to antenna radio modem. The CYWUSB6935 is designed to

implement wireless devices operating in the worldwide 2.4-

GHz Industrial, Scientific, and Medical (ISM) frequency band

(2.400GHz - 2.4835GHz). It is intended for systems compliant

with world-wide regulations covered by ETSI EN 301 489-1

V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries);

FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB

STD-T66 (Japan).

4.3.3

32 chips/bit Single Channel 2x Oversampled

The baseband supports a single data stream operating at

31.25 kbits/sec that is sampled twice as much as the other

modes. The advantage of selecting this mode is its ability to

tolerate a noisy environment.

4.3.4

32 chips/bit Single Channel Dual Data Rate (DDR)

The CYWUSB6935 contains a 2.4-GHz radio transceiver, a

GFSK modem and a dual DSSS reconfigurable baseband.

The radio and baseband are both code- and frequency-agile.

Forty-nine spreading codes selected for optimal performance

(Gold codes) are supported across 78 1-MHz channels

yielding a theoretical spectral capacity of 3822 channels. The

CYWUSB6935 supports a range of up to 50 meters or more.

The baseband spreads bits in pairs and supports a single data

stream operating at 62.5 kbits/sec.

4.4

Serializer/Deserializer (SERDES)

data Serializer/Deserializer

CYWUSB6935 provides

a

(SERDES), which provides byte-level framing of transmit and

receive data. Bytes for transmission are loaded into the

SERDES and receive bytes are read from the SERDES via the

SPI interface. The SERDES provides double buffering of

transmit and receive data. While one byte is being transmitted

by the radio the next byte can be written to the SERDES data

register insuring there are no breaks in transmitted data.

4.1

2.4-GHz Radio

The receiver and transmitter are a single-conversion low-Inter-

mediate Frequency (low-IF) architecture with fully integrated

IF channel matched filters to achieve high performance in the

presence of interference. An integrated Power Amplifier (PA)

provides an output power control range of 30 dB in seven

steps.

Both the receiver and transmitter integrated Voltage

Controlled Oscillator (VCO) and synthesizer have the agility to

cover the complete 2.4-GHz GFSK radio transmitter ISM

band. The VCO loop filter is also integrated on-chip.

After a receive byte has been received it is loaded into the

SERDES data register and can be read at any time until the

next byte is received, at which time the old contents of the

SERDES data register will be overwritten.

4.5

Application Interfaces

CYWUSB6935 has a fully synchronous SPI slave interface for

connectivity to the application MCU. Configuration and byte-

oriented data transfer can be performed over this interface. An

interrupt is provided to trigger real time events.

An optional SERDES Bypass mode (DIO) is provided for appli-

cations that require a synchronous serial bit-oriented data

path. This interface is for data only.

4.2

GFSK Modem

The transmitter uses a DSP-based vector modulator to

convert the 1-MHz chips to an accurate GFSK carrier.

The receiver uses a fully integrated Frequency Modulator (FM)

detector with automatic data slicer to demodulate the GFSK

signal.

4.6

Clocking and Power Management

4.3

Dual DSSS Baseband

A 13-MHz crystal is directly connected to X13IN and X13

without the need for external capacitors. The CYWUSB6935

has a programmable trim capability for adjusting the on-chip

load capacitance supplied to the crystal. The Radio Frequency

(RF) circuitry has on-chip decoupling capacitors. The

CYWUSB6935 is powered from a 2.7V to 3.6V DC supply. The

CYWUSB6935 can be shutdown to a fully static state using the

PD pin.

Data is converted to DSSS chips by a digital spreader. De-

spreading is performed by an oversampled correlator. The

DSSS baseband cancels spurious noise and assembles

properly correlated data bytes.

The DSSS baseband has four operating modes: 64 chips/bit

Single Channel, 32 chips/bit Dual Channel, 32 chips/bit Single

Document 38-16008 Rev. **

Page 2 of 32

CYWUSB6935

PRELIMINARY

Below are the requirements for the crystal to be directly

5.0

5.1

Application Interfaces

SPI Interface

connected to X13IN and X13:

• Nominal Frequency: 13 MHz

• Operating Mode: Fundamental Mode

• Resonance Mode: Parallel Resonant

• Frequency Stability: ± 30 ppm

• Series Resistance: ≤ 100 ohms

• Load Capacitance: 10 pF

The CYWUSB6935 has a four-wire SPI communication

interface between an application MCU and one or more slave

devices. The SPI interface supports single-byte and multi-byte

serial transfers. The four-wire SPI communications interface

consists of Master Out-Slave In (MOSI), Master In-Slave Out

(MISO), Serial Clock (SCK), and Slave Select (SS).

The SPI receives SCK from an application MCU on the SCK

pin. Data from the application MCU is shifted in on the MOSI

pin. Data to the application MCU is shifted out on the MISO

pin. The active-low Slave Select (SS) pin must be asserted to

initiate a SPI transfer.

The application MCU can initiate a SPI data transfer via a

multi-byte transaction. The first byte is the Command/Address

byte, and the following bytes are the data bytes as shown in

Figure 5-1 through Figure 5-4. The SS signal should not be

deasserted between bytes. The SPI communications is as

follows:

• Drive Level: 10uW–100 uW

4.7

Receive Signal Strength Indicator (RSSI)

The RSSI register (Reg 0x22) returns the relative signal

strength of the ON-channel signal power and can be used to:

1) determine the connection quality, 2) determine the value of

the noise floor, and 3) check for a quiet channel before trans-

mitting.

The internal RSSI voltage is sampled through a 5-bit analog-

to-digital converter (ADC). A state machine controls the

conversion process. Under normal conditions, the RSSI state

machine initiates a conversion when an ON-channel carrier is

detected and remains above the noise floor for over 50uS. The

conversion produces a 5-bit value in the RSSI register (Reg

0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22,

bit 5). The state machine then remains in HALT mode and

does not reset for a new conversion until the receive mode is

toggled off and on. Once a connection has been established,

the RSSI register can be read to determine the relative

connection quality of the channel. A RSSI register value lower

than 10 indicates that the received signal strength is low, a

value greater than 28 indicates a strong signal level.

To check for a quiet channel before transmitting, first set up

receive mode properly and read the RSSI register (Reg 0x22).

If the valid bit is zero, then force the Carrier Detect register

(Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait

greater than 50uS and read the RSSI register again. Next,

clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn

the receiver OFF. Measuring the noise floor of a quiet channel

is inherently a 'noisy' process so, for best results, this

procedure should be repeated several times (~20) to compute

an average noise floor level. A RSSI register value of 0-10

indicates a channel that is relatively quiet. A RSSI register

value greater than 10 indicates the channel is probably being

used. A RSSI register value greater than 28 indicates the

presence of a strong signal.

• Command Direction (bit 7) = “0” Enables SPI read transac-

tion. A “1” enables SPI write transactions.

• Command Increment (bit 6) = “1” Enables SPI auto address

increment. When set, the address field automatically incre-

ments at the end of each data byte in a burst access, oth-

erwise the same address is accessed.

• Six bits of address.

• Eight bits of data.

The SPI communications interface has a burst mechanism,

where the command byte can be followed by as many data

bytes as desired. A burst transaction is terminated by

deasserting the slave select (SS = 1).

The SPI communications interface single read and burst read

sequences are shown in Figure 5-2 and Figure 5-3, respec-

tively.

The SPI communications interface single write and burst write

sequences are shown in Figure 5-4 and Figure 5-5, respec-

tively.

Document 38-16008 Rev. **

Page 3 of 32

CYWUSB6935

PRELIMINARY

Byte 1

Byte 1+N

[7:0]

Bit #

7

6

[5:0]

Bit Name

DIR

INC

Address

Data

Figure 5-1. SPI Transaction Format

S C K

S S

c m d

a d d r

IN C

^D0^IR

0

M O S I

M IS O

A 5

A 4

A 3

A 2

A 1

A 0

d a ta to m c u

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

Figure 5-2. SPI Single Read Sequence

S C K

S S

cm d

addr

IN C

^D0^IR

1

A 5

A 4

A 3

A 2

A 1

A 0

M O S I

M IS O

data to m cu

1+N

1

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

Figure 5-3. SPI Burst Read Sequence

SCK

SS

cmd

addr

data from mcu

INC

^D1^IR

0

MOSI

MISO

D0

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

Figure 5-4. SPI Single Write Sequence

SCK

SS

cmd

addr

data from mcu

1+N

1

INC

^D1^IR

1

MOSI

MISO

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

A5

A4

A3

A2

A1

A0

Figure 5-5. SPI Burst Write Sequence

Document 38-16008 Rev. **

Page 4 of 32

CYWUSB6935

PRELIMINARY

the data as shown in Figure 5-6. In transmit mode, DIO and

DIOVAL are sampled on the falling edge of the IRQ, which

clocks the data as shown in Figure 5-7. The application MCU

samples the DIO and DIOVAL on the rising edge of IRQ.

5.2

DIO Interface

The DIO communications interface is an optional SERDES

bypass data-only transfer interface. In receive mode, DIO and

DIOVAL are valid after the falling edge of IRQ, which clocks

IRQ

DIOVAL

v0

d0

v1

d1

v2

d2

v3

d3

v4

d4

v5

d5

v6

v7

v8

v9

v10

d10

v11

d11

v12

d12

v13

d13

v14

d14

v...

d...

data to mcu

DIO

d6

d7

d8

d9

Figure 5-6. DIO Receive Sequence

IRQ

DIOVAL

DIO

v8

v9

v10

v11

d11

v12

d12

v13

d13

v14

d14

v...

d...

v0

v1

v2

d2

v3

d3

v4

d4

v5

v6

v7

data from mcu

d8

d9

d10

d0

d1

d5

d6

d7

Figure 5-7. DIO Transmit Sequence

interrupt indicates that the oscillator has started, and that the

5.3

Interrupts

device is ready to receive SPI transfers.

The CYWUSB6935 features three sets of interrupts: transmit,

received, and a wake interrupt. These interrupts all share a

single pin (IRQ), but can be independently enabled/disabled.

In transmit mode, all receive interrupts are automatically

disabled, and in transmit mode all receive interrupts are

automatically disabled. However, the contents of the enable

registers are preserved when switching between transmit and

receive modes.

The wake interrupt is enabled by setting bit 0 of the Wake

Enable register (Reg 0x1C, bit 0=1). Whether or not a wake

interrupt is pending is indicated by the state of bit 0 of the Wake

Status register (Reg 0x1D, bit 0). Reading the Wake Status

register (Reg 0x1D) clears the interrupt.

5.3.2

Transmit Interrupts

Interrupts are enabled and the status read through 6 registers:

Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status

(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit

Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake

Status (Reg 0x1D).

If more than 1 interrupt is enabled at any time, it is necessary

to read the relevant interrupt status register to determine which

event caused the IRQ pin to assert. Even when a given

interrupt source is disabled, the status of the condition that

would otherwise cause an interrupt can be determined by

reading the appropriate interrupt status register. It is therefore

possible to use the devices without making use of the IRQ pin

at all. Firmware can poll the interrupt status register(s) to wait

for an event, rather than using the IRQ pin.

Four interrupts are provided to flag the occurrence of transmit

events. The interrupts are enabled by writing to the Transmit

Interrupt Enable register (Reg 0x0D), and their status may be

determined by reading the Transmit Interrupt Status register

(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary

to read the Transmit Interrupt Status register (Reg 0x0E) to

determine which event caused the IRQ pin to assert.

The function and operation of these interrupts are described in

detail in Section 7.0.

5.3.3

Receive Interrupts

Eight interrupts are provided to flag the occurrence of receive

events, four each for SERDES A and B. In 64 chips/bit and 32

chips/bit DDR modes, only the SERDES A interrupts are

available, and the SERDES B interrupts will never trigger,

even if enabled. The interrupts are enabled by writing to the

Receive Interrupt Enable register (Reg 0x07), and their status

may be determined by reading the Receive Interrupt Status

register (Reg 0x08). If more than one interrupt is enabled, it is

necessary to read the Receive Interrupt Status register (Reg

0x08) to determine which event caused the IRQ pin to assert.

The polarity of all interrupts can be set by writing to the Config-

uration register (Reg 0x05), and it is possible to configure the

IRQ pin to be open drain (if active low) or open source (if active

high).

5.3.1

Wake Interrupt

When the PD pin is low, the oscillator is stopped. After PD is

deasserted, the oscillator takes time to start, and until it has

done so, it is not safe to use the SPI interface. The wake

The function and operation of these interrupts are described in

detail in Section 7.0.

Document 38-16008 Rev. **

Page 5 of 32

CYWUSB6935

PRELIMINARY

6.0

Application Examples

LDO/

3.3 V

0.1µF

DC2DC

+

-

Battery

PCB Trace

Inverted “F”

Antenna

(PIFA)

Vcc

RESET

27 pF

1.0 pF

RFOUT

RFIN

3.0 pF

3.3 nH

PD

Application

Hardware

IRQ

WirelessUSB LR

PSoC

13MHz

SPI

4

Crystal

Figure 6-1. CYWUSB6935 Battery Powered Device

P S oC + S M O K E

D E TE C TO R

W irelessU S B LR

A LA R M P A N E L

P S oC + M O TIO N

D E TE C TO R

P S oC + D O O R

S E N S O R

W irelessU S B LR +

P S oC

…

W irelessU S B LR

P S oC + K E Y P A D

Figure 6-2. WirelessUSB LR Alarm System

7.0

Register Descriptions

Table 7-1 displays the list of registers inside the

CYWUSB6935 that are addressable through the SPI interface.

All registers are read and writable, except where noted.

Table 7-1. CYWUSB6935 Register Map^[1]

CYWUSB6935

Address

Register Name

Revision ID

Synthesizer A Counter

Synthesizer N Counter

Control

Mnemonic

Page

9

8

9

Default

0x07

0x00

0x01

Access

REG_ID

0x00

0x01

0x02

0x03

0x04

0x05

RO

RW

REG_SYN_A_CNT

REG_SYN_N_CNT

REG_CONTROL

REG_DATA_RATE

REG_CONFIG

Data Rate

Configuration

10

11

Note:

1. All registers are accessed Little Endian.

Document 38-16008 Rev. **

Page 6 of 32

CYWUSB6935

PRELIMINARY

Table 7-1. CYWUSB6935 Register Map^[1]

Register Name

CYWUSB6935

Mnemonic

Address

0x06

Page

11

Default

0x03

0x00

Access

RW

RO

RW

RO

RW

RO

RW

RO

RW

RO

SERDES Control

Receive Interrupt Enable

Receive Interrupt Status

Receive Data A

Receive Valid A

Receive Data B

Receive Valid B

Transmit Interrupt Enable

Transmit Interrupt Status

Transmit Data

REG_SERDES_CTL

REG_RX_INT_EN

REG_RX_INT_STAT

REG_RX_DATA_A

REG_RX_VALID_A

REG_RX_DATA_B

REG_RX_VALID_B

REG_TX_INT_EN

REG_TX_INT_STAT

REG_TX_DATA

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

12

13

14

15

16

17

18

19

20

21

22

0x00

Transmit Valid

REG_TX_VALID

0x10

0x00

0x1E8B6A3DE0E9B222

PN Code

REG_PN_CODE

0x11–0x18

0x19

Threshold Low

Threshold High

Wake Enable

REG_THRESHOLD_L

REG_THRESHOLD_H

REG_WAKE_EN

0x08

0x38

0x00

0x01

0x04

0x00

0x64

–

0x1A

0x1C

0x1D

0x20

0x21

0x22

0x23

0x24

0x26

0x2E

0x2F

Wake Status

Analog Control

Channel

REG_WAKE_STAT

REG_ANALOG_CTL

REG_CHANNEL

Receive Signal Strength Indicator REG_RSSI

Power Control

Crystal Adjust

VCO Calibration

AGC Control

REG_PA

REG_CRYSTAL_ADJ

REG_VCO_CAL

REG_AGC_CTL

Carrier Detect

Clock Manual

Clock Enable

Synthesizer Lock Count

Manufacturing ID

REG_CARRIER_DETECT

REG_CLOCK_MANUAL

REG_CLOCK_ENABLE

REG_SYN_LOCK_CNT

REG_MID

0x32

0x33

0x38

0x3C–0x3F

Document 38-16008 Rev. **

Page 7 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x00

REG_ID

Default: 0x07

7

6

5

4

3

2

1

0

Silicon ID

Product ID

Figure 7-1. Revision ID Register

Bit

7:4

3:0

Name

Silicon ID

Description

These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only.

Product ID These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.

Addr: 0x01

REG_SYN_A_CNT

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Count

Figure 7-2. Synthesizer A Counter

Bit

7:5

4:0

Name

Description

Reserved These bits are reserved and should be written with zeros.

Count

The Synthesizer A Counter register is used for diagnostic purposes and is not recommended for normal operation.

The Channel register is the recommended method of setting the Synthesizer frequency.

The Synthesizer A Count along with the Synthesizer N Count can be used to generate the Synthesizer frequency. The

range of valid values of the Synthesizer A Count is 0 through 31. Using the Synthesizer A and N Count register is an

alternative to using the Channel register. Selection between the use of the Channel register or the A and N registers

is done through the Channel register (Reg 0x21, bit 7). When in Channel mode the A and N Count bits can be used

to read the A and N values derived directly from the Channel.

Addr: 0x02

REG_SYN_N_CNT

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Count

Figure 7-3. Synthesizer N Counter

Bit

7

6:0

Name

Reserved

Count

Description

This bit is reserved and should be written with zero.

The Synthesizer N Counter register is used for diagnostic purposes and therefore is not recommended for normal

operation. The Channel register is the recommended method of setting the Synthesizer frequency.

The Synthesizer N Count along with the Synthesizer A Count can be used to generate the Synthesizer frequency. The

range of valid values of the Synthesizer N Count is 74 through 76. Using the Synthesizer A and N Count register is

an alternative to using the Channel register. Selection between the use of the Channel register or the A and N registers

is done through the Channel register (Reg 0x21, bit 7). When in Channel mode the A and N Count bits can be used

to read the A and N values derived directly from the Channel.

Document 38-16008 Rev. **

Page 8 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x03

REG_CONTROL

Default: 0x00

7

6

5

4

3

2

1

0

RX

TX

PN Code

Auto Syn

Auto PA

PA Enable

Auto Syn

Syn Enable

Enable

Select

Count Select

Disable

Figure 7-4. Control

Bit Name

Description

7

6

5

RX Enable

The Receive Enable bit is used to place the IC in receive mode.

1 = Receive Enabled

0 = Receive Disabled

TX Enable

The Transmit Enable bit is used to place the IC in transmit mode.

1 = Transmit Enabled

0 = Transmit Disabled

PN Code Select The Pseudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code.

1 = 32 Most Significant Bits of PN code are used

0 = 32 Least Significant Bits of PN code are used

This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1).

4

3

Auto Syn Count The Auto Synthesizer Count Select bit is used to select the method of determining the settle time of the synthesizer.

Select

The two options are a programmable settle time based on the value in Syn Lock Count register (Reg 0x38), in units

of 2us, or by the auto detection of the synthesizer lock.

1 = Synthesizer settle time is based on a count in Syn Lock Count register (Reg 0x38)

0 = Synthesizer settle time is based on the internal synthesizer lock signal

It is recommended that the Auto Syn Count Select bit is set to 1 as that guarantees a consistent settle time for the

synthesizer.

Auto PA

Disable

The Auto Power Amplifier Disable bit is used to determine the method of controlling the Power Amplifier. The two

options are automatic control by the baseband or by firmware through register writes.

1 = Register controlled PA Enable.

0 = Auto PA Enable.

When this bit is set to 1 the state of PA enable is directly controlled by bit PA Enable (Reg 0x03, bit 2). It is

recommended that this bit is set to 0 leaving the PA control to the baseband.

2

1

PA Enable

The PA Enable bit is used to enable or disable the Power Amplifier.

1 = Power Amplifier Enabled

0 = Power Amplifier Disabled

This bit only applies when the Auto PA Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is don’t care.

Auto Syn

Disable

The Auto Synthesizer Disable bit is used to determine the method of controlling the Synthesizer. The two options

are automatic control by the baseband or by firmware through register writes.

1 = Register controlled Synthesizer Enable.

0 = Auto Synthesizer Enable.

When this bit is set to 1 the state of the Synthesizer is directly controlled by bit Syn Enable (Reg 0x03, bit 0). When

this bit is set to 0 the state of the Synthesizer is controlled by the Auto Syn Count Select bit (Reg 0x03, bit 4). It is

recommended that this bit is set to 0 leaving the Synthesizer control to the baseband.

0

Syn Enable

The Synthesizer Enable bit is used to enable or disable the Synthesizer.

1 = Synthesizer Enabled

0 = Synthesizer Disabled

This bit only applies when Auto Syn Disable bit is selected (Reg 0x03, bit 1=1), otherwise this bit is don’t care.

Document 38-16008 Rev. **

Page 9 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x04

REG_DATA_RATE

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Code Width

Data Rate

Sample Rate

Figure 7-5. Data Rate

Bit Name

Description

These bits are reserved and should be written with zeros.

7:3 Reserved

2^[2]Code Width The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.

1 = 32 chips/bit PN codes

0 = 64 chips/bit PN codes

The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to inter-

ference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double

data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more

robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted

and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample

Rate (Reg 0x04, bit 0).

1^[2]Data Rate

The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of

62.5kbits/sec.

1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)

0 = Normal Data Rate - 1 bit per PN code

This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg

0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit

PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code

register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate

capability. When using Normal Data Rate, the raw data throughput is 32kbits/sec. Additionally, Normal Data Rate

enables the user to potentially correlate data using two differing 32 chips/bit PN codes.

0^[2]Sample Rate The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.

1 = 12x Oversampling

0 = 6x Oversampling

Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double Data

Rate this bit is don’t care. When in the Normal Data Rate setting and choosing 12x oversampling, eliminates the ability

to receive from two different PN codes. Therefore the only time when 12x oversampling is to be selected is when a 32

chips/bit PN code is being used and there is no need to receive data from sources with two different PN codes.

Note:

2. The following Reg 0x04, bits 2:0 values are not valid:

•

001–Not Valid

010–Not Valid

011–Not Valid

Document 38-16008 Rev. **

Page 10 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x05

REG_CONFIG

Default: 0x01

7

6

5

4

3

2

1

0

Reserved

Receive Invert Transmit Invert

Reserved

IRQ Pin Select

Figure 7-6. Configuration

Bit Name

Description

7:5 Reserved

These bits are reserved and should be written with zeros.

4

3

2

Receive Invert The Receive Invert bit is used to invert the received data.

1 = Inverted over-the-air Receive data

0 = Non-inverted over-the-air Receive data

Transmit Invert The Transmit Invert bit is used to invert the data that is to be transmitted.

1 = Inverted Transmit Data.

0 = Non-inverted Transmit Data.

Reserved

This bit is reserved and should be written with zero.

1:0 IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.

11 = Open Drain (asserted = 0, deasserted = Hi-Z)

10 = Open Source (asserted = 1, deasserted = Hi-Z)

01 = CMOS (asserted = 1, deasserted = 0)

00 = CMOS Inverted (asserted = 0, deasserted = 1)

Addr: 0x06

REG_SERDES_CTL

Default: 0x03

7

6

5

4

3

2

1

0

Reserved

SERDES

Enable

EOF Length

Figure 7-7. SERDES Control

Bit

7:4

3

Name

Reserved

Description

These bits are reserved and should be written with zeros.

SERDES Enable The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.

1 = SERDES enabled.

0 = SERDES disabled, bit-serial mode enabled.

When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the use of

the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of

the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid the need to

manage the timing required by the bit-serial mode.

2:0

EOF Length

The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without

valid data before an EOF event will be generated. When in receive mode and a valid bit has been received the

EOF event can then be identified by the number of bit times that expire without correlating any new data. The

EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate

interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception.

Document 38-16008 Rev. **

Page 11 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x07

REG_RX_INT_EN

Default: 0x00

7

6

5

4

3

2

1

0

Underflow B

Overflow B

EOF B

Full B

Underflow A

Overflow A

EOF A

Full A

Figure 7-8. Receive Interrupt Enable

Bit Name

Description

7

6

5

Underflow B

The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES

Data B register (Reg 0x0B)

1 = Underflow B interrupt enabled for Receive SERDES Data B

0 = Underflow B interrupt disabled for Receive SERDES Data B

An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is

empty.

Overflow B

EOF B

The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES

Data B register (Reg 0x0B)

1 = Overflow B interrupt enabled for Receive SERDES Data B

0 = Overflow B interrupt disabled for Receive SERDES Data B

An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg

0x0B) before the prior data is read out.

The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.

1 = EOF B interrupt enabled for Channel B Receiver.

0 = EOF B interrupt disabled for Channel B Receiver.

The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has

been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is

the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by

reading the receive status register

4

Full B

The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having

data placed in it.

1 = Full B interrupt enabled for Receive SERDES Data B

0 = Full B interrupt disabled for Receive SERDES Data B

A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B

register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

3

2

1

Underflow A

Overflow A

EOF A

The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES

Data A register (Reg 0x09)

1 = Underflow A interrupt enabled for Receive SERDES Data A

0 = Underflow A interrupt disabled for Receive SERDES Data A

An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is

empty.

The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES

Data A register (0x09)

1 = Overflow A interrupt enabled for Receive SERDES Data A

0 = Overflow A interrupt disabled for Receive SERDES Data A

An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09)

before the prior data is read out.

The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel

A Receiver.

1 = EOF A interrupt enabled for Channel A Receiver.

0 = EOF A interrupt disabled for Channel A Receiver.

The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has

been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the

EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading

the receive status register.

0

Full A

The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having

data written into it.

1 = Full A interrupt enabled for Receive SERDES Data A

0 = Full A interrupt disabled for Receive SERDES Data A

A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A

register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

Document 38-16008 Rev. **

Page 12 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x08

REG_RX_INT_STAT

Default: 0x00

7

6

5

4

3

2

1

0

Valid B

Flow Violation B

EOF B

Full B

Valid A

Flow Violation A

EOF A

Full A

Figure 7-9. Receive Interrupt Status^[3]

Bit Name

Description

7

Valid B

The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.

1 = All bits are valid for Receive SERDES Data B.

0 = Not all bits are valid for Receive SERDES Data B.

When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within the

byte that has been written are valid. This bit cannot generate an interrupt.

6

Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the Receive

SERDES Data B register (Reg 0x0B).

1 = Overflow/underflow interrupt pending for Receive SERDES Data B.

0 = No overflow/underflow interrupt pending for Receive SERDES Data B.

Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B)

before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data B

register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register

(Reg 0x08)

5

4

EOF B

Full B

The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive.

1 = EOF interrupt pending for Channel B.

0 = No EOF interrupt pending for Channel B.

An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times

specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is cleared

by reading the Receive Interrupt Status register (Reg 0x08)

The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data.

1 = Receive SERDES Data B full interrupt pending.

0 = No Receive SERDES Data B full interrupt pending.

A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B

register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

3

2

Valid A

The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid.

1 = All bits are valid for Receive SERDES Data A.

0 = Not all bits are valid for Receive SERDES Data A.

When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within the

byte that has been written are valid. This bit cannot generate an interrupt.

Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the Receive

SERDES Data A register (Reg 0x09).

1 = Overflow/underflow interrupt pending for Receive SERDES Data A.

0 = No overflow/underflow interrupt pending for Receive SERDES Data A.

Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09)

before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A

register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register

(Reg 0x08)

1

0

EOF A

Full A

The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive.

1 = EOF interrupt pending for Channel A.

0 = No EOF interrupt pending for Channel A.

An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times

specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared by

reading the Receive Interrupt Status register (Reg 0x08).

The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data.

1 = Receive SERDES Data A full interrupt pending.

0 = No Receive SERDES Data A full interrupt pending.

A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A

Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or

not a complete byte has been received.

Note:

3. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The

status bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These

register are read-only.

Document 38-16008 Rev. **

Page 13 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x09

REG_RX_DATA_A

Default: 0x00

7

6

5

4

3

2

1

0

Data

Figure 7-10. Receive SERDES Data A

Bit

Name Description

Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,

7:0

Data

followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.

Addr: 0x0A

REG_RX_VALID_A

Default: 0x00

7

6

5

4

3

2

1

0

Valid

Figure 7-11. Receive SERDES Valid A

Bit Name

Description

These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the

7:0 Valid

corresponding data bit is valid for Channel A.

If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A

register (Reg 0x09) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0A). The

over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5,

followed by bit 6, followed by bit 7. This register is read-only.

Addr: 0x0B

REG_RX_DATA_B

Default: 0x00

7

6

5

4

3

2

1

0

Data

Figure 7-12. Receive SERDES Data B

Bit Name

Description

Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,

7:0 Data

followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.

Addr: 0x0C

REG_RX_VALID_B

Default: 0x00

7

6

5

4

3

2

1

0

Valid

Figure 7-13. Receive SERDES Valid B

Bit Name Description

These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the

7:0 Valid

corresponding data bit is valid for Channel B.

If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register

(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C).The over-the-

air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed

by bit 6, followed by bit 7. This register is read-only.

Document 38-16008 Rev. **

Page 14 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x0D

REG_TX_INT_EN

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Underflow

Overflow

Done

Empty

Figure 7-14. Transmit Interrupt Enable

Bit Name

7:4 Reserved

Description

These bits are reserved and should be written with zeros.

The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit

3

Underflow

SERDES Data register (Reg 0x0F)

1 = Underflow interrupt enabled.

0 = Underflow interrupt disabled.

An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does

not have any data.

The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data

register (0x0F).

2

Overflow

1 = Overflow interrupt enabled.

0 = Overflow interrupt disabled.

An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F)

before the preceding data has been transferred to the transmit shift register.

1

0

Done

The Done bit is used to enable the interrupt that signals the end of the transmission of data.

1 = Done interrupt enabled.

0 = Done interrupt disabled.

The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and

there is no more data for it to transmit.

Empty

The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty.

1 = Empty interrupt enabled.

0 = Empty interrupt disabled.

The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer

and it's safe to load the next byte

Addr: 0x0E

REG_TX_INT_STAT

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Underflow

Overflow

Done

Empty

Figure 7-15. Transmit Interrupt Status^[4]

Bit Name

Description

7:4 Reserved These bits are reserved. This register is read-only.

3

Underflow The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register

(Reg 0x0F) has occurred.

1 = Underflow Interrupt pending.

0 = No Underflow Interrupt pending.

This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs

when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register

(Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the

Transmit Interrupt Status register (Reg 0x0E).

2

Overflow The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F)

has occurred.

1 = Overflow Interrupt pending.

0 = No Overflow Interrupt pending.

This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs

when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent.

This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).

1

Done

The Done bit is used to signal the end of a data transmission.

1 = Done Interrupt pending.

0 = No Done Interrupt pending.

This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only

assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status

register (Reg 0x0E)

0

Empty

The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.

1 = Empty Interrupt pending.

0 = No Empty Interrupt pending.

This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES

Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when

the data is loaded into the transmitter, and it is ok to write new data.

Note:

4. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling

IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in

transmit mode. These registers are read-only.

Document 38-16008 Rev. **

Page 15 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x0F

REG_TX_DATA

Default: 0x00

7

6

5

4

3

2

1

0

Data

Figure 7-16. Transmit SERDES Data

Bit Name Description

7:0 Data

Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit

4, followed by bit 5, followed by bit 6, followed by bit 7.

Addr: 0x10

REG_TX_VALID

Default: 0x00

7

6

5

4

3

2

1

0

Valid

Figure 7-17. Transmit SERDES Valid

Bit

7:0

Name Description

Valid^[5]The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid.

1 = Valid transmit bit.

0 = Invalid transmit bit.

Default:

Addr: 0x11-18

REG_PN_CODE

0x1E8B6A3DE0E9B222

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Address 0x18 Address 0x17 Address 0x16 Address 0x15

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Address 0x14 Address 0x13 Address 0x12

9

8

7

6

5

4

3

2

1

0

Address 0x11

Figure 7-18. PN Code

Bit

Name

Description

63:0 PN Codes

The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes can

be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32 chips/bit

PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value

can be used as a PN code as there are certain characteristics that are needed to minimize the possibility of multiple

PN codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by

bit 1... followed by bit 62, followed by bit 63.

Note:

5. Note: The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the

data byte. Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the

Transmit SERDES Valid register (Reg 0x10) will send half a byte.

Document 38-16008 Rev. **

Page 16 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x19

REG_THRESHOLD_L

Default: 0x08

7

6

5

4

3

2

1

0

Reserved

Threshold Low

Figure 7-19. Threshold Low

Bit Name

Description

7

Reserved

This bit is reserved and should be written with zero.

6:0 Threshold Low

The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate

a single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would result in zero

correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low

value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data

bit. This value along with the Threshold High value determine the correlator count values for logic ‘1’ and logic ‘0’.

The threshold values used determine the sensitivity of the receiver to interference and the dependability of the

received data. By allowing a minimal number of erroneous chips the dependability of the received data increases

while the robustness to interference decreases. On the other hand increasing the maximum number of missed

chips means reduced data integrity but increased robustness to interference and increased range.

Addr: 0x1A

REG_THRESHOLD_H

Default: 0x38

7

6

5

4

3

2

1

0

Reserved

Threshold High

Figure 7-20. Threshold High

Bit

7

6:0

Name

Reserved

Threshold High

Description

This bit is reserved and should be written with zero.

The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate

a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit PN code

would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received

perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous

while still identifying the value of the received data bit. This value along with the Threshold Low value determine

the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the

receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous

chips the dependability of the received data increases while the robustness to interference decreases. On the

other hand increasing the maximum number of missed chips means reduced data integrity but increased

robustness to interference and increased range.

Document 38-16008 Rev. **

Page 17 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x1C

REG_WAKE_EN

Default: 0x00

7

6

5

4

3

2

1

0

Wakeup Enable

Reserved

Figure 7-21. Wake Enable

Bit Name

Description

These bits are reserved and should be written with zeros.

7:1 Reserved

0

Wakeup Enable Wakeup interrupt enable.

0 = disabled

1 = enabled

A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.

Addr: 0x1D

REG_WAKE_STAT

Default: 0x01

7

6

5

4

3

2

1

0

Wakeup Status

Reserved

Figure 7-22. Wake Status

Bit

7:1

0

Name

Reserved

Description

These bits are reserved. This register is read-only.

Wakeup Status Wakeup status.

0 = Wake interrupt not pending

1 = Wake interrupt pending

This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg

0x1D). This register is read-only.

Addr: 0x20

REG_ANALOG_CTL

Default: 0x00

7

6

5

4

3

2

1

0

AGC Disable

MID Read

Enable

Reserved

PA Output

Enable

PaInv

Rst

Figure 7-23. Analog Control

Bit Name

Description

This bit is reserved and should be written with zero.

7

6

5

Reserved

AGC RSSI Control Enables AGC/RSSI control via Reg 0x2E and Reg 0x2F.

MID Read Enable The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F).

Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when

reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F).

4:3 Reserved

These bits are reserved and should be written with zeros.

2

PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier.

1 = PA Control Output Enabled on PACTL pin.

0 = PA Control Output Disabled on PACTL pin.

1

PA Invert

Reset

The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set high.

PA Output Enable and PA Invert cannot be simultaneously changed.

1 = PACTL active low

0 = PACTL active high

0

The Reset bit is used to generate a self clearing device reset.

1 = Device Reset. All registers are restored to their default values.

0 = No Device Reset.

Document 38-16008 Rev. **

Page 18 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x21

REG_CHANNEL

Default: 0x00

7

6

5

4

3

2

1

0

A+N

Channel

Figure 7-24. Channel

Bit Name

A+N

Description

7

The A+N bit is used to specify whether the Synthesizer frequency is generated through the use of the Channel register (Reg

0x21) or through the use of the Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg

0x02).

1 = Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) registers used to generate

Synthesizer frequency.

0 = Channel register (Reg 0x21) is used to generate Synthesizer frequency.

When set to 1 the channel value is ignored and the values written in the Synthesizer A Counter register (Reg 0x01) and the

Synthesizer N Counter register (Reg 0x02) are used. When set to 0 the values written to the Synthesizer A Counter register

(Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) are ignored and the channel value is used by the synthesizer.

It is recommended that the Channel register (Reg 0x21) is used as opposed to the Synthesizer A Counter register (Reg

0x01) and the Synthesizer N Counter register (Reg 0x02) method.

The Channel register (Reg 0x21) is used to determine the Synthesizer frequency when the A+N bit is set to 0. Use of other

channels may be restricted by certain regulatory agencies. A value of 1 corresponds to a communication frequency of 2.402

GHz, while a value of 79 corresponds to a frequency of 2.479GHz. The channels are separated from each other by 1 MHz

intervals.

6:0 Channel

Addr: 0x22

REG_RSSI

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Valid

RSSI

Figure 7-25. Receive Signal Strength Indicator (RSSI)^[6]

Bit Name

Description

These bits are reserved. This register is read-only.

7:6 Reserved

5

Valid

The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is Read Only.

1 = RSSI value is valid

0 = RSSI value is invalid

The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only

value with the higher values indicating stronger received signals meaning more reliable transmissions.

4:0 RSSI

Addr: 0x23

REG_PA

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

PA Bias

Figure 7-26. Power Control

Bit Name

Description

7:3 Reserved

2:0 PA Bias

These bits are reserved and should be written with zeros.

The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7)

or decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the

transmit power. By changing the PA Bias value signal strength management functions can be accomplished. For general

purpose communication a value of 7 is recommended.

Note:

6. The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1).

Document 38-16008 Rev. **

Page 19 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x24

REG_CRYSTAL_ADJ

Default: 0x00

7

6

5

4

3

2

1

0

Reserved

Clock Output

Crystal Adjust

Disable

Figure 7-27. Crystal Adjust

Bit Name

Description

7

6

Reserved

This bit is reserved and should be written with zero.

Clock Output Disable The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin.

1 = No 13 MHz clock driven externally.

0 = 13 MHz clock driven externally.

If the 13 MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by -4 dBm on channels

5+13n. By default the 13 MHz clock output pin is enabled. This pin is useful for adjusting the 13 MHz clock, but

it interfere with every 13th channel beginning with 2.405GHz channel. Therefore, it is recommended that the 13

MHz clock output pin be disabled when not in use.

The Crystal Adjust value is used to calibrate the on-chip load capacitance supplied to the crystal. The Crystal

Adjust value will depend on the parameters of the crystal being used. Refer to the appropriate reference material

for information about choosing the optimum Crystal Adjust value.

5:0 Crystal Adjust

Addr: 0x26

REG_VCO_CAL

Default: 0x00

7

6

5

4

3

2

1

0

VCO Slope Enable

Reserved

Figure 7-28. VCO Calibration

Bit Name

Description

7:6 VCO Slope Enable The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance automat-

(Write-Only)

ically added to the VCO.

11 = -5/+5 VCO adjust. The application MCU must configure this option during initialization.

10 = -2/+3 VCO adjust.

01 = Reserved.

00 = No VCO adjust.

These bits are undefined for read operations.

5:0 Reserved

These bits are reserved and should be written with zeros.

Document 38-16008 Rev. **

Page 20 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x2E

REG_AGC_CTL

Default: 0x00

7

6

5

4

3

2

1

0

AGC Lock

Reserved

Figure 7-29. AGC Control

Bit Name

Description

7

AGC Lock

When set, this bit disables the on-chip LNA AGC system, powers down unused circuitry, and locks the LNA to maximum

gain. The user must set Reg 20, bit 6=1 to enable writes to Reg 0x2E. It is recommended to set this bit during

initialization to save power.

6:0 Reserved

These bits are reserved and should be written with zeros.

Addr: 0x2F

REG_CARRIER_DETECT

Default: 0x00

7

6

5

4

3

2

1

0

Carrier Detect

Override

Reserved

Figure 7-30. Carrier Detect

Bit Name

Description

7

Carrier Detect Override When set, this bit overrides carrier detect. The user must set Reg 20, bit 6=1 to enable writes to Reg 0x2F.

6:0 Reserved

These bits are reserved and should be written with zeros.

Addr: 0x32

REG_CLOCK_MANUAL

Default: 0x00

7

6

5

4

3

2

1

0

Manual Clock Overrides

Figure 7-31. Clock Manual

Bit Name

Description

7:0 Manual Clock Overrides This register must be written with 0x41 after reset for correct operation

Addr: 0x33

REG_CLOCK_ENABLE

Default: 0x00

7

6

5

4

3

2

1

0

Manual Clock Enables

Figure 7-32. Clock Enable

Bit Name

Description

7:0 Manual Clock Enables This register must be written with 0x41 after reset for correct operation

Document 38-16008 Rev. **

Page 21 of 32

CYWUSB6935

PRELIMINARY

Addr: 0x38

REG_SYN_LOCK_CNT

Default: 0x64

7

6

5

4

3

2

1

0

Count

Figure 7-33. Synthesizer Lock Count

Bit Name Description

Determines the length of delay in 2µs increments for the synthesizer to lock when auto synthesizer is enabled via Control

7:0 Count

register (0x03, bit 1=0) and not using the PLL lock signal.

Addr: 0x3C-3F

REG_MID

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Address 0x3F Address 0x3E Address 0x3D

Address 0x3C

Figure 7-34. Manufacturing ID

Bit Name

Description

31:0 Address[31:0] These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read unless the MID

Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg

0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only

be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only.

Document 38-16008 Rev. **

Page 22 of 32

CYWUSB6935

PRELIMINARY

8.0

Pin Descriptions

Table 8-1. Pin Description Table

Pin SOIC

Pin QFN

Name

Type Default

Description

Analog RF

3

6

46

5

RFIN

RFOUT

Input

Output

Input RF Input. Modulated RF signal received.

N/A

RF Output. Modulated RF signal to be transmitted.

Crystal / Power Control

26

25

19

38

35

26

X13

X13IN

Input

N/A

Crystal Input. (refer to Section 4.6).

X13OUT Output Output System Clock. Buffered 13-MHz system clock.

/Hi-Z

23

33

PD

Input

N/A

Power Down. Asserting this input (low), will put the IC in the Suspend

Mode (X13OUT is 0 when PD is Low).

10

24

14

34

RESET

PACTL

Input

I/O

N/A

Active LOW Reset. Device reset.

Input PACTL. External Power Amplifier control. Pull-down or make output.

SERDES Bypass Mode Communications/Interrupt

13

12

14

20

19

21

DIO

DIOVAL

IRQ

I/O

Input Data Input/Output. SERDES Bypass Mode Data Transmit/Receive.

Input Data I/O Valid. SERDES Bypass Mode Data Transmit/Receive Valid.

Output Output IRQ. Interrupt and SERDES Bypass Mode DIOCLK.

/Hi-Z

SPI Communications

16

17

23

24

MOSI

MISO

Input

Output

/Hi-Z

N/A

Hi-Z

Master-Output-Slave-Input Data. SPI data input pin.

Master-Input-Slave-Output Data. SPI data output pin.

18

15

25

22

SCK

SS

Input

N/A

SPI Input Clock. SPI clock.

Slave Select Enable. SPI enable.

Power and Ground

V

_CC= 2.7V to 3.6V.

2, 7, 8, 11, 6, 9, 16, 28,

20,21, 22, 29, 32, 41, 42, VCC

VCC

H

27, 28

45

44

13

Vcc = 2.7V to 3.6V. (Decouple separately from VCC pins)

Ground = 0V.

1

9

AVCC

GND

AVCC

GND

H

L

Tie to Ground.

4, 5

1, 2, 3, 4, 7, 8,

10, 11, 12, 15,

17, 18, 27, 30, NC

31, 36, 37, 39,

N/A

L

40, 43, 47, 48

Must be tied to Ground.

Exposed paddle

GND

Document 38-16008 Rev. **

Page 23 of 32

CYWUSB6935

PRELIMINARY

SOIC^*

Top View

AVCC

VCC

X13

X13IN

PACTL

PD

VCC

X13OUT

SCK

MISO

MOSI

SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

RFIN

NC

RFOUT

VCC

GND

RESET

VCC

DIOVAL

DIO

* E-PAD BOTTOM SIDE

IRQ

Figure 8-1. CYWUSB6935, 28 SOIC – Top View

CYWUSB6935

Top View*

NC

1

2

3

4

5

6

7

8

9

36 NC

35 X13IN

34 PACTL

PD

NC

33

32 V_CC

RFOUT

V_CC

31

30

29

28

NC

V_CC

CYWUSB6935

48 QFN

NC

V_CC

NC 10

NC 11

27 NC

26 X13OUT

25 SCK

12

NC

Figure 8-2. CYWUSB6935, 48 QFN – Top View

Document 38-16008 Rev. **

Page 24 of 32

CYWUSB6935

PRELIMINARY

9.0

Absolute Maximum Ratings

10.0

Operating Conditions

Storage Temperature ..................................–65°C to +150°C

Ambient Temperature with Power Applied..–55°C to +125°C

Supply Voltage on V_CCrelative to VSS.......... –0.3V to +3.9V

DC Voltage to Logic Inputs^[7]..................–0.3V to V_CC+0.3V

V_CC(Supply Voltage)..........................................2.7V to 3.6V

T_A(Ambient Temperature Under Bias).......... -40°C to +85°C

Ground Voltage ................................................................. 0V

F_OSC(Oscillator or Crystal Frequency) ..................... 13 MHz

DC Voltage applied to

Outputs in High-Z State...........................–0.3V to V_CC+0.3V

11.0

DC Characteristics (over the operating range)

Static Discharge Voltage (Digital)...............................>2000V

Static Discharge Voltage (RF)^[8].................................... 500V

Latch-up Current..................................... +200 mA, –200 mA

Table 11-1. DC Parameters

Parameter

V_CC

Description

Conditions

Min.

2.7

Typ.^[10]Max. Unit

Supply Voltage

3.0

V_CC

3.0

3.6

V

V_OH1

V_OH2

V_OL

Output High Voltage condition 1

Output High Voltage condition 2

Output Low Voltage

At I_OH= –100.0µA V_CC–0.1

At I_OH= –2.0 mA

At I_OL= 2.0 mA

2.4

0.0

0.4

V

[9]

V_IH

Input High Voltage

2.0

–0.3

–1

V_CC

0.8

+1

10

V_IL

Input Low Voltage

I_IL

Input Leakage Current

0 < V_IN< V_CC

0.26

3.5

0.24

3

1.8

5.9

µA

pF

µA

mA

C_IN

Pin Input Capacitance (except X13, X13IN, RFIN)

I_Sleep

Current consumption during power-down mode PD = LOW

IDLE I_CC

STARTUP I_CC

TX AVG I_CC1

TX AVG I_CC2

RX I_{CC (PEAK)}

TX I_{CC (PEAK)}

Current consumption without synthesizer

ICC from PD high to oscillator stable.

Average transmitter current consumption^[11]

Average transmitter current consumption^[12]

Current consumption during receive

PD = HIGH

no handshake

with handshaking

8.1

57.7

69.1

28.7

Current consumption during transmit

SYNTH SETTLE Current consumption with Synthesizer on, No

I_CC

Transmit or Receive

Notes:

7. It is permissible to connect voltages above Vcc to inputs through a series resistor limiting input current to 1 mA. This can’t be done during power down mode.

AC timing not guaranteed.

8. Human Body Model (HBM).

9. It is permissible to connect voltages above Vcc to inputs through a series resistor limiting input current to 1 mA.

10. Typ. values measured with Vcc = 3.0V @ 25°C

11. Average Icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10ms using the WirelessUSB 1-way protocol.

12. Average Icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10ms using the WirelessUSB 2-way protocol.

Document 38-16008 Rev. **

Page 25 of 32

CYWUSB6935

PRELIMINARY

12.0

AC Characteristics^[13]

Table 12-1. SPI Interface^[15]

Parameter

Description

Min.

476

238

158

Typ.

Max.

Unit

ns

t_{SCK_CYC}

t_{SCK_HI (BURST READ)}

t_{SCK_HI}

t_{SCK_LO}

t_{DAT_SU}

t_{DAT_HLD}

t_{DAT_VAL}

t_{SS_SU}

SPI Clock Period

[14]

SPI Clock High Time

SPI Clock Low Time

SPI Input Data Set-up Time

SPI Input Data Hold Time

SPI Output Data Valid Time

10

97^[15]

77^[15]

174^[15]

SPI Slave Select Set-up Time before first positive edge of SCK^[16]250

t_{SS_HLD}

SPI Slave Select Hold Time after last negative edge of SCK

80

t_{SCK_CYC}

t_{SCK_HI}

t_{SCK_LO}

SCK

t_{SS_SU}

t_{DAT_SU}

t_{SS_HLD}

SS

M O SI

M ISO

t_{DAT_HLD}

data from m cu

data to m cu

data

t_{DAT_VAL}

data to m cu

Figure 12-1. SPI Timing Diagram

t_{SCK_CYC}

t_{SCK_HI}

t_{SCK_LO}

t_{SCK_HI (BURST READ)}

every 8^thSCK_HI

every 9^thSCK_HI

every 10^thSCK_HI

SCK

SS

data to mcu

data

MISO

t_{DAT_VAL}

Figure 12-2. SPI Burst Read Every 9th SCK HI Stretch Timing Diagram

Notes:

13. AC values are not guaranteed if voltages on any pin exceed Vcc.

14. This stretch only applies to every 9th SCK HI pulse for SPI Burst Reads only.

15. For F

= 13 MHz, 3.3v @ 25°C.

OSC

16. SCK must start low, otherwise the success of SPI transactions are not guaranteed.

Document 38-16008 Rev. **

Page 26 of 32

CYWUSB6935

PRELIMINARY

Table 12-2. DIO Interface

Parameter

Transmit

t_{TX_DIOVAL_SU}

Description

Min.

2.1

0

Typ.

Max.

Unit

µs

Unit

µs

DIOVAL Set-up Time

t_{TX_DIO_SU}

DIO Set-up Time

DIOVAL Hold Time

DIO Hold Time

t_{TX_DIOVAL_HLD}

t_{TX_DIO_HLD}

t_{TX_IRQ_HI}

0

Minimum IRQ High Time - 32 chips/bit DDR

Minimum IRQ High Time - 32 chips/bit

Minimum IRQ High Time - 64 chips/bit

Minimum IRQ Low Time - 32 chips/bit DDR

Minimum IRQ Low Time - 32 chips/bit

Minimum IRQ Low Time - 64 chips/bit

8

16

32

8

16

32

Typ.

t_{TX_IRQ_LO}

Receive

t_{RX_DIOVAL_VLD}

Min.

-0.01

Max.

6.1

8.2

16.1

6.1

8.2

DIOVAL Valid Time - 32 chips/bit DDR

DIOVAL Valid Time - 32 chips/bit

DIOVAL Valid Time - 64 chips/bit

DIO Valid Time - 32 chips/bit DDR

DIO Valid Time - 32 chips/bit

DIO Valid Time - 64 chips/bit

Minimum IRQ High Time - 32 chips/bit DDR

Minimum IRQ High Time - 32 chips/bit

Minimum IRQ High Time - 64 chips/bit

Minimum IRQ Low Time - 32 chips/bit DDR

Minimum IRQ Low Time - 32 chips/bit

Minimum IRQ Low Time - 64 chips/bit

t_{RX_DIO_VLD}

t_{RX_IRQ_HI}

t_{RX_IRQ_LO}

16.1

1

8

16

32

t_{RX_IRQ_HI}

t_{RX_IRQ _LO}

IRQ

DIO /

data

DIO VAL

t_{RX_DIO _VLD}

t_{RX_DIOVAL_VLD}

Figure 12-3. DIO Receive Timing Diagram

t_{TX_IRQ_HI}

t_{TX_IRQ_LO}

IRQ

DIO/

data

DIOVAL

t_{TX_DIO_SU}

t_{TX_DIOVAL_SU}

t_{TX_DIO_HLD}

t_{TX_DIOVAL_HLD}

Figure 12-4. DIO Transmit Timing Diagram

Document 38-16008 Rev. **

Page 27 of 32

CYWUSB6935

PRELIMINARY

12.1

Table 12-3. Radio Parameters

Parameter Description

RF Frequency Range

Radio Parameters

Conditions

Min.

2.400

Typ.

Max.

2.483

Unit

GHz

[18]

–3

Radio Receiver (V = 3.3V, fosc = 13.000 MHz, X13OUT off, 64 chips/bit, Threshold Low = 8, Threshold High = 56, BER < 10

)

CC

Sensitivity

Maximum Received Signal

–85

–20

–95

–6

dBm

RSSI value for PWR_in> -40 dBm

RSSI value for PWR_in< -95 dBm

Interference Performance

28 - 31

0 -10

Co-channel Interference rejection Carrier-to-Interference (C/I) C = –60 dBm

9

-2

–32

–40

–31

–38

dB

Adjacent (1 MHz) channel selectivity C/I 1 MHz

Adjacent (2 MHz) channel selectivity C/I 2 MHz

Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz

Image^[20]Frequency Interference, C/I Image

C = –60 dBm

C = –67 dBm

Adjacent (1 MHz) interference to in-band image frequency, C/I C = –67 dBm

image ±1 MHz

Out-of-Band Blocking Interference Signal Frequency

30 MHz – 2399 MHz except (FO/N & FO/N±1 MHz)^[17]

C = –67 dBm

–24

–22

–31

dBm

[17]

2498 MHz – 12.75 GHz, except (FO*N & FO*N±1 MHz)

Intermodulation

C = –64 dBm

∆f = 5,10 MHz

Spurious Emission

30 MHz – 1 GHz

1 GHz – 12.75 GHz except (4.8GHz - 5.0GHz)

4.8 GHz – 5.0 GHz

–57

–47

dBm

–37^[19]

Radio Transmitter (V = 3.3V, fosc = 13.000 MHz)

CC

Maximum RF Transmit Power

RF Power Control Range

RF Power Range Control Step Size

Frequency Deviation

Zero Crossing Error

PA = 7

–0.5

28.9

4.1

276

317

±80

898

dBm

dB

kHz

ns

seven steps, monotonic

PN Code Pattern 10101010

PN Code Pattern 11110000

Occupied Bandwidth

100-kHz resolution

bandwidth, –6 dBc

500

kHz

Initial Frequency Offset

In-band Spurious

Second Channel Power (±2 MHz)

> Third Channel Power (>3 MHz)

Non-Harmonically Related Spurs

30 MHz – 12.75 GHz

±44.6

kHz

–41

–49

–30

–40

dBm

–57

dBm

Harmonic Spurs

Second Harmonic

Third Harmonic

–20

–30

–47

dBm

Fourth and Greater Harmonics

Notes:

17. FO = Tuned Frequency, N = Integer.

18. Subject to regulation.

19. Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements.

20. Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection).

Document 38-16008 Rev. **

Page 28 of 32

CYWUSB6935

PRELIMINARY

12.2

Power Management Timing

Description

Time from PD deassert to X13OUT

Parameter

Conditions

Min.

Typ

2000

Max.

Unit

µs

ns

µs

t_{PDN_X13}

t_{SPI_RDY}

t_{PWR_RST}

t_RST

t_{PWR_PD}

t_WAKE

Time from oscillator stable to start of SPI transactions

Power On to RESET deasserted

Minimum RESET asserted pulse width

Power On to PD deasserted^[21]

PD deassert to clocks running^[22]

1

1300

1

V_cc@ 2.7V

1300

2000

t_PD

t_SLEEP

Minimum PD asserted pulse width

PD assert to low power mode

10

50

2000

2100

t_{WAKE_INT}

t_STABLE

PD deassert to IRQ^[23]assert (wake interrupt)^[24]

PD deassert to clock stable

to within ±10 ppm

t_{SPI_RDY}

t_{PDN_X13}

X13OUT

VCC

t_{PW R_RST}

t_{PW R_PD}

t_RST

RESET

PD

Figure 12-5. Power On Reset/Reset Timing

t_{W AKE}

X13OUT

PD

t_PD

t_STABLE

t_SLEEP

t_{WAKE_INT}

IRQ

Figure 12-6. Sleep / Wake Timing

Notes:

21. The PD pin must be asserted at power up to ensure proper crystal startup.

22. When X13OUT is enabled.

23. Both the polarity and the drive method of the IRQ pin are programmable. See page 11 for more details. Figure 12-6 illustrates default values for the Configuration

register (Reg 0x05, bits 1:0).

24. A wakeup event is triggered when the PD pin is deasserted. Figure 12-6 illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable

register (Reg 0x1C, bit 0=1).

Document 38-16008 Rev. **

Page 29 of 32

CYWUSB6935

PRELIMINARY

12.3

AC Test Loads and Waveforms

for Digital Pins

AC Test Loads

OUTPUT

DC Test Load

OUTPUT

R1

V

CC

5 pF

30 pF

OUTPUT

INCLUDING

JIG AND

SCOPE

Max

R2

JIG AND

SCOPE

Typical

ALL INPUT PULSES

90%

10%

V

Parameter

R1

R2

R_TH

V_TH

Unit

Ω

CC

90%

10%

1071

937

500

1.4

GND

Ω

Fall time: 1 V/ns

Ω

Rise time: 1 V/ns

V

THÉ

VENIN EQUIVALENT

Equivalent to:

OUTPUT

V_CC

3.00

R

TH

V

TH

Figure 12-7. AC Test Loads and Waveforms for Digital Pins

13.0

Ordering Information

Part Number

Radio

Transceiver

Package Name Package Type

Operating Range

Industrial

CYWUSB6935-28SEI

CYWUSB6935-48LFI

CYWUSB6935-48LFC

28 SOIC

48 QFN

28-Lead Molded SOIC Exposed Paddle

48 Quad Flat Package No Leads

Commercial

14.0

Package Description

MIN.

DIMENSIONS IN INCHES[MM]

MAX.

REFERENCE JEDEC MS-013

PACKAGE WEIGHT 0.8gms

PART #

PIN 1 ID

SE28.3 STANDARD PKG.

SA28.3 LEAD FREE PKG.

14

1

14

0.394[10.01]

0.419[10.64]

0.291[7.39]

0.300[7.62]

E-PAD

15

28

15

0.026[0.66]

0.032[0.81]

TOP VIEW

BOTTOM VIEW

SEATING PLANE

0.697[17.70]

0.713[18.11]

0.092[2.33]

0.105[2.67]

0.004[0.10]

0.0091[0.23]

0.0125[3.17]

0.050[1.27]

TYP.

0.015[0.38]

0.050[1.27]

0.013[0.33]

0.019[0.48]

0.004[0.10]

0.0118[0.30]

51-85184-*A

Figure 14-1. 28-pin (300-Mil) SOIC EPAD SE28.3 SOIC

Document 38-16008 Rev. **

Page 30 of 32

CYWUSB6935

PRELIMINARY

The recommend dimension of the PCB pad size for the E-PAD underneath the SOIC is 190 mils × 225 mils (width × length).

51-85152-*A

Figure 14-2. 48-pin QFN 7 x 7 mm LF48

The recommended dimension of the PCB pad size for the E-

PAD underneath the QFN is 209 mils × 209 mils (width x

length).

This document is subject to change, and may be found to contain errors of omission or changes in parameters. For feedback or

technical support regarding Cypress WirelessUSB products please contact Cypress at www.cypress.com. WirelessUSB and

enCoRe are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trade-

marks of their respective holders.

Document 38-16008 Rev. **

Page 31 of 32

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CYWUSB6935

PRELIMINARY

Document History Page

Document Title: CYWUSB6935 WirelessUSB™ LR 2.4-GHz DSSS Radio SoC

Document Number: 38-16008

Orig. of

REV.

ECN NO. Issue Date Change

Description of Change

**

207428

See ECN

TGE

New Data Sheet

Document 38-16008 Rev. **

Page 32 of 32

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