请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

CYWB0120AB-BVXI

型号：

CYWB0120AB-BVXI

品牌：

CYPRESS[ CYPRESS ]

页数：

23 页

PDF大小：

425 K

下载PDF手册
CYWB0120AB  
West Bridge® Antioch™-Lite USB/SD  
Controller  
Features  
Applications  
■ SLIM® architecture, enabling simultaneous and independent  
data paths between processor and USB, and between USB  
and mass storage  
■ Cellular Phones  
■ Portable Media Players  
■ Personal Digital Assistants  
■ Digital Cameras  
■ High Speed USB at 480 Mbps  
❐ USB 2.0 compliant  
❐ Integrated USB 2.0 transceiver, smart serial interface engine  
❐ 16 programmable endpoints  
■ Portable Video Recorder  
■ Mass storage device supports MMC/MMC+/SD  
■ Memory mapped interface to main processor  
■ DMA slave support  
■ Ultra low power, 1.8 V core operation  
■ Low power modes  
■ Small footprint, 6x6 mm VFBGA  
■ Selectableclockinputfrequencies:19.2MHz,24MHz,26MHz,  
and 48 MHz  
Logic Block Diagram  
West Bridge Antioch Lite  
Control  
Registers  
8051  
MCU  
P
U
SLIMTM  
Mass Storage Interface  
SD/MMC+  
S
Cypress Semiconductor Corporation  
Document Number: 001-49144 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 19, 2012  
CYWB0120AB  
Contents  
Functional Overview ........................................................3  
The SLIM® Architecture ..............................................3  
8051 Microprocessor ...................................................3  
Configuration and Status Registers .............................3  
Processor Interface (P-Port) ........................................3  
USB Interface (U-Port) ................................................3  
Mass Storage Support (S-Port) ...................................3  
Clocking .......................................................................3  
Power Domains ...........................................................4  
Power Modes ..............................................................5  
Absolute Maximum Ratings ..........................................10  
Operating Conditions .....................................................10  
DC Characteristics .........................................................10  
USB Transceiver .......................................................11  
AC Characteristics .........................................................12  
USB Transceiver .......................................................12  
P-Port Interface .........................................................12  
SD/MMC Parameters ................................................19  
Reset and Standby Timing Parameters ....................20  
Ordering Information ......................................................21  
Ordering Code Definitions .........................................21  
Package Diagrams ..........................................................21  
Acronyms ........................................................................22  
Document Conventions .................................................22  
Units of Measure .......................................................22  
Document History Page .................................................23  
Sales, Solutions, and Legal Information ......................23  
Worldwide Sales and Design Support .......................23  
Products ....................................................................23  
PSoC Solutions .........................................................23  
Document Number: 001-49144 Rev. *C  
Page 2 of 23  
CYWB0120AB  
It then performs the appropriate read or write operations on the  
buffer through the processor interface. This way, the external  
processor only deals with the buffers to access a multitude of  
storage devices connected to Antioch.  
Functional Overview  
The SLIM® Architecture  
The Simultaneous Link to Independent Multimedia (SLIM)  
architecture allows three different interfaces (the P-port, the  
S-port, and the U-port) to connect to one another independently.  
With this architecture, using West Bridge® Antioch™ to connect  
a device to a PC through an USB does not disturb any of the  
functions of the device. It still accesses mass storage at the  
same time the PC is synchronizing with the main processor.  
In the Interrupt mode, Antioch communicates important buffer  
status changes to the external processor using an interrupt  
signal. The external processor then polls Antioch for the specific  
buffers ready for read or write and performs the appropriate read  
or write operations through the processor interface.  
USB Interface (U-Port)  
In accordance with the USB 2.0 specification, Antioch operates  
in Full Speed USB mode in addition to High Speed USB mode.  
The USB interface consists of the USB transceiver. The USB  
interface accesses and also is accessed by both the P-port and  
the S-port.  
The SLIM architecture enables new usage models, in which a  
PC accesses a mass storage device independent of the main  
processor, or enumerates access to both the mass storage and  
the main processor at the same time.  
In a handset, this typically enables the user to use the phone as  
a thumb drive or download media files to the phone while still  
having full functionality available on the phone. The same phone  
functions as a modem to connect the PC to the web.  
The Antioch USB interface supports programmable  
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.  
Mass Storage Support (S-Port)  
8051 Microprocessor  
The S-port is configured to support SD/MMC+ port.  
The 8051 microprocessor embedded in Antioch does basic  
transaction management for all the transactions between the  
P-port, the S-port, and the U-port. The 8051 does not reside in  
the data path; it manages the path. The data path is optimized  
for performance. The 8051 executes firmware that supports SD  
and MMC devices at the S-port.  
SD/MMC Port (S-Port)  
Antioch Lite is configured to support MMC/SD. This interface  
supports:  
■ The MultiMediaCard System Specification, MMCA Technical  
Committee, Version 4.1  
Configuration and Status Registers  
■ SD Memory Card Specification - Part 1, Physical Layer  
Specification, SD Group, Version 1.10, October 15, 2004, and  
Version 2.0, November 9, 2005  
The West Bridge Antioch device includes configuration and  
status registers that are accessible as memory mapped registers  
through the processor interface. The configuration registers  
enable the system to specify specific behavior from Antioch. For  
example, it masks some status registers from raising an  
interrupt. The status registers convey the status of the different  
parameters of Antioch, such as the addresses of buffers for read  
operations.  
West Bridge Antioch provides support for 1-bit and 4-bit SD  
cards: 1-bit, 4-bit, and 8-bit MMC, and MMC+. For the SD,  
MMC/MMC+ card, this block supports one card for one physical  
bus interface.  
Antioch supports SD commands including the multisector  
program command that is handled by the API.  
Processor Interface (P-Port)  
Clocking  
Communication with the external processor is realized through a  
dedicated processor interface. This interface supports both  
synchronous and asynchronous SRAM mapped memory  
accesses. This ensures straightforward electrical  
communications with the processor that also has other devices  
connected on a shared memory bus. Asynchronous accesses  
reach a bandwidth of up to 66.7 MBps. Synchronous accesses  
are performed at 33 MHz across 16 bits for up to 66.7 MBps  
bandwidth.  
Antioch allows either to connect a crystal between the XTALIN  
and XTALOUT balls or connect an external clock at the XTALIN  
ball. The power supply level at the crystal supply XVDDQ  
determines whether a crystal or a clock is provided. If XVDDQ is  
detected as 1.8 V, Antioch assumes that a clock input is  
provided. To connect a crystal, XVDDQ must be 3.3 V. Note that  
the clock inputs at 3.3 V level are not supported.  
CYWB0120AB supports crystals only at 19.2, 24, and 26 MHz.  
At 48 MHz, only clock inputs are supported. Clock inputs are  
supported at all frequencies.  
The memory address is decoded to access any of the multiple  
endpoint buffers inside Antioch. These endpoints serve as  
buffers for data between each pair of ports, for example, between  
the processor port and the USB port. The processor writes and  
reads into these buffers through the memory interface.  
Antioch has an on-chip oscillator circuit that uses an external  
19.2/24/26 MHz (±150 ppm) crystal with the following  
characteristics:  
Access to these buffers is controlled by using either a DMA  
protocol or an interrupt to the main processor. These two modes  
are configured by the external processor.  
■ Parallel resonant  
■ Fundamental mode  
■ 1 mW drive level  
■ 12 pF (5% tolerance) load capacitors[1]  
As a DMA slave, Antioch generates a DMA request signal to  
signify to the main processor that it is ready to read from or write  
to a specific buffer. The external processor monitors this signal  
and polls Antioch for the specific buffers ready for read or write.  
Note  
1. Specified as typical for 24 MHz frequency. Load capacitance varies with crystal vendor specifications and frequency used.  
Document Number: 001-49144 Rev. *C  
Page 3 of 23  
CYWB0120AB  
Figure 1. Capacitor.  
24 MHz  
C1  
C2  
12 pF  
12 pF  
PLL  
12 pF capacitor values assumes a trace capacitance  
of 3 pF per side on a four-layer FR4 PCA  
Table 1. External Clock Requirements  
Parameter  
Specification  
Min Max  
Description  
Unit  
PN_100Hz  
PN_1k  
Input phase noise at 100 Hz offset  
–
–
–75  
–104  
–120  
–128  
–130  
70  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
%
Input phase noise at 1 kHz offset  
Input phase noise at 10 kHz offset  
Input phase noise at 100 kHz offset  
Input phase noise at 1 MHz offset  
Duty cycle  
PN_10k  
PN_100k  
PN_1M  
–
–
–
30  
–
Maximum frequency deviation  
Overshoot  
150  
3
ppm  
–
%
Undershoot  
–
–3  
%
This on-chip PLL multiplies the 19.2/24/26/48 MHz frequency up  
to 480 MHz, as required by the transceiver/PHY. The internal  
counters divide it down for use as the 8051 clock. The 8051 clock  
frequency is 48 MHz. The XTALIN frequency is independent of  
the clock/data rate of the 8051 microprocessor or any of the  
device interfaces (including P-port and S-port). The internal PLL  
applies the proper clock multiply option depending on the input  
frequency.  
UVDDQ: This is the 3.3 V nominal supply for the USB I/O and  
some analog circuits. It also supplies power to the USB  
transceiver.  
VDD33: This supply is required for the power sequence control  
circuits. For more information, see Table 2 on page 6.  
VDD: This is the supply voltage for the logic core. The nominal  
supply voltage level is 1.8 V. This supplies the core logic circuits.  
The same supply is also used for AVDDQ.  
For applications that use an external clock source to drive  
XTALIN, the XTALOUT Ball is left floating. The external clock is  
a square wave that conforms to high and low voltage levels  
mentioned in Table 3 on page 10 and the rise and fall time speci-  
fications in Figure 17 on page 20. The external clock source also  
stops high or low and is not toggling to achieve the lowest  
possible current consumption. The requirements for an external  
clock source are shown in Table 4 on page 11.  
AVDDQ: This is the 1.8 V supply for PLL and USB serializer  
analog components. The same supply is also used for VDD. The  
maximum noise permitted on AVDDQ is 20 mV p-p.  
XVDDQ: This is the clock I/O supply. 3.3 V for XTAL or 1.8 V for  
an external clock.  
Figure 2. Antioch Power Supply Domains  
VDD  
UVDDQ  
*VDDQ  
Power Domains  
Antioch has multiple power domains that serve different  
purposes within the chip.  
D+  
I/O  
D-CORE  
USB-IO  
D-  
*VDDQ: This refers to a group of five independent supply  
domains for the digital I/Os. The nominal voltage level on these  
supplies are 1.8 V, 2.5 V, or 3.3 V. Specifically, the three separate  
I/O power domains are:  
■ PVDDQ – P-port processor interface I/O  
■ SVDDQ – S-port SD interface I/O  
■ GVDDQ – Other miscellaneous I/O  
Document Number: 001-49144 Rev. *C  
Page 4 of 23  
CYWB0120AB  
Noise guideline for all supplies except AVDDQ is a maximum of  
100 mV p-p. All I/O supplies of Antioch are ON when a system  
is active, even if Antioch is not used. The core VDD is also  
deactivated at any time to preserve power, provided that there is  
a minimum impedance of 1 kbetween the VDD Ball and ground.  
All I/Os tristate when the core is disabled.  
completed before Antioch enters Suspend mode (state of  
outstanding transactions are not preserved).  
■ The firmware resumes its operation from where it has  
suspended, because the program counter is not reset.  
■ The only inputs that are sensed are RESET#, GPIO[0], D+, and  
CE#. The last three are wakeup sources (each is individually  
enabled or disabled).  
Power Supply Sequence  
The power supplies are independently sequenced without  
damaging the part. All power supplies are up and stable before  
the device operates. If all supplies are not stable, the remaining  
domains are in low power (standby) mode.  
■ Hard reset is performed by asserting the RESET# input and  
Antioch performs initialization.  
Standby Mode  
Flexible IOs  
Standby mode is a low-power state. This is the lowest power  
mode of Antioch while still maintaining external supply levels.  
This mode is entered through the deassertion of the WAKEUP  
input ball or through internal register settings. It is exited by  
asserting the WAKEUP Ball if the mode is entered by  
deasserting the WAKEUP Ball. Exiting Standby mode is also  
accomplished by asserting CE# LOW or processor writes to  
Internal registers.  
Each of Antioch’s ports operates between 1.8 V and 3.3 V with  
an adjustable slew rate for each port, and adjustable drive  
strength for each port for the I/Os. The slew rate and drive  
strength are controlled by registers.  
Power Modes  
In addition to the normal operating mode, Antioch contains  
several low power modes when normal operation is not required.  
In this mode, the following characteristics apply:  
■ All Configuration register settings and program RAM contents  
are preserved. However, data in the buffers or other parts of  
the data path, if any, is not guaranteed in values. As a result,  
the external processor ensures that the required data is read  
before the Antioch is moved into this Standby mode.  
Normal Mode  
In this mode, Antioch is fully functional. This is the mode, in which  
data transfer functions described in this datasheet are  
performed.  
❐ The program counter is reset upon waking up from Standby  
mode.  
Suspend Mode  
This mode is entered internally by 8051 (external processor only  
initiates entry into this mode through Mailbox commands). This  
mode is exited by the D+ bus going low, GPIO[0] going to a  
predetermined state, or by asserting CE# LOW.  
❐ All outputs are tri-stated (except UVALID), and I/O is placed  
in input only configuration. Values of IOs in Standby mode  
are listed in the Table 2 on page 6.  
❐ Core power supply is retained.  
❐ Hard reset is performed by asserting the RESET# input, and  
In Suspend mode of Antioch:  
■ The clocks are shut off.  
Antioch performs initialization.  
❐ PLL is disabled.  
■ All I/Os maintain their previous state.  
■ Core power supply is retained.  
Core Power Down Mode  
The core power supply VDD is powered down in this mode.  
AVDDQ is tied to the same supply as VDD and as a result, is also  
powered down. The endpoint buffers, configuration registers,  
and the program RAM do not maintain state. It is necessary to  
reload the firmware upon exiting from this mode. All VDDQ  
power supplies (except AVDDQ) must be on and not powered  
down in this mode. VDD33 must remain ON and the requirement  
of a minimum impedance of 1 kbetween the VDD ball and  
ground remains unchanged.  
■ The states of the Configuration registers, endpoint buffers, and  
the program RAM are maintained. All transactions are  
Document Number: 001-49144 Rev. *C  
Page 5 of 23  
CYWB0120AB  
The Ball Assignment table for CYWB0120AB follows.[2, 3, 4]  
Table 2. Ball Assignment  
Power  
Domain  
VFBGA Ball Name  
I/O  
Ball Description  
Standby Reset[5]  
J2  
G1  
H3  
H2  
H1  
J3  
CLK  
CE#  
A[7]  
A[6]  
A[5]  
A[4]  
A[3]  
A[2]  
A[1]  
I
I
I
I
I
I
I
I
I
I
Clock for P-port  
–
–
–
–
–
–
–
–
–
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
Chip Select for P-port. Active LOW  
Bit 7 of Address Bus for P-port  
Bit 6 of Address Bus for P-port  
Bit 5 of Address Bus for P-port  
Bit 4 of Address Bus for P-port  
Bit 3 of Address Bus for P-port  
Bit 2 of Address Bus for P-port  
Bit 1 of Address Bus for P-port  
Bit 0 of Address Bus for P-port  
J1  
K3  
K2  
K1  
G2  
G3  
F1  
F2  
F3  
E1  
E2  
E3  
D1  
D2  
D3  
C1  
C2  
C3  
B1  
B2  
A1  
A[0]  
DQ[15]  
DQ[14]  
DQ[13]  
DQ[12]  
DQ[11]  
DQ[10]  
DQ[9]  
DQ[8]  
DQ[7]  
DQ[6]  
DQ[5]  
DQ[4]  
DQ[3]  
DQ[2]  
DQ[1]  
DQ[0]  
ADV#  
I/O Bit 15 of Data Bus for P-port  
I/O Bit 14 of Data Bus for P-port  
I/O Bit 13 of Data Bus for P-port  
I/O Bit 12 of Data Bus for P-port  
I/O Bit 11 of Data Bus for P-port  
I/O Bit 10 of Data Bus for P-port  
I/O Bit 9 of Data Bus for P-port  
I/O Bit 8 of Data Bus for P-port  
I/O Bit 7 of Data Bus for P-port  
I/O Bit 6 of Data Bus for P-port  
I/O Bit 5 of Data Bus for P-port  
I/O Bit 4 of Data Bus for P-port  
I/O Bit 3 of Data Bus for P-port  
I/O Bit 2 of Data Bus for P-port  
I/O Bit 1 of Data Bus for P-port  
I/O Bit 0 of Data Bus for P-port  
PVDDQ  
VGND  
P-port  
I
Address Valid for P-port. Valid during asynchronous mode.  
ADV# deassertion causes to latch the address.  
Output Enable. Controls the data bus output drive. Ignored  
during write cycle. Active LOW.  
Write Enable. Signals a read (HIGH) or write (LOW) access  
cycle.  
Interrupt Request. Assertion indicates that an interrupt event  
has occurred. Active LOW.  
DMA Request. Assertion indicates to Processor that it is ready  
to read or write one or more endpoints. It reflects register  
CY_AN_MEM_P0_DRQ EPnDRQ assertions. Active LOW or  
HIGH (programmable).  
B3  
A2  
A3  
A4  
OE#  
WE#  
INT#  
DRQ#  
I
–
–
Z
Z
–
–
Z
Z
I
O
O
B4  
DACK#  
I
DMA Acknowledgement. Assertion indicates DMA  
acknowledgement from processor. Is configured in ACK mode  
(asserted throughout DMA transfer) or EOB mode (pulsed at  
end of DMA transfer). Active LOW or HIGH (programmable).  
–
–
Notes  
2. Unused inputs: Must be connected to HIGH/VDD or LOW/GND (negligible difference in current drawn) logic level, through a single 10 K pull-up resistor. The only  
exceptions are WAKEUP, SDCFG and CLK. WAKEUP is tied HIGH for normal operation.CLK is tied LOW for asynchronous P-port operation.  
3. Unused I/Os: For lowest leakage, unused I/Os must be connected to a HIGH logic level. It is recommended that connection to the power supply is through a single  
10 kpull-up resistor for all unused I/Os.  
4. No Antioch balls have internal pull-up or pull-down resistors. Input/output balls may require external pull-up or pull-down resistors depending on the application. The  
pull-up resistors used to indicate speed capability on the USB are included in Antioch and need not be connected externally.  
5. The Reset column indicates the state of signals during reset (RESET# asserted). The Standby column indicates signal state during Standby (low power operating  
mode through WAKEUP deassertion) or core V deactivation.  
DD  
Document Number: 001-49144 Rev. *C  
Page 6 of 23  
CYWB0120AB  
Table 2. Ball Assignment (continued)  
VFBGA Ball Name I/O  
Power  
Domain  
Ball Description  
Standby Reset[5]  
G9  
G10  
F9  
F10  
E9  
E10  
D9  
D10  
F8  
SD_D[7]  
SD_D[6]  
SD_D[5]  
SD_D[4]  
SD_D[3]  
SD_D[2]  
SD_D[1]  
SD_D[0]  
SD_CLK  
I/O Serve as SD_D[7] for SD port  
I/O Serve as SD_D[6] for SD port  
I/O Serve as SD_D[5] for SD port  
I/O Serve as SD_D[4] for SD port  
I/O Serve as SD_D[3] for SD port  
I/O Serve as SD_D[2] for SD port  
I/O Serve as SD_D[1] for SD port  
I/O Serve as SD_D[0] for SD port  
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
SVDDQ  
VGND  
O
Clock output for the SD interface. Frequency is changed and  
clock is disabled through firmware control.  
G8  
H8  
SD_CMD  
SD_POW  
I/O SD Command/Response Ball.  
Z
Z
Z
Z
O
SD Power Control. This GPIO is used to control SD/MMC card  
power FET if present. HIGH indicates on, LOW indicates off.  
SD Write Protection Detection. Connected to GPIO for  
firmware detection. HIGH indicates that the device connected  
to the SD port has write protect enabled.  
H10  
SD_WP  
I
–
–
S-port  
K7  
K8  
J8  
K9  
J9  
H9  
K10  
J10  
K6  
J6  
SD_RSV  
SD_RSV  
SD_RSV  
SD_RSV  
SD_RSV  
SD_RSV  
SD_RSV  
SD_RSV  
NC  
I/O Connect to SVDDQ with 10 K pull-up resistor  
I/O Connect to SVDDQ with 10 K pull-up resistor  
I/O Connect to SVDDQ with 10 K pull-up resistor  
I/O Connect to SVDDQ with 10 K pull-up resistor  
I/O Connect to SVDDQ with 10 K pull-up resistor  
I/O Connect to SVDDQ with 10 K pull-up resistor  
I/O Connect to SVDDQ with 10 K pull-up resistor  
I/O Connect to SVDDQ with 10 K pull-up resistor  
Z
–
–
–
–
–
–
–
Z
Z
Z
Z
Z
Z
–
Z
Z
Z
–
–
–
–
–
–
–
Z
Z
Z
Z
Z
Z
–
Z
Z
SVDDQ  
VGND  
O
O
O
O
O
O
I
Left floating  
Left floating  
Left floating  
Left floating  
Left floating  
Left floating  
Connect to SVDDQ with 10 K pull-up resistor  
Left floating  
NC  
NC  
NC  
NC  
J5  
K4  
H6  
J7  
NC  
J4  
SD_RSV  
NC  
D+  
D–  
UVALID  
K5  
A5  
A6  
A7  
O
I/O/Z USB D+  
I/O/Z USB D–  
Z
Low  
Z
Low  
UVDDQ  
UVSSQ  
U-port  
O
External USB Switch Control. Reflects value of register  
CY_AN_MEM_PMU_UPDATE.UVALID.  
A8  
B8  
XTALIN  
XTALOUT[6]  
RESET#  
I
Input for either crystal or clock signal. XVDDQ is 3.3 V for  
crystal input; XVDDQ is 1.8 V for clock input.  
Output to connect to feedback input of crystal. Is left floating  
when external clock at XTALIN.  
Reset. Asserted to place Antioch into reset mode and subse-  
quent initialization. Active LOW.  
Reset Out. Deasserted LOW when RESET# is asserted LOW.  
Asserted HIGH after RESET# is deasserted and initialization  
is complete. Reflects value of RSTCMPT bit.  
–
Z
–
Z
–
Z
XVDDQ  
VGND  
O
I
C10  
B10  
–
RESETOUT  
O
Low  
Others  
GVDDQ  
VGND  
C9  
D8  
GPIO[1]  
GPIO[0]  
I/O General purpose input/output  
Z
Z
Z
Z
I/O General purpose input/output.GPIO[0] is used for SD Card  
Detect with firmware detection. LOW indicates card is  
inserted.  
C7  
WAKEUP[7]  
I
Wake Up Signal. 1 = normal operation, 0 = low power “sleep”  
mode. Is asserted for Antioch to initialize.  
–
–
Notes  
6. XTALOUT is driven HIGH during Standby mode. XTALOUT operates the same during RESET# assertion and Normal mode: fixed HIGH when XVDDQ is 1.8 V (ext  
clock) and actively toggles when XVDDQ is 3.3 V (crystal).  
7. When RESET# is asserted, the device enters reset state and WAKEUP is ignored.  
Document Number: 001-49144 Rev. *C  
Page 7 of 23  
CYWB0120AB  
Table 2. Ball Assignment (continued)  
Power  
Domain  
VFBGA Ball Name  
I/O  
Ball Description  
Standby Reset[5]  
C5  
XTALSLC[1]  
I
Clock Select. For CYWB0120AB, XTALSLC[1:0] is decoded  
as:  
–
–
00 = 19.2 MHz, 01 = 24 MHz, 10 = 48 MHz, 11 = 26 MHz.  
Clock Select. For CYWB0120AB, XTALSLC[1:0] is decoded  
as:  
C4  
XTALSLC[0]  
I
–
–
00 = 19.2 MHz, 01 = 24 MHz, 10 = 48 MHz, 11 = 26 MHz.  
S-port Configuration. Must be set to ‘1’  
Test mode selection. Is tied to VGND for normal operation  
(CMOS level inputs).  
C6  
E8  
SDCFG  
TEST[2]  
-
I
–
–
–
–
Config  
C8  
D7  
TEST[1]  
TEST[0]  
I
I
Test mode selection. Is tied to VGND for normal operation  
(CMOS level inputs).  
Test mode selection. Is tied to VGND for normal operation  
(CMOS level inputs).  
–
–
–
–
D4, H4  
H5  
B5  
H5, H7  
D6  
B9  
PVDDQ  
SVDDQ  
UVDDQ  
SVDDQ  
GVDDQ  
AVDDQ  
XVDDQ  
Power Power for P-port I/O. 1.8 V, 2.5 V, or 3.3 V nominal.  
Power Power for SD port I/O. 1.8 V, 2.5 V, or 3.3 V nominal.  
Power Power for USB I/O. 3.3 V nominal.  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GVDDQ  
VGND  
Power Power for SD port  
Power Power for miscellaneous I/O. 1.8 V, 2.5 V, or 3.3 V nominal.  
Power Power for internal PLL and USB serializer. 1.8 V nominal.  
Power Power for crystal or clock I/O. 1.8 V (clock) or 3.3 V (crystal)  
nominal.  
B7  
D5, G4,  
G5, G6,  
G7, F7  
A10  
B6  
A9  
E4, E5,  
E6, E7,  
F4, F5,  
F6  
VDD  
Power Power for core. 1.8 V nominal.  
–
–
Power  
VDD33[8] Power Power sequence control supply. 3.3 V nominal.  
UVSSQ  
AVSSQ  
VGND  
–
–
–
–
–
–
–
–
Power Ground for all USB  
Power Ground for PLL  
Power Ground for core  
Note  
8. VDD33: In CYWB0120AB, the Ball is no-connect internally. It handles power sequence control in future West Bridge products. When migrating to Astoria, it is connected  
to the highest supply to the device. If USB is used, for example, then VDD33 is connected to nominal 3.3 V (because 3.3 V is required for USB). VDD33 is always  
supplied in Astoria.  
Document Number: 001-49144 Rev. *C  
Page 8 of 23  
CYWB0120AB  
Figure 3. CYWB0120AB 100 VFBGA  
Top View  
1
2
3
4
5
6
7
8
9
10  
A
B
C
D
E
F
ADV#  
WE#  
INT#  
DRQ#  
D+  
D-  
UVALID  
XTALIN  
AVSSQ  
VDD33  
A
B
C
D
E
F
DQ[1]  
DQ[4]  
DQ[7]  
DQ[10]  
DQ[13]  
CE#  
DQ[0]  
DQ[3]  
DQ[6]  
DQ[9]  
DQ[12]  
DQ[15]  
A[6]  
OE#  
DQ[2]  
DQ[5]  
DQ[8]  
DQ[11]  
DQ[14]  
A[7]  
DACK#  
UVDDQ  
UVSSQ  
SDCFG  
GVDDQ  
VGND  
VGND  
VDD  
XVDDQ  
WAKEUP  
TEST[0]  
VGND  
VDD  
XTALOUT  
TEST[1]  
GPIO[0]  
AVDDQ RESETOUT  
XTALSLC[0] XTALSLC[1]  
GPIO[1]  
SD_D[1]  
SD_D[3]  
SD_D[5]  
SD_D[7]  
SD_RSV  
SD_RSV  
RESET#  
SD_D[0]  
SD_D[2]  
SD_D[4]  
SD_D[6]  
SD_WP  
SD_RSV  
PVDDQ  
VGND  
VDD  
VGND  
VGND  
VDD  
TEST[2]  
SD_CLK  
SD_CMD  
SD_POW  
SD_RSV  
VGND  
G
H
J
VDD  
VDD  
G
H
J
A[5]  
PVDDQ  
SD_RSV  
SVDDQ  
NC  
NC  
SVDDQ  
NC  
A[3]  
CLK  
A[4]  
NC  
K
A[0]  
1
A[1]  
2
A[2]  
3
NC  
4
NC  
5
NC  
6
SD_RSV  
7
SD_RSV  
8
SD_RSV  
9
SD_RSV  
10  
K
POWER DOMAIN KEY  
UVDDQ  
GVDDQ  
SVDDQ  
VGND  
PVDDQ  
Document Number: 001-49144 Rev. *C  
Page 9 of 23  
CYWB0120AB  
Static Discharge Voltage (ESD) from JESD22-A114> 2,000 V  
Latch-Up Current....................................................> 200 mA  
Absolute Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. User guidelines are not tested.  
Maximum Output Short Circuit Current  
for all I/O Configurations. (Vout = 0 V)[9] ................. –100 mA  
Storage Temperature............................... –65 °C to +150 °C  
Operating Conditions  
Ambient Temperature with  
Power Supplied (Industrial) ....................... –40 °C to +85 °C  
TA (Ambient Temperature Under Bias)  
Industrial..................................................... –40 °C to +85 °C  
Supply Voltage to Ground Potential  
VDD, AVDDQ ...............................................–0.5 V to +2.0 V  
VDD, AVDDQ Supply Voltage ..........................1.7 V to 1.9 V  
UVDDQ Supply Voltage....................................3.0 V to 3.6 V  
GVDDQ, PVDDQ, SVDDQ,  
UVDDQ and VDD33 and XVDDQ ................–0.5 V to +4.0 V  
PVDDQ, GVDDQ, SVDDQ  
Supply Voltage..................................................1.7 V to 3.6 V  
DC Input Voltage to Any Input Ball .................1.89 V to 3.6 V  
(Depends on I/O supply voltage. Inputs are not over  
voltage tolerant)  
XVDDQ (Crystal I/O) Supply Voltage ...............3.0 V to 3.6 V  
XVDDQ (Ext. Clock I/O) Supply Voltage ..........1.7 V to 1.9 V  
DC Voltage Applied to  
Outputs in High Z State ..................... –0.5 V to VDDQ+0.5 V  
DC Characteristics  
Table 3. DC Specifications for All Voltage Supplies  
Parameter  
VDD  
Description  
Core voltage supply  
Analog voltage supply  
Crystal voltage supply  
Clock voltage supply  
Processor interface I/O  
Conditions  
Min  
1.7  
1.7  
3.0  
1.7  
1.7  
Typ  
1.8  
Max  
1.9  
1.9  
3.6  
1.9  
3.6  
Unit  
V
AVDDQ  
XVDDQ  
XVDDQ  
1.8  
V
3.3  
V
1.8  
V
PVDDQ[11]  
GVDDQ[11]  
1.8, 2.5, 3.3  
V
Miscellaneous I/O voltage  
supply  
1.7  
1.8, 2.5, 3.3  
3.6  
V
SVDDQ[10,11]  
UVDDQ[13]  
VDD33  
S-port SD I/O voltage supply  
USB voltage supply  
1.7  
3.0  
3.0  
1.8, 2.5, 3.3  
3.6  
3.6  
3.6  
V
V
V
3.3  
3.3  
Power sequence control  
supply  
[12]  
Input HIGH voltage 1  
Input HIGH voltage 2  
All ports except USB, 2.0 V < VCC < 3.6 V 0.625*VCC  
All ports except USB, 1.7 V < VCC < 2.0 V VCC – 0.4  
–0.3  
VCC + 0.3  
VCC + 0.3  
0.25*VCC  
V
VIH1  
[12]  
VIH2  
VIL  
Input LOW voltage  
V
V
VOH  
VOL  
IIX  
Output HIGH voltage  
Output LOW voltage  
Input leakage current  
Output leakage current  
IOH(MAX) = –0.1 mA  
IOL(MIN) = 0.1 mA  
0.9*VCC  
0.1*VCC  
V
All I/O signals held at VDDQ  
All I/O signals held at VDDQ  
Outputs tristated  
–1  
–1  
1
1
A  
A  
mA  
IOZ  
I
CC Core  
Operating current of core  
voltage supply (VDD) and  
analog voltage supply  
(AVDDQ)  
110  
Notes  
9. Do not test more than one output at a time. Duration of the short circuit does not exceed 1 second. Tested initially, and after any redesign or process changes, may  
affect these parameters.  
10. The SVDDQ I/O voltage is dynamically changed (for example, from high range to low range) as long as the supply voltage undershoot does not surpass the lower  
minimum voltage limit. SVDDQ levels for SD modes: 2.0 V–3.6 V, MMC modes: 1.7 V–3.6 V.  
11. Interfaces with a voltage range are adjustable with respect to the I/O voltage and thus support multiple I/O voltages.  
12. V = pertinent VDDQ value.  
CC  
13. When U-port is in a disabled state, UVDDQ goes down to 2.4 V, provided UVDDQ is still the highest supply voltage level.  
Document Number: 001-49144 Rev. *C  
Page 10 of 23  
CYWB0120AB  
Table 3. DC Specifications for All Voltage Supplies (continued)  
Parameter  
Description  
Conditions  
Min  
Typ  
Max  
Unit  
ICC Crystal  
Operating current of crystal XTALOUT Floating  
voltage supply (XVDDQ)[16]  
5
mA  
ICC USB  
ISB1  
Operating current of USB  
Operating and terminated for High Speed  
25  
mA  
voltage supply (UVDDQ)[16] mode  
250[14]  
Total standby current of  
Antioch when device is in  
suspend mode  
1. *VDDQ = 3.3 V Nominal (3.0–3.6 V)  
2500  
A  
2. Outputs and Bidirs High or Floating[15]  
3. XTALOUT Floating  
4. D+ Floating (no current drawn through  
internal 1.5 kpull-up), D– Grounded,  
UVALID Driven LOW  
5. Device in Suspend Mode  
ISB2  
Total standby current of  
Antioch when device is in  
standby mode  
1. *VDDQ = 3.3 V Nominal  
(3.0–3.6 V)  
25 °C  
85 °C  
45  
A  
A  
2. Outputs and Bidirs High or  
Floating[15]  
290  
3. XTALOUT Floating  
4. D+ Floating, D– Grounded,  
UVALID Driven LOW  
ISB3  
Total standby current of  
Antioch when device is in  
core power-down mode  
1. Outputs and Bidirs High or  
Floating[15]  
2. XTALOUT Floating  
3. D+ Floating, D– Grounded,  
UVALID Driven LOW  
4. Core Powered Down  
25 °C  
85 °C  
25  
139  
Table 4. Capacitance  
Parameter  
Description  
Conditions  
Typ  
Max  
9
Unit  
CIN  
Input Ball Capacitance, Except D+/D– TA = 25 °C, f = 1 MHz,  
pF  
VCC = VCCIO  
Input Ball Capacitance, D+/D–  
15  
10  
COUT  
Output Ball Capacitance  
pF  
USB Transceiver  
USB 2.0 compliant in full speed and high speed modes.  
Notes  
14. Isb1 typical value is not a maximum specification but a typical value. Isb1 maximum current value specified for 85 °C.  
15. The Outputs/Bidirs that are forced low in Standby mode increases I/O supply standby current beyond specified value.  
16. Active Current Conditions:  
-UVDDQ: USB transmitting 50% of the time, receiving 50% of the time.  
-PVDDQ/SVDDQ/GVDDQ: Active Current Depends on IO activity, bus load, and supply level.  
-XVDDQ: Assume highest frequency clock (48 MHz) or crystal (26 MHz).  
Document Number: 001-49144 Rev. *C  
Page 11 of 23  
CYWB0120AB  
AC Characteristics  
USB Transceiver  
USB 2.0 compliant in full speed and high speed modes.  
P-Port Interface  
Asynchronous Mode Timing Parameters  
Table 5. Asynchronous Mode Timing Parameters  
Parameter  
Description  
Min  
Max  
Unit  
Read Timing Parameters  
tAA  
Address to data valid  
–
3
–
–
5
30  
–
ns  
ns  
ns  
ns  
ns  
ns  
tOH  
Data output hold from address change  
Chip enable to data valid  
tEA  
30  
30  
–
tAADV  
tAVS  
tAVH  
ADV# to data valid access time  
Address valid to ADV# HIGH  
ADV# HIGH to address hold  
2[18]  
5
–
tCVS  
tVPH  
CE# Low setup time to ADV# HIGH  
ADV# HIGH time  
–
–
ns  
ns  
15[17]  
tVP  
ADV# pulse width LOW  
OE# LOW to data valid  
OE# LOW to Low Z  
OE# HIGH to High Z  
CE# LOW to Low Z  
CE# HIGH to High Z  
7.5  
–
–
22.5  
–
ns  
ns  
ns  
ns  
ns  
ns  
tOE  
tOLZ  
tOHZ  
tLZ  
3
0
22.5  
–
3
tHZ  
–
22.5  
Write Timing Parameters  
tCW  
CE# LOW to write end  
30  
30  
0
–
–
–
–
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAW  
Address valid to write end  
Address setup to write start  
ADV# setup to write start  
WE# pulse width  
tAS  
tADVS  
tWP  
0
22  
10  
10  
5
tWPH  
tCPH  
tAVS  
tAVH  
WE# HIGH time  
CE# HIGH time  
Address valid to ADV# HIGH  
ADV# HIGH to address hold  
2[18]  
5
tCVS  
tVPH  
CE# LOW setup time to ADV# HIGH  
ADV# HIGH time  
–
–
ns  
ns  
15[17]  
7.5  
30  
18  
0
tVP  
ADV# pulse width LOW  
–
–
ns  
ns  
ns  
ns  
ns  
ns  
tVS  
ADV# LOW to End of Write  
Data setup to write end  
tDW  
tDH  
–
Data hold from write end  
WE# Low to DQ High Z output  
WE# High to DQ Low Z output  
–
tWHZ  
tWLZ  
–
22.5  
–
3
Notes  
17. In applications where access cycle time is at least 60 ns, t  
is relaxed to 12 ns.  
VPH  
18. In applications where back-to-back accesses are not performed on different endpoint addresses, the minimum t  
specification is relaxed to 0 ns.  
AVH  
Document Number: 001-49144 Rev. *C  
Page 12 of 23  
CYWB0120AB  
Figure 4. Asynchronous Single Read Timing  
Valid Address  
tAA  
A
tVPH  
tAVS  
tAVH  
ADV#  
CE#  
tHZ  
tVP  
tAADV  
tEA  
tOE  
OE#  
tOHZ  
WE#  
DQ  
tOLZ  
High Z  
Valid Output  
tLZ  
Figure 5. Asynchronous Back-to-Back Read Timing  
Valid Address  
tAA  
Valid Address  
tOH  
A
tVPH  
tAVS  
tAVH  
ADV#  
CE#  
tHZ  
tVP  
tAADV  
tEA  
OE#  
tOHZ  
WE#  
DQ  
High Z  
Valid Output  
Valid Output  
tLZ  
Document Number: 001-49144 Rev. *C  
Page 13 of 23  
CYWB0120AB  
Figure 6. Asynchronous Back-to-Back Write Timing  
Valid Address  
Valid Address  
A
tAVS  
tVP  
tAVH  
tVPH  
ADV#  
CE#  
tVS  
tCW  
OE#  
WE#  
tAW  
tWPH  
tWP  
tOW  
tAS  
tADVS  
tDH  
tDW  
High Z  
Valid Input  
Valid Input  
DQ_IN  
tWHZ  
tLZ  
DQ_OUT  
Figure 7. Asynchronous Read to Write Timing  
A
Valid Address  
Valid Address  
Valid Address  
tAA  
tAVS  
tAVH  
ADV#  
tVPH  
tVPH  
tAVS  
tAVH  
tVP  
tVP  
tVS  
tAADV  
CE#  
tEA  
tOE  
OE#  
WE#  
tOHZ  
tAW  
tWP  
tOW  
tDH  
tDW  
tAS  
High Z  
Valid Input  
Valid Input  
DQ_IN  
tOLZ  
tWHZ  
High Z  
DQ_OUT  
Valid Output  
tLZ  
Document Number: 001-49144 Rev. *C  
Page 14 of 23  
CYWB0120AB  
Figure 8. Asynchronous Write to Read Timing  
Valid Address  
tAVS  
tVP  
Valid Address  
A
tAA  
tAVH  
tAVS  
tAVH  
ADV#  
CE#  
tVP  
tVS  
tAADV  
tOE  
OE#  
WE#  
tAW  
tWP  
tDH  
tDW  
tAS  
Valid Input  
DQ_IN  
tOLZ  
tWHZ  
DQ_OUT  
Valid Output  
Synchronous Mode Timing Parameters  
Table 6. Synchronous Mode Timing Parameters  
Parameter  
FREQ  
Description  
Interface clock frequency  
Clock Period  
Conditions  
Min  
Max  
33  
–
Unit  
MHz  
ns  
–
30  
12  
12  
7.5  
1.5  
–
tCLK  
tCLKH  
tCLKL  
tS  
Clock HIGH time  
–
ns  
Clock LOW time  
–
ns  
CE#/WE#/ADDR/DQ setup time  
CE#/WE#/ADDR/DQ hold time  
Clock to valid data  
–
ns  
tH  
–
ns  
tCO  
18  
–
ns  
tOH  
Clock to data hold time  
OE# HIGH to data High Z  
OE# LOW to data Low Z  
OE# LOW to data valid  
WE# Low to DQ High Z output  
WE# High to DQ Low Z output  
2
ns  
tHZ  
–
22.5  
–
ns  
tLZ  
3
ns  
tOE  
–
22.5  
22.5  
–
ns  
tWHZ  
tWLZ  
tCKHZ  
–
ns  
3
ns  
Clock to Data High Z (Figure 12 on page 17) Measured from the rising edge of the  
–
18  
ns  
second clock after the deassertion of  
CE#islatchedbytherisingedgeofthe  
clock.  
tCKLZ  
Clock to Data Low Z (Figure 14 on page 18)  
3
–
ns  
Document Number: 001-49144 Rev. *C  
Page 15 of 23  
CYWB0120AB  
Figure 9. Synchronous Write Timing  
tCLKH  
tCLKL  
tCLK  
CLK  
CE#  
tH  
tS  
A[7:0]  
An+1  
An+2  
An  
An+3  
WE#  
OE#  
DQ[15:0]  
(input)  
Dn+1  
Dn+2  
Dn  
Dn+3  
DQ[15:0] High Z  
(output)  
Note:  
- Assumes previous cycle had CE# deselected  
- OE# is don’t care during write operations  
Figure 10. Synchronous Read Timing  
tCLKH  
tCLKL  
tCLK  
CLK  
CE#  
tH  
tS  
A[7:0]  
An+1  
An+2  
An  
An+3  
An+4  
WE#  
OE#  
High Z  
High Z  
DQ[15:0]  
(input)  
tLZ  
tHZ  
tOH  
Dn  
tCO  
DQ[15:0]  
(output)  
Dn+1  
tOE  
Note:  
- Assumes previous cycle had CE# deselected  
Document Number: 001-49144 Rev. *C  
Page 16 of 23  
CYWB0120AB  
Figure 11. Synchronous Read (OE# Fixed LOW) Timing  
CLK  
CE#  
tH  
tS  
A[7:0]  
Ax+1  
Ax+2  
Ax  
WE#  
OE#  
tCKHZ  
Dx+1  
tOH  
Dx-1  
tCO  
DQ[15:0]  
(output)  
Dx-2  
Dx  
Dx  
Note:  
- Assumes previous several cycles were Read  
Figure 12. Synchronous Read to Write (OE# Controlled) Timing  
tCLKH  
tCLKL  
tCLK  
CLK  
CE#  
tH  
tS  
A[7:0]  
Ax+1  
An  
An+2  
Ax  
An+1  
Dn+1  
WE#  
OE#  
tH  
tS  
Dn  
High Z  
Note:  
DQ[15:0]  
(input)  
Dn+2  
tOH  
Dx-1  
tCO  
tHZ  
Dx  
DQ[15:0]  
(output)  
Dx-2  
- Assumes previous several cycles were Read  
- (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline.  
Document Number: 001-49144 Rev. *C  
Page 17 of 23  
CYWB0120AB  
Figure 13. Synchronous Read to Write (OE# Fixed LOW) Timing  
tCLKH  
tCLKL  
tCLK  
CLK  
CE#  
tH  
tS  
A[7:0]  
Ax+1  
Ax+2  
Ax  
An  
An+1  
Dn+1  
WE#  
OE#  
tWHZ  
tH  
Dn  
tS  
High Z  
DQ[15:0]  
(input)  
tCO  
tOH  
Dx-1  
DQ[15:0]  
(output)  
Dx  
Dx-2  
tCO  
Note:  
- Assumes previous several cycles were Read  
- In this scenario, OE# is held LOW  
- (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline.  
- No operation is performed during the Ax+2 cycle (true turnaround operation)  
Figure 14. Synchronous Write to Read Timing  
tCLKH  
tCLKL  
tCLK  
CLK  
CE#  
tH  
tH  
tS  
tS  
A[7:0]  
An+1  
Dn+1  
An+2  
An+4  
An  
Dn  
An+3  
WE#  
OE#  
tWLZ  
DQ[15:0]  
(input)  
tOH  
tCO  
High Z  
DQ[15:0]  
(output)  
Dn+2  
tCKLZ  
Note:  
- Assumes previous cycle has CE# deselected  
- In this scenario, OE# is held LOW  
Document Number: 001-49144 Rev. *C  
Page 18 of 23  
CYWB0120AB  
SD/MMC Parameters  
Figure 15. SD/MMC Timing Waveform - All Modes  
tSDCLKH  
tSDCLK  
SD_CLK  
tSDCLKL  
tSDOS  
tSDOH  
tSDCKLZ  
tSDCKHZ  
SD_CMD/  
SD_D0-D3  
Output  
SD_CMD/  
SD_D0-D3  
Input  
tSDIH  
tSDIS  
Table 7. Common Timing Parameters for SD and MMC – During Identification Mode  
Parameter  
SDFREQ  
tSDCLK  
Description  
SD_CLK interface clock frequency  
Clock period  
Min  
–
Max  
400  
–
Unit  
kHz  
s  
2.5  
1.0  
1.0  
tSDCLKH  
tSDCLKL  
Clock high time  
–
s  
Clock low time  
–
s  
Table 8. Common Timing Parameters for SD and MMC – During Data Transfer Mode  
Parameter  
SDFREQ  
tSDCLK  
Description  
SD_CLK interface clock frequency  
Clock period  
Min  
5
Max  
48  
200  
60  
3
Unit  
MHz  
ns  
20.8  
40  
–
tSDCLKOD  
tSCLKR  
Clock duty cycle  
%
Clock rise time  
ns  
tSCLKF  
Clock fall time  
–
3
ns  
Table 9. Timing Parameters for SD – All Modes  
Parameter Description  
tSDIS Input setup time  
Min  
4
Max  
–
Unit  
ns  
tSDIH  
Input hold time  
2.5  
7
–
ns  
tSDOS  
Output setup time  
Output hold time  
Clock to Data High Z  
Clock to Data Low Z  
–
ns  
tSDOH  
6
–
ns  
tSDCKHZ  
tSDCKLZ  
–
18  
–
ns  
3
ns  
Table 10. Timing Parameters for MMC – All Modes  
Parameter Description  
tSDIS Input setup time  
Min  
4
Max  
–
Unit  
ns  
tSDIH  
Input hold time  
4
–
ns  
tSDOS  
Output setup time  
Output hold time  
Clock to Data High Z  
Clock to Data Low Z  
6
–
ns  
tSDOH  
6
–
ns  
tSDCKHZ  
tSDCKLZ  
–
18  
–
ns  
3
ns  
Document Number: 001-49144 Rev. *C  
Page 19 of 23  
CYWB0120AB  
Reset and Standby Timing Parameters  
Figure 16. Reset and Standby Timing Diagram  
Core  
Power-Down  
VDD  
(core)  
VDDQ  
(I/O)  
XTALIN up & stable  
before WAKEUP  
asserted  
XTALIN  
tWPW  
tWU  
tWH  
Standby  
Mode  
tRR  
WAKEUP  
Mandatory  
Reset Pulse  
Mandatory  
Reset Pulse  
tRH  
Hard Reset  
RESET#  
Firmware Init  
Complete  
Firmware Init  
Complete  
Firmware Init  
Complete  
High-Z  
tRPW  
RESETOUT  
UVALID  
USB Switch  
Disabled  
USB Switch  
Enabled  
tSLP  
CY_AN_MEM_PMU_UPDATE.UVALID  
bit is set to ‘0’  
CY_AN_MEM_PMU_UPDATE.UVALID  
bit is set to ‘0’  
CY_AN_MEM_PMU_UPDATE.UVALID  
bit is set to ‘1’  
Table 11. Reset and Standby Timing Parameters  
Parameter  
tSLP  
Description  
Conditions  
Min  
–
Max  
1
Unit  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
Sleep time  
tWU  
WAKEUP time from standby mode  
Clock on XTALIN  
1
–
Crystal on XTALIN-XTALOUT  
5
5
5
5
1
5
1
–
tWH  
WAKEUP high time  
WAKEUP pulse width  
RESET# high time  
RESET# pulse width  
–
tWPW  
tRH  
–
–
tRPW  
Clock on XTALIN  
–
Crystal on XTALIN-XTALOUT  
–
tRR  
RESET# recovery time  
–
Figure 17. AC Test Loads and Waveforms  
Document Number: 001-49144 Rev. *C  
Page 20 of 23  
CYWB0120AB  
Ordering Information  
Ordering Code  
CYWB0120AB-BVXI  
CYWB0120AB-BVXIT  
Turbo-MTP Enabled  
No  
Package Type  
Available Clock Input Frequencies (MHz)  
19.2, 24, 26, 48  
100 VFBGA – Pb-Free  
Ordering Code Definitions  
AB  
I
T
BV X  
CY WB 0120  
Tape and Reel  
Temperature range: I = Industrial  
Pb-free  
100-ball VFBGA  
A generation  
Antioch-lite Bridge  
Family: West Bridge  
Company ID: CY = Cypress  
Package Diagrams  
Figure 18. 100 VFBGA (6 x 6 x 1.0 MM) BZ100A  
51-85209 *D  
Document Number: 001-49144 Rev. *C  
Page 21 of 23  
CYWB0120AB  
Acronyms  
Document Conventions  
Units of Measure  
Acronym  
DMA  
MMC  
MTP  
PLL  
Description  
direct memory access  
Symbol  
°C  
Unit of Measure  
multimedia card  
media transfer protocol  
phase-locked loop  
secure digital  
degree Celsius  
microampere  
millisecond  
milliampere  
megabytes per second  
megahertz  
nanosecond  
ohm  
µA  
ms  
mA  
Mbps  
MHz  
ns  
SD  
I/O  
input / output  
USB  
universal serial bus  
pF  
picofarad  
V
volt  
Document Number: 001-49144 Rev. *C  
Page 22 of 23  
CYWB0120AB  
Document History Page  
Document Title: CYWB0120AB West Bridge® Antioch™-Lite USB/SD Controller  
Document Number: 001-49144  
Orig. of  
Change  
Submission  
Date  
Revision  
ECN  
Description of Change  
**  
*A  
*B  
2574764 OGC/AESA 11/11/2008 New release  
2746360  
3525332  
OGC  
07/30/2009 Replaced NC on ball map J4 with SD_RSV  
PRVE  
02/15/2012 Updated Ordering Information (CYWB0120AB-BVXIT).  
Package Diagrams updated 51-85209 from Rev *B to *D.  
Added Acronyms, Document Conventions, Ordering Code Definitions, and Table  
of Contents.  
*C  
3555122  
AASI  
03/19/2012 Post the datasheet to Cypress.com.  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at Cypress Locations.  
Products  
PSoC Solutions  
Automotive  
cypress.com/go/automotive  
cypress.com/go/clocks  
cypress.com/go/interface  
cypress.com/go/powerpsoc  
cypress.com/go/plc  
psoc.cypress.com/solutions  
PSoC 1 | PSoC 3 | PSoC 5  
Clocks & Buffers  
Interface  
Lighting & Power Control  
Memory  
cypress.com/go/memory  
cypress.com/go/image  
cypress.com/go/psoc  
Optical & Image Sensing  
PSoC  
Touch Sensing  
USB Controllers  
Wireless/RF  
cypress.com/go/touch  
cypress.com/go/USB  
cypress.com/go/wireless  
© Cypress Semiconductor Corporation, 2005-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-49144 Rev. *C  
Revised March 19, 2012  
Page 23 of 23  
Astoria™ is the trademark and PSoC® and West Bridge® are the registered trademarks of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the  
trademarks of their respective holders.  
厂商 型号 描述 页数 下载

CYPRESS

 		CYW134MOXC 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

CYPRESS

 		CYW134MOXCT 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

CYPRESS

 		CYW134SOXC 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

CYPRESS

 		CYW134SOXCT 直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ] 12 页

SPECTRALINEAR

 		CYW137OXC FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ] 8 页

SPECTRALINEAR

 		CYW137OXCT FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ] 8 页

SILICON

 		CYW150 [ 440BX AGPset Spread Spectrum Frequency Synthesizer ] 15 页

SILICON

 		CYW150OXC [ 440BX AGPset Spread Spectrum Frequency Synthesizer ] 15 页

SILICON

 		CYW150OXCT [ 440BX AGPset Spread Spectrum Frequency Synthesizer ] 15 页

CYPRESS

 		CYW15G0101DXB 单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ] 39 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于达普

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：smail@ic72.com

服务时间：周一至周六 8:30-17:30

达普官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.211477s