CYW43143KMLGT,PDF,CYW43143KMLGT PDF资料,Datasheet,下载CYW43143KMLGT技术资料

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CYW43143

Single Chip IEEE 802.11 b/g/n MAC/PHY/Radio with

USB/SDIO Host Interface

The CYW43143 is a single-band, single-stream, IEEE 802.11n compliant, MAC/PHY/Radio system-on-a-chip with internal 2.4 GHz

Power Amplifier (PA) and integrated T/R switch. The CYW43143 supports internal RX diversity by providing two antenna ports. The

device enables development of USB or SDIO 802.11n WLAN clients that can take advantage of the high throughput and extended

range of Cypress second-generation solution. The CYW43143 maintains compatibility with legacy IEEE 802.11b/g devices.

State-of-the-art security is provided by industry standard support for WPA, WPA2 (802.11i), and hardware-accelerated AES

encryption/decryption, coupled with TKIP, IEEE 802.1X support, and a WLAN Authentication and Privacy Infrastructure (WAPI)

hardware engine.

Embedded hardware acceleration enables increased system performance and reduced host-CPU utilization in both client and access

point configurations. The CYW43143 also supports Cypress widely accepted and deployed WPS to easily secure WLAN networks.

■ SDIO and USB wireless client modules for digital TVs, Blu-ray Disc^®players, set-top boxes, game consoles, and printers.

■ Supports the I²S digital audio interface.

■ Stand-alone wireless USB dongles and multimedia streaming boxes.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

BCM43143

CYW43143

BCM43143KMLG

CYW43143KMLG

Features

Supports 3.3V ±10% power supply input with high efficiency

Power Management Unit (PMU).

■ Full IEEE 802.11b/g legacy compatibility with enhanced perfor-

mance.

■ Programmable dynamic power management.

■ Eight GPIOs with multiplexed JTAG interface.

■ Supports Cypress OneDriver™ software.

■ Supports drivers for Windows^®, Linux^®, and Android™

operating systems.

■ Complies with USB 2.0 specification and link power

management.

■ Comprehensive wireless network security support that

includesWPA,WPA2, andAESencryption/decryption, coupled

with TKIP, IEEE 802.1X support, and a WAPI encryption/

decryption engine.

■ Supports standard SDIO v2.0 (50 MHz, 4-bit and 1-bit) and

USB host interfaces.

■ 20 MHz reference clock.

■ Single stream IEEE 802.11n support for 20 MHz and 40 MHz

channels provides PHY layer rates up to 150 Mbps for typical

upper-layer throughput in excess of 90 Mbps.

IEEE 802.11x Key Features:

■ IEEE 802.11n compliant.

■ Supports the IEEE 802.11n RX space-time block coding

(STBC) and low-density parity check (LDPC) options for

improved range and power efficiency.

■ 2.4 GHz internal PA.

■ Internal T/R and RX diversity switches.

■ Supports MCS 0–7 coding rates.

■ Support for Short Guard Interval (SGI).

■ Supports an IEEE 802.15.2 external coexistence interface to

optimize bandwidth utilization with other colocated wireless

technologies such as GPS, WiMAX, LTE, Bluetooth, and UWB.

■ Supports USB 2.0, standard SDIO v2.0 (50 MHz,

4-bit and 1-bit) host interfaces.

■ Integrated ARM Cortex-M3 processor and on-chip memory for

complete WLAN subsystem functionality, minimizing the need

to wake up the applications processor for standard WLAN

functions. This allows for further minimization of power

consumption while maintaining the ability to field upgrade with

future features. On-chip memory includes 448 KB SRAM and

256 KB ROM.

■ Supports the I²S audio interface.

■ Greenfield, mixed mode, and legacy mode support.

■ 802.11n MPDU/MSDU aggregation support for high

throughput.

Cypress Semiconductor Corporation

Document Number: 002-15045 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 20, 2017

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CYW43143

■ USB 2.0 with Link Power Management (LPM) for low power

standby application.

■ Single stream IEEE 802.11n support for 20 MHz and 40 MHz

channels provides PHY layer rates up to 150 Mbps for typical

upper-layer throughput in excess of 90 Mbps.

■ SDIO out of band low power application.

■ Supports the IEEE 802.11n RX space-time block coding

(STBC) and low-density parity check (LDPC) options for

improved range and power efficiency.

■ Integrated One Time Programmable (OTP) memory to save

configuration settings.

Package options:

■ 7 mm × 7 mm, 56-pin QFN package.

Figure 1.CYW43143 High-Level Block Diagram

CYW43143

IEEE

JTAG

PA

JTAG

USB

IEEE

802.11n

MAC

IEEE

802.11n

PHY

RF Front

End

802.11n

2.4 GHz

Radio

2.4 GHz

USB 2.0

Device

(switches)

Security

SDIO or

I²S

Interface

SDIO or I²S

Interface

Serial

Flash

Interface

OTP

(2 Kbits)

GPIO

FLASH

Memory

IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website

(http://community.cypress.com/).

Document Number: 002-15045 Rev. *F

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CYW43143

Contents

1. Introduction ...................................................................4

2. Power Management and Resets ..................................6

2.1 Power Management .............................................. 6

2.2 Power Topology .................................................... 6

2.3 Reset and Low-Power Off Mode ........................... 6

3. WLAN Global Functions ..............................................7

3.1 GPIO Interface ...................................................... 7

3.2 OTP....................................................................... 7

3.3 JTAG Interface ...................................................... 7

3.4 Crystal Oscillator ................................................... 7

4. WLAN USB 2.0 Host Interface .....................................8

4.1 Link Power Management (LPM) Support .............. 8

4.2 I²S Interface .......................................................... 9

5. SDIO Interface .............................................................10

6. Wireless LAN MAC and PHY .....................................11

6.1 IEEE 802.11n MAC Description .......................... 11

6.2 IEEE 802.11n PHY Description........................... 12

6.3 Single-Band Radio Transceiver........................... 13

7. Pin Assignments ........................................................14

7.1 56-Pin QFN Assignments.................................... 14

8. Signal and Pin Descriptions ......................................18

8.1 Package Signal Descriptions............................... 18

8.2 Strapping Options................................................ 20

9. Electrical Characteristics ...........................................22

9.1 Absolute Maximum Ratings................................. 22

9.2 Recommended Operating Conditions and

DC Characteristics .............................................. 22

9.3 WLAN Current Consumption............................... 23

10. Regulator Electrical Specifications ........................25

10.1 Core Buck Switching Regulator......................... 25

10.2 CLDO ................................................................ 25

10.3 LNLDO .............................................................. 26

11. WLAN Specifications ...............................................28

11.1 2.4 GHz Band General RF Specifications......... 28

11.2 2.4 GHz Band Receiver RF Specifications........ 28

11.3 2.4 GHz Band Transmitter RF Specifications.... 29

11.4 2.4 GHz Band Local Oscillator Specifications... 30

12. Antenna Specifications ............................................31

12.1 Voltage Standing Wave Ratio ........................... 31

13. Timing Characteristics .............................................32

13.1 Power Sequence Timing ................................... 32

13.2 Serial Flash Timing............................................ 33

13.3 I²S Slave Mode Tx Timing................................. 34

13.4 SDIO Default Mode Timing ............................... 35

13.5 SDIO High Speed Mode Timing........................ 36

13.6 USB Parameters ............................................... 37

14. Thermal Information .................................................39

14.1 Junction Temperature Estimation and

PSI_JTVersus Theta_{JC..................................................}39

15. Package Information ................................................40

16. Ordering Information ................................................41

Document History ..........................................................42

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CYW43143

1. Introduction

The Cypress CYW43143 single-chip device provides the highest level of integration for wireless systems with integrated IEEE

802.11b/g/n (MAC/PHY/radio). It provides a small form-factor solution with minimal external components to drive down the cost for

mass volumes and allows for wireless media client flexibility in size, form, and function.

Figure 1. CYW43143 System Diagram Showing Two Antennas and a Single Stream

CYW43143

IEEE 802.11n

2.4 GHz Radio

Transceiver

with integrated

PA

IEEE 802.11n

2.4 GHz Radio

Transceiver

with integrated

PA

RF

IEEE

802.11n

MAC/PHY

IEEE

802.11n

MAC/PHY

TR and Rx

Diversity

Switches

TR and Rx

Diversity

Switches

Host

I/F

Host

I/F

Employing a native 32-bit bus with a Direct Memory Access (DMA) architecture, the CYW43143 offers significant performance

improvements in both transfer rates and CPU utilization. Flexible support for a variety of system bus interfaces is provided, including

USB and SDIO devices.

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CYW43143

Figure 2 shows a block diagram of the device.

Figure 2. CYW43143 Functional Block Diagram

CYW43143

Host Interface

Clock and Reset

USB

USB20d

DFLL

PLL

XTAL

(PL368/9 regs. ifc)

(inside USB)

SDIOd

I²S

AXI2APB 1

PLL

(inside WL radio)

POR

ClkRst

EXTPOR_L

ARM

CORTEX‐M3

ChipCommon

WDog timer

OTP

Power Topology

AXI

backplane

PL301

BUCK

Digital

I/Os

(inside PMU)

(2 Kbits)

DevID

RAM

ROM

CLDO

(448 KB)

(256 KB)

GPIO

(inside PMU)

SECI

CLDO

SOCSRAM

(BT Coex)

(inside USB)

mini PMU

SFLASH

(inside WL radio)

GSIO

(SPI2C)

WLAN 802.11bgn (1 × 1)

JTAG_SEL

UART

JTAG

iTR

IEEE

802.11n

2.4 GHz

Radio

iPA

IEEE

802.11n

MAC

IEEE

802.11n

PHY

UART

RF Ifc

PMU Ctrl

iRD

SAXI

RF_SWCTRL

Digital

I/Os

AXI2APB 0

PMU

pinmux

(Core register ifc)

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CYW43143

2. Power Management and Resets

2.1 Power Management

The CYW43143 includes an internal Power Management Unit (PMU). The PMU takes care of powering up the chip, and also enables

and disables clocks based on clock requests sent from CYW43143 internal blocks.

2.2 Power Topology

The CYW43143 contains a high-efficiency power topology to convert input supply voltages to the supply voltages required by the

device’s internal blocks. A CBUCK switching regulator is used to convert the input supply to 1.35V. Internal LDOs perform a low-noise

conversion from 1.35V to 1.2V. As shown in Figure 3 on page 6, the CYW43143 supports two power supply configurations:

■ A 3.3V power supply, connected to SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3.

■ A 5V power supply connected to SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3 connected to 3.3V. The latter can

be obtained through a DC-DC conversion as shown in Figure 3 on page 6.

The default VDDIO supply of the BCM43143 is 3.3V. In SDIO mode, the BCM43143 supports an SDIO interface specific voltage range

of 1.8V to 3.3V. Refer to pin 46 description in Table 4 on page 18. All VDDIO pins other than pin 46 remain at 3.3V as described in

Table 4 on page 18.

Figure 3. Power Topology with the VDD33 (3.3V) Main Supply

VDDIO

GPIO

CYW43143

USB2.0

3.3V

LDO

USB_AVDD3P3

50 mA

2.5V

For 5 volts power

supplies only

WRF_PAD_VDD3P3

5V

WRF_PA_VDD3P3

VBUS

D+

PA

3.3V

BG

Radio

D-

1.35V

GND

3.3V

5V

mini

PMU

XTAL_VDD1P2

WRF_SYN_VDD1P2

LNLDO_VOUT1P2

3.3V - 5V

SR_VDDVBAT5V

Buck

500mA

1.2V

2.2 µH

1.35V

1 µF

SR_VLX

4.7 µF

PMU

LNDO_VDD1P5

1 µF

1.35V

Digital

Core

CLDO

150 mA

1.2V

LDO_VDD1P5

2.2 µF

2.3 Reset and Low-Power Off Mode

Full-chip reset is achieved by switching off the 3.3V VDDIO voltage to pins 1, 25, 37, and 53. This puts the chip in reset and low-power

off mode; in this mode the internal CBUCK switcher is shut down, bringing the total typical current consumption down to less than 100

µA. The device must be kept in reset/low-power off mode for at least 25 ms.

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CYW43143

3. WLAN Global Functions

3.1 GPIO Interface

2

There are 19 General-Purpose I/O (GPIO) pins provided on the CYW43143. GPIOs 0–18 are multiplexed with the JTAG, SDIO, I S,

SFlash, and Serial Enhanced Coexistence Interface (SECI) functions. These pins can be used to interface to various external devices.

Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via

the GPIO control register. A programmable internal pull-up/pull-down resistor is included on each GPIO. If a GPIO output enable is

not asserted, and the corresponding GPIO signal is not being driven externally, the GPIO state is determined by its programmable

resistor.

3.2 OTP

The CYW43143 has 2 Kbits of on-chip One-Time Programmable (OTP) memory that can be used for non-volatile storage of WLAN

information such as a MAC address and other hardware-specific board and interface configuration parameters.

3.3 JTAG Interface

The CYW43143 supports the IEEE 1149.1 JTAG boundary-scan standard for testing a packaged device on a manufactured board.

The JTAG interface is enabled by driving the JTAG_SEL pin high.

3.4 Crystal Oscillator

Table 2 lists the requirements for the crystal oscillator.

Table 2. Crystal Oscillator Requirements

Parameter

Value

Frequency

Mode

20 MHz

AT cut, fundamental

16 pF

Load capacitance

ESR

50Ω maximum

±10 ppm at 25°C

±10 ppm at 0°C to +85°C

Frequency stability

Aging

±3 ppm/year maximum the first year, ±1 ppm thereafter

Drive level

Q-factor

300 µW maximum

40,000 minimum

< 5 pF

Shunt capacitance

Figure 4 shows the recommended oscillator configuration.

Figure 4. Recommended Oscillator Configuration

XTAL_OP_IN

27 pF

Crystal

20 MHz 10 ppm

XTAL_ON_OUT

27 pF

220

Note: Refer to reference schematics for design-specific details.

Note: The component values referenced in Figure 4 are only recommended values and the correct values will have to be

characterized on a per board basis. Please see the reference board schematic for the correct characterized values.

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CYW43143

4. WLAN USB 2.0 Host Interface

The CYW43143 USB interface can be set to operate as a USB 2.0 port. Features include the following:

■ A USB 2.0 protocol engine that supports the following:

❐ A Parallel Interface Engine (PIE) between packet buffers and USB transceiver

❐ Up to nine endpoints, including Configurable Control Endpoint 0

■ Separate endpoint packet buffers with a 512-byte FIFO buffer each

■ Host-to-device communication for bulk, control, and interrupt transfers

■ Configuration and status registers

Figure 5 shows the blocks in the device core.

Figure 5. WLAN USB 2.0 Host Interface Block Diagram

32‐Bit On‐Chip Communication System

DMA Engines

RX FIFO

TX FIFOs

Endpoint Management Unit

USB 2.0 Protocol Engine

USB 2.0 PHY

D+

D‐

The USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and device. It is primarily responsible

for data transmission and recovery. On the transmit side, data is encoded, along with a clock, using the NRZI scheme with bit stuffing

to ensure that the receiver detects a transition in the data stream. A SYNC field that precedes each packet enables the receiver to

synchronize the data and clock recovery circuits. On the receive side, the serial data is deserialized, unstuffed, and checked for errors.

The recovered data and clock are then shifted to the clock domain that is compatible with the internal bus logic.

The endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces between the packet buffers

and the USB transceiver. It handles packet identification (PID), USB packets, and transactions.

The endpoint logic contains nine uniquely addressable endpoints. These endpoints are the source or sink of communication flow

between the host and the device. Endpoint zero is used as a default control port for both the input and output directions. The USB

system software uses this default control method to initialize and configure the device information and allows USB status and control

access. Endpoint zero is always accessible after a device is attached, powered, and reset.

Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT endpoints. Both TX and RX

data transfers support a DMA burst of 4, which guarantees low latency and maximum throughput performance. The RX FIFO can

never overflow by design. The maximum USB packet size cannot be more than 512 bytes.

4.1 Link Power Management (LPM) Support

The USB 2.0 host interface supports a power management feature called Link Power Management (LPM) which is similar to the

existing suspend/resume, but has transitional latencies of tens of microseconds between power states (instead of three to greater

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CYW43143

than 20 millisecond latencies of the USB 2.0 suspend/resume). LPM simply adds a new feature and bus state that co-exists with the

USB 2.0 defined suspend/resume.

2

4.2 I S Interface

2

The I S interface for audio supports slave mode transmit 2.1 or 5.1 channel operation. The I S signals are:

2

■ I S bit clock: I2S_BITCLK

2

■ I S Word Select: I2S_WS

2

■ I S Data Out: I2S_SDOUT

I2S_BITCLK and I2S_WS are inputs, while I2S_SDOUT is an output. Channel word lengths of 16 bits, 20 bits, 24 bits, and 32 bits are

2

supported, and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I S bus, per the I S

specification. The MSB of each data word is transmitted one bit clock cycle after the I2S_WS transition, synchronous with the falling

edge of bit clock. Left-channel data is transmitted when I2S_WS is low, and right-channel data is transmitted when I2S_WS is high.

An embedded 128 x 32 bits single port SRAM for data processing enhances the performance of the interface.

2

The bit depth of I S is 16, 20, 24, and 32.

Variable sampling rates are also supported:

■ 8k, 12k, 16k, 24k, 32k, 48k, 96k with a 12.288 MHz master clock used by the external master receiver and/or controller

■ 22.05k, 44.1k, 88.2k with a 11.2896 MHz master clock used by the external master receiver and/or controller

■ 96k with a 24.567 MHz master clock used by the external master receiver and/or controller

2

The BCM43143 needs an external clock source input on the slave clock pin for the I S interface. The slave clock frequency is

2

dependent upon the audio sample rate and the external I S codec.

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CYW43143

5. SDIO Interface

The SDIO interface is enabled by a strapping option (see Table 5 on page 21 for details). The CYW43143 supports all of the SDIO

version 2.0 modes:

■ 1-bit SDIO-SPI mode (25 Mbps)

■ 1-bit SDIO-SD mode (25 Mbps)

■ 4-bit SDIO-SD default speed mode (100 Mbps)

■ 4-bit SDIO-SD high speed mode (200 Mbps).

The SDIO interface supports the full clock range from 0 to 50 MHz. The chip has the ability to stop the SDIO clock between transactions

to reduce power consumption. As an option, the GPIO_4 or the GPIO_16 pin can be mapped to provide an SDIO Interrupt signal.

This out-of-band interrupt is hardware generated and is always valid (unlike the SDIO in-band interrupt, which is signalled only when

data is not driven on SDIO lines). The ability to force control of the gated clocks from within the WLAN chip is also provided. Three

functions are supported:

■ Function 0 standard SDIO function. Maximum BlockSize/ByteCount = 32 bytes.

■ Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. Maximum BlockSize/ ByteCount =

64 bytes.

■ Function 2 WLAN function for efficient WLAN packet transfer through DMA. Maximum BlockSize/ByteCount = 512 bytes.

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CYW43143

6. Wireless LAN MAC and PHY

6.1 IEEE 802.11n MAC Description

The IEEE 802.11n MAC features include:

■ Enhanced MAC for supporting 802.11n features

■ Programmable Access Point (AP) or Station (STA) functionality

■ Programmable mode selection as Independent Basic Service Set (IBSS) or infrastructure

■ Aggregated MAC Protocol Data Unit (MPDU) support for High Throughput (HT)

■ Passive scanning

■ Network Allocation Vector (NAV), Interframe Space (IFS), and Timing Synchronization Function (TSF) functionality

■ RTS/CTS procedure support

■ Transmission of response frames (ACK/CTS)

■ Address filtering of receive frames as specified by IBSS rules

■ Multirate support

■ Programmable Target Beacon Transmission Time (TBTT), beacon transmission/cancellation, and Announcement Traffic Indication

Message (ATIM) window

■ Coordination Function (CF) conformance: Setting a NAV for neighborhood Point Coordination Function (PCF) operation

■ Security through a variety of encryption schemes including WEP, TKIP, AES, WPA, WAP2, and IEEE 802.1X

■ Power management

■ Statistics counters for MIB support

The MAC core supports the transmission and reception of packet sequences, together with related timing, without any packet-by-

packet driver interaction. Time-critical tasks requiring response times of only a few milliseconds are handled in the MAC core. This

achieves the required medium timing while minimizing driver complexity. Also, the MAC driver processes incoming packets that have

been buffered in the MAC core in bursts, enabling high bandwidth performance.

The MAC driver interacts with the MAC core to prepare transmit packet queues and to analyze and forward received packets to upper

software layers. The internal blocks of the MAC core are connected to a Programmable State Machine (PSM) through the host

interface that connects to the internal bus (see Figure 6 on page 11).

Figure 6. Enhanced MAC Block Diagram

Host Interface (Host Registers)

Six TX FIFOs

TX Status FIFO

RX FIFO

Code Memory

Templates

TX Engine

Programmable

State Machine

(PSM)

Power

Management

Wireless Security Engine

Timing and

Control

RX Engine

Data Memory

PHY Interface

The host interface consists of registers for controlling and monitoring the status of the MAC core and interfacing with the TX/RX FIFOs.

For transmission, 32 KB of FIFO buffering is available that can be dynamically allocated to six transmit queues plus template space

for beacons, ACKs, and probe responses. Whenever the host has a frame to transmit, the host queues the frame into one of the

transmit FIFOs with a TX descriptor containing TX control information. The PSM schedules the transmission on the medium depending

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CYW43143

on the frame type, transmission rules in the IEEE 802.11™ protocol, and the current medium occupancy scenario. After the trans-

mission completes, a TX status is returned to the host, informing the host of the transmission.

The MAC contains a 10 KB RX FIFO. Received frames are sent to the host along with RX descriptors that contain additional frame

reception information.

The power management block maintains power management state information of the core (and of the associated STAs in the case

of an AP) to help with dynamic frame transmission decisions by the core.

The wireless security engine performs the required encryption/decryption on the TX/RX frames. This block supports separate transmit

and receive keys with four shared keys and 50 link-specific keys. The link-specific keys are used to establish a secure link between

any two network nodes. The wireless security engine supports the following encryption schemes that can be selected on a per-

destination basis:

■ None: The wireless security engine acts as a pass-through

■ WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std. 802.11-2007

■ WEP128: 104-bit secure key and 24-bit IV

■ TKIP: IEEE Std. 802.11-2007

■ AES: IEEE Std. 802.11-2007

The transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the encryption engine and the

addition of a CRC-32 Frame Check Sequence (FCS) as required by IEEE 802.11-2007. Similarly, the receive engine is responsible

for byte flow from the PHY interface to the RX FIFO through the decryption engine and for detection of errors in the RX frame.

The timing block performs the TSF, NAV, and IFS functionality as described in IEEE Std. 802.11-2007.

The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for both transmission and

reception. The PSM also maintains the statistics counters required for MIB support.

6.2 IEEE 802.11n PHY Description

The PHY supports:

■ Programmable data rates from MCS 0–7 in 20 MHz and 40 MHz channels, as specified in 802.11n.

■ Short Guard Interval (SGI) and optional reception of two space-time block encoded streams.

■ All scrambling, encoding, forward error correction, and modulation in the transmit direction, and inverse operations in the receive

direction.

■ Advanced digital signal processing technology for best-in-class receive sensitivity.

■ Both mixed-mode and optional greenfield preamble of 802.11n.

■ Both long and optional short IEEE 802.11b preambles.

■ Closed-Loop transmit power control.

■ Per-packet receive antenna diversity.

■ Automatic Gain Control (AGC).

■ Available per-packet channel quality and signal strength measurements.

The CYW43143 PHY provides baseband processing at all mandatory 802.11n data rates up to 150 Mbps, and the legacy rates

specified in IEEE 802.11b/g, including 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 Mbps. This core acts as an intermediary between

the MAC and the 2.4 GHz radio, converting back and forth between packets and baseband waveforms.

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CYW43143

Figure 7. PHY Block Diagram

CCK/DSSS

Demodulate

Filters and

Radio Comp

Frequency and

Timing Synch

OFDM

Demodulate

Viterbi

Decoder

Descramble

and Deframe

Carrier Sense,

AGC, and Rx

FSM

Buffers

Radio

Control

Block

MAC

Interface

FFT/IFFT

AFE

and

Radio

Modulation

and Coding

Tx FSM

Common Logic

Block

Frame and

Scramble

Filters and

Radio Comp

Modulate and

Spread

PA Comp

COEX

6.3 Single-Band Radio Transceiver

The CYW43143 has a 2.4 GHz radio transceiver that ensures low power consumption and robust communication in 20 MHz and

40 MHz channel bandwidths as specified in IEEE 802.11n.

6.3.1 Receiver Path

The CYW43143 has a wide dynamic range, direct conversion receiver. It employs high-order, on-chip channel filtering to ensure

reliable operation in the noisy 2.4 GHz ISM band. The excellent noise figure of the receiver makes an external LNA unnecessary.

6.3.2 Transmitter Path

Baseband data is modulated and upconverted to the 2.4 GHz ISM band. Linear on-chip power amplifiers are included, which are

capable of delivering a nominal output power exceeding +15 dBm while meeting the IEEE 802.11n specification. The TX gain has 128

steps of 0.25 dB per step.

6.3.3 Calibration

The CYW43143 features dynamic on-chip calibration, eliminating process variation across components. This enables the device to

be used in high-volume applications because calibration routines are not required during manufacturing. These calibration routines

are performed periodically in the course of normal radio operation.

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CYW43143

7. Pin Assignments

7.1 56-Pin QFN Assignments

The 56-pin QFN package pin assignments are shown in Figure 8.

Figure 8. CYW43143 56-Pin QFN Package

56 55 54 53 52 51 50 49 48 47 46 45 44 43

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

VDDIO

UART_RX

USB_RREF

USB_MONPLL

USB_AVDD3P3

3

UART_TX

4

WRF_PAD_VDD3P3

NC

USB_DM

USB_DP

5

6

WRF_PA_VDD3P3

WRF_OUT_IN1

NC

VDDIO

7

SFLASH_SO|GSIO_SDO

SFLASH_CLK|GSIO_SCLK

SFLASH_SI|GSIO_SDI

VDDC

BCM43143

7 X 7 QFN

8

9

WRF_RFIN2

10

11

12

13

14

WRF_GPIOOUT

LNLDO_VDD1P5

LDO_VDD1P5

VOUT_CLDO

SR_VDDBAT5V

SR_VLX

15 16 17 18 19 20 21 22 23 24 25 26 27 28

7.1.1 56-Pin QFN Signals

Pin Assignments by Pin Number

Table 3. Pin Assignments by Pin Number

Signal Name

1

2

3

4

5

6

VDDIO

UART_RX

UART_TX

WRF_PAD_VDD3P3

GND

WRF_PA_VDD3P3

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Signal Name

7

WRF_OUT_IN1

GND

8

9

WRF_RFIN2

WRF_GPIOOUT

LNLDO_VDD1P5

LNLDO_VOUT1P2

WRF_SYN_VDD1P2

XTAL_VDD1P2

XTAL_OP_IN

XTAL_ON_OUT

JTAG_SEL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

VDDC

GPIO0

GPIO1

GPIO2

VDDIO

GPIO3

GPIO4

GPIO5

SR_VLX

SR_VDDBAT5V

VOUT_CLDO

LDO_VDD1P5

VDDC

SFLASH_SI|GSIO_SDI

SFLASH_CLK|GSIO_SCLK

SFLASH_SO|GSIO_SDO

VDDIO

USB_DP

USB_DM

USB_AVDD3P3

USB_MONPLL

USB_RREF

VDDC

SDIO_DATA3

SDIO_DATA2

VDDIO

SDIO_CMD

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Signal Name

48

49

50

51

52

53

54

55

56

SDIO_CLK

SDIO_DATA1

SDIO_DATA0

SFLASH_CSN

GSIO_CSN

VDDIO

GPIO17

GPIO18

VDDC

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Pin Assignments by Pin Name

Table 4. Pin Assignments by Signal Name

Signal Name

VDDC

43

56

1

GPIO0

22

VDDC

GPIO1

23

24

26

27

28

54

55

52

20

32

11

12

13

14

15

5

VDDIO

GPIO2

VDDIO

25

37

46

53

31

10

7

GPIO3

VDDIO

GPIO4

VDDIO

GPIO5

VDDIO

GPIO17

VOUT_CLDO

WRF_GPIOOUT

WRF_OUT_IN1

GPIO18

GSIO_CSN

JTAG_SEL

WRF_PA_VDD3P3

WRF_PAD_VDD3P3

WRF_RFIN2

6

LDO_VDD1P5

LNLDO_VDD1P5

LNLDO_VOUT1P2

GND

4

9

WRF_SYN_VDD1P2

XTAL_ON_OUT

XTAL_OP_IN

16

19

18

17

XTAL_VDD1P2

GND

8

SDIO_CLK

48

47

50

49

45

44

35

51

34

36

30

29

2

SDIO_CMD

SDIO_DATA0

SDIO_DATA1

SDIO_DATA2

SDIO_DATA3

SFLASH_CLK|GSIO_SCLK

SFLASH_CSN

SFLASH_SI|GSIO_SDI

SFLASH_SO|GSIO_SDO

SR_VDDBAT5V

SR_VLX

UART_RX

UART_TX

3

USB_AVDD3P3

USB_DM

40

39

38

41

42

21

33

USB_DP

USB_MONPLL

USB_RREF

VDDC

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8. Signal and Pin Descriptions

8.1 Package Signal Descriptions

The signal name, type, and description of each pin in the CYW43143 56-pin QFN package is listed in Table 4. The symbols shown in

the Type column indicate pin directions (I/O = bidirectional, I = input, O = output, and OD = open drain output) and the internal pull-

up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Resistor strapping

options are defined in Table 5 on page 21.

Table 4. CYW43143 Signal Descriptions

Signal

Type

I/O

Description

SDIO Bus Interface

48

47

SDIO_CLK

SDIO clock

When not used as SDIO this is a general purpose GPIO pin (GPIO12) or an

I S Audio Interface signal (I2S_WS)

2

SDIO_CMD

I/O

SDIO bus command line

When not used as SDIO this is a general purpose GPIO pin (GPIO11) or an

2

I S Audio Interface signal (I2S_BITCLK)

50

49

SDIO_DATA0

SDIO_DATA1

I/O

SDIO data line 0

When not used as SDIO this is a general purpose GPIO pin (GPIO14)

SDIO data line 1

When not used as SDIO this is a general purpose GPIO pin (GPIO13) or an

2

I S Audio Interface signal (I2S_SDOUT)

45

44

SDIO_DATA2

SDIO_DATA3

I/O

SDIO data line 2

When not used as SDIO this is a general purpose GPIO pin (GPIO10)

SDIO data line 3

When not used as SDIO this is a general purpose GPIO pin (GPIO9)

USB Interface

39

38

41

42

USB_DM

I/O

–

USB data negative

USB_DP

USB data positive

USB_MONPLL

USB_RREF

USB reserved pin for Diagnostic purposes only

–

USB bandgap reference resistor/capacitor, tie this pin in parallel through a 100

pF capacitor and a 4 kΩ resistor to ground

WLAN RF Signal Interface

2.4 GHz RF output, 2.4 GHz RF input 1

2.4 GHz RF input 2

7

WRF_OUT_IN1

WRF_RFIN2

I/O

I

9

10

WRF_GPIOOUT

O

WLAN reference output.

Connect to ground through a 15 kΩ, 1% resistor.

I²S Audio Interface

2

47

48

49

I2S_BITCLK

I2S_WS

I/O

I S serial bit clock, only available when no SDIO I/F

2

I S word select, only available when no SDIO I/F

2

I2S_SDOUT

I S serial data out, only available when no SDIO I/F

Serial Flash Interface and SPI/BSC Interface

51

34

SFLASH_CSN

I/O

Serial flash chip select.

When not used as SFLASH, this is a general purpose GPIO pin (GPIO15)

SFLASH_SI GSIO_SDI

I/O

This pin is muxed with:

•

Serial flash data in

SPI/BSC data in

When not used as SFLASH or GSIO this is a general purpose GPIO pin

(GPIO6)

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Table 4. CYW43143 Signal Descriptions (Cont.)

Signal

Type

I/O

Description

36

SFLASH_SO GSIO_SDO

This pin is muxed with:

•

Serial flash data out

SPI/BSC data out

When not used as SFLASH or GSIO this is a general purpose GPIO pin

(GPIO8)

35

SFLASH_CLK GSIO_SCLK I/O

This pin is muxed with:

•

Serial flash clock

SPI/BSC clock

When not used as SFLASH or GSIO this is a general purpose GPIO pin

(GPIO7)

52

22

GSIO_CSN

I/O

SPI/BSC chip select.

When not used as GSIO this is a general purpose GPIO pin (GPIO16).

GPIO Pins

GPIO0

TDI

BTCX_RF_ACTIVE

SECI_IN0

This pin is muxed with:

•

GPIO0, a general purpose I/O pin

JTAG test data in

Legacy BT coexistence RF Active

SECI in0

23

24

26

GPIO1

TDO

BTCX_TX_CONF

SECI_OUT

I/O

This pin is muxed with:

•

GPIO1, a general purpose I/O pin

JTAG test data out

Legacy BT coexistence TX Conf

SECI out

GPIO2

TCK

BTCX_STATUS

SECI_AUX0

This pin is muxed with:

•

GPIO2, a general purpose I/O pin

JTAG test clock

Legacy BT coexistence Status

SECI aux0

GPIO3

TRST-L

BTCX_PRISEL

SECI_IN1

This pin is muxed with:

•

GPIO3, a general purpose I/O pin

JTAG test reset low

Legacy BT coexistence Priority Select

SECI in1

27

28

GPIO4

TMS

BTCX_FREQ

This pin is muxed with:

•

GPIO4, a general purpose I/O pin

JTAG test mode select

Legacy BT coexistence FREQ

GPIO5

I/O (PU) This pin is muxed with:

EXTPOR_L

•

GPIO5, a general purpose I/O pin

External power-on reset low, when JTAG_SEL high

54

55

GPIO17

GPIO18

I/O (PD) General purpose I/O pin

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Table 4. CYW43143 Signal Descriptions (Cont.)

Pin Signal Type

Description

UART Interface

2

3

UART_RX

UART_TX

I/O (PD) UART receive data (SW debug)

I/O (PU) UART transmit data (SW debug)

Crystal Oscillator

19

XTAL_ON_OUT

O

XTAL oscillator output.

Connect a 20 MHz, 10 ppm crystal between the XTAL_ON_OUT and

XTAL_OP_IN pins

18

20

XTAL_OP_IN

JTAG_SEL

I

XTAL oscillator input

Test Pins

I (PD)

JTAG select

Strap Pins

2

UART_RX

UART_TX

SFLASH_SI

GPIO17

I/O (PD) Strap RemapToROM[1]

I/O (PU) Strap RemapToROM[0]

I/O (PD) Strap SDIOHighDrive

I/O (PD) Strap SDIOEnabled

I/O (PD) Strap SDIOIso

3

34

54

55

GPIO18

Integrated Voltage Regulators

11, 12, 13, LNLDO_VDD1P5

14

PWR

LNLDO 1.5V input

15

30

29

31

32

LNLDO_VOUT1P2

SR_VDDBAT5V

SR_VLX

PWR

LNLDO 1.2V output

VBAT power input

CBUCK switching regulator output

Output of core LDO

VOUT_CLDO

LDO_VDD1P5

Input of core LDO

WLAN Power Supplies

USB 3.3V input

40

16

6

USB_AVDD3P3

PWR

WRF_SYN_VDD1P2

WRF_PA_VDD3P3

WRF_PAD_VDD3P3

XTAL_VDD1P2

RF synthesizer VDD 1.2V input

WLAN PA 3.3V supply

WLAN PA driver 3.3V supply

XTAL oscillator 1.2V supply

4

17

Miscellaneous Power Supplies and Ground

21, 33, 43, VDDC

56

PWR

Core supply for WLAN

1, 25, 37, VDDIO

53

PWR

I/O supply for pads (3.3V)

46

H

VDDIO

PWR

GND

I/O supply for SDIO pads (1.8V to 3.3V). Can only be 3.3V when USB is used.

GND_SLUG

GND

Ground

5, 8

8.2 Strapping Options

The pins listed in Table 5 are sampled at Power-On Reset (POR) to determine the various operating modes. Sampling occurs within

a few milliseconds following internal POR or deassertion of external POR. After POR, each pin assumes the function specified in the

signal descriptions table. Each pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change

1

the mode, connect an external PU resistor to VDDIO or a PD resistor to GND (use 10 kΩ or less) .

1. CYW43143 reference board schematics can be obtained through your CypressCypress representative.

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Table 5. Strapping Options

Signal Name

Mode

Default

Description

[UART_RX,

UART_TX]

RemapToROM[1:0]

[PD,PU]

00 = Boot from SRAM, ARMCM3 in reset, no SFLASH connected

01 = Boot from ROM, no SFLASH connected (default)

10 = Boot from SFLASH

11 = Invalid

2

GPIO17

SDIOEnabled

SDIOIso

PD

0 = USB Enabled, SDIO pins can be GPIO or I S (default)

1 = SDIO Enabled

GPIO18

0 = SDIO pads are not in Isolation mode (default)

1 = Keep SDIO pads in Isolation mode

SFLASH_SI

SDIOHighDrive

0 = SDIO pins drive strength set by SDIOd core or PMU Chip Control (=

default)

1 = SDIO pins drive strength set by SDIOd core to either 12 mA or 16 mA

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9. Electrical Characteristics

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

9.1 Absolute Maximum Ratings

Caution! These specifications indicate levels where permanent damage to the device can occur. Functional operation

is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can

adversely affect the long-term reliability of the device.

Table 6. Absolute Maximum Ratings

Rating

Symbol

SR_VDDBAT5V

Minimum

–0.5

Maximum

5.5

Unit

DC supply for CBUCK switching regulator

DC supply voltage for the WL PA/PA driver

V

WRF_PA_VDD3P3,

WRF_PAD_VDD3P3

–0.5

3.8

V

DC supply voltage for I/O

VDDIO

VDDC

–0.5

3.8

V

DC supply voltage for the CYW43143 core

DC supply voltage for CYW43143 RF blocks

1.32

WRF_SYN_VDD1P2,

XTAL_VDD1P2

DC input supply voltage for CLDO and LNLDO

LDO_VDD1P5, LNLDO_-

VDD1P5

–0.5

2.1

V

Maximum junction temperature

Operating humidity

T

–

T

–

125

85

°C

%

°C

%

V

J_MAX

–

a

Ambient operating temperature

Storage temperature

–

65

–40

–

125

60

STG

Storage humidity

ESD protection (HBM)

V

–

2000

ESD

a. On a 1s1P JEDEC board, not exceeding T_{J_MAX}, see Section 14.: “Thermal Information,” on page 39.

9.2 Recommended Operating Conditions and DC Characteristics

Table 7. Guaranteed Operating Conditions and DC Characteristics

Value

Element

Parameter

Unit

Minimum

Typical

Maximum

DC supply for CBUCK switching regulator

DC supply voltage for WL PA/PA driver

SR_VDDBAT5V

2.3

3.6

5.25

3.63

V

WRF_PA_VDD3P3,

WRF_PAD_VDD3P3

2.97

3.3

DC supply voltage for core

VDDC

1.14

1.2

1.26

V

DC supply voltage for RF blocks in chip

VDDRF

SDIO Interface I/O Pins^a

Input high voltage

VIH

0.625 × VDDIO

–

V

Input low voltage

VIL

–

0.25 × VDDIO

–

Output high voltage @ 2 mA

Output low voltage @ 2 mA

VOH

VOL

0.75 × VDDIO

–

0.125 × VDDIO

Other Digital I/O Pins

Input low voltage

VIL

–

0.8

V

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Table 7. Guaranteed Operating Conditions and DC Characteristics (Cont.)

Value

Element

Parameter

Unit

Minimum

Typical

Maximum

Input high voltage

VIH

2.0

–

V

Output low voltage @ 2 mA

Output high voltage @ 2 mA

VOL

VOH

0.4

–

VDDIO – 0.4V

RF Switch Control I/O Pins

Input low voltage

VIL

–

0.8

–

V

pf

Input high voltage

VIH

2.0

Output low voltage @ 2 mA

Output high voltage @ 2 mA

Input capacitance

VOL

VOH

Cin

–

0.4

–

VDDIO – 0.4V

–

5

a. VDDIO voltage tolerance is ±10%; for SDIO 1.8V levels (VDDIO at pin 46 = 1.8V ±10%), the maximum SDIO clock frequency should be limited

to 25 MHz in high-speed mode only.

9.3 WLAN Current Consumption

The WLAN current consumption measurements are shown in Table 8 through Table 9 on page 24.

Table 8. WLAN Current Consumption in SDIO Mode using SR_VDDBAT5V^a

VDDIO SR_VDDBAT5V

mA

WRF_PA_VDD3P3 WRF_PAD_VDD3P3 USB_AVDD3P3

I_Total P_Total

mW

Host Interface SDIO

OFF (Low power off

mode: VDDIO switched

off)

0

0.07

0

0.07

0.2

b

Sleep

1

2

3

0

1

0

< 5

< 6

42

< 17

< 20

139

c

Power save

RX (Listen), 2.4 GHz HT

40

d

20

RX (Active), 2.4 GHz HT

20

2

1

2

65

56

58

0

1

0

68

224

1373

1265

e,f

TX CCK (20 dBm @ Chip

329

295

30

416

385

g

port, 2.4 GHz HT 20)

TX OFDM, 54 Mbps (–20

dBm @ Chip port,

g

2.4 GHz HT 20)

TX MCS7 (18 dBm @

Chip port, 2.4 GHz HT20)

2

72

78

249

272

24

25

0

347

377

1145

1244

g

TX MCS7 (18 dBm @

Chip port, 2.4 GHz HT40)

g

a. Typical numbers, measured at 3.3V, 25°C.

b. Inter-beacon sleep.

c. Beacon interval = 102.4 ms, DTIM = 3, Beacon duration = 1 ms @ 1 Mbps.

Integrated sleep + wake up + Beacon RX current over 3 DTIM intervals.

d. Carrier sense (CCA) when no carrier present.

e. Carrier sense (CS) detect/packet RX.

f. Applicable to all supported rates.

g. Duty cycle is 100%.

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Table 9. WLAN Current Consumption in USB mode using VDD33^a

VDDIO SR_VDDBAT5V

mA

WRF_PA_VDD3P3 WRF_PAD_VDD3P3 USB_AVDD3P3

I_Total

P_Total

mW

Host Interface USB

OFF (Low power off

mode: VDDIO switched

off)

0

0.07

0

0.07

0.2

b

Sleep

0.4

2

3

0

1

5.6

22

< 9

< 10

68

< 30

< 33

226

c

Power save

RX (Listen), 2.4 GHz HT

45

d

20

RX (Active), 2.4 GHz HT

20

0.4

0.5

0.4

70

55

59

0

1

23

21

94

312

1407

1239

e,f

TX CCK (20 dBm @ Chip

320

265

30

427

376

g

port, 2.4 GHz HT 20)

TX OFDM, 54 Mbps (–20

dBm @ Chip port,

g

2.4 GHz HT 20)

TX MCS7 (18 dBm @

Chip port, 2.4 GHz HT20)

0.6

1.6

74

80

248

272

24

25

21

368

400

1213

1319

g

TX MCS7 (18 dBm @

Chip port, 2.4 GHz HT40)

g

a. Typical numbers, measured at 3.3V, 25°C.

b. Inter-beacon sleep.

c. Beacon interval = 102.4 ms, DTIM = 3, Beacon duration = 1 ms @ 1 Mbps.

Integrated sleep + wake up + Beacon RX current over 3 DTIM intervals.

d. Carrier sense (CCA) when no carrier present.

e. Carrier sense (CS) detect/packet RX.

f. Applicable to all supported rates.

g. Duty cycle is 100%.

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10. Regulator Electrical Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Functional operation is not guaranteed outside of the specification limits provided in this section.

10.1 Core Buck Switching Regulator

Table 10. Core Buck Switching Regulator (CBUCK) Specifications

Specification

Input supply voltage (DC)

Input supply voltage (spikes)

Notes

Min

2.3

Typ

3.6

Max

5.25

Units

DC voltage range inclusive of disturbances.

V

Up to 10 seconds cumulative duration over 7

years lifetime.

–

5.5

10 ms maximum pulse width.

PWM mode switching frequency

CCM:

2

4

6

MHz

Load > 100 mA

SR_VDDBAT5V = 3.6V

a

PWM output current

Output current limit

Output voltage range

–

500

–

mA

V

–

1390

1.35

Programmable, 30 mV steps

Default = 1.35V

1.2

1.5

PWM output voltage

DC accuracy

Includes load and line regulation.

Forced PWM mode

–4

–

4

%

PWM ripple voltage, static

PWM mode peak efficiency

PFM mode efficiency

Measure with 20 MHz bandwidth limit.

Peak Efficiency at 200 mA load

5 mA load current

–

7

20

–

mVpp

%

78

–

84

65

80

–

%

Low Power Operating mode (LPOM) 5 mA load current

efficiency

–

%

Start-up time from power down

VDDIO already ON and steady.

Time from REG_ON rising edge to CLDO

reaching 1.2V

–

850

µs

External inductor

0603 size, ±30%, 0.26 ±25% ohms

1.2

2.2

4.7

3.3

10

µH

µF

b

External output capacitor

Ceramic, X5R, 0402,

ESR <30mꢀ at 4 MHz, ±20%,

6.3V

2.53

External input capacitor

For SR_VDDBATP5V pin,

Ceramic, X5R, 0603,

ESR < 30 mꢀ at 4 MHz, ± 20%,

6.3V,

0.76

4.7

–

µF

4.7 μF

Operating junction temperature

Input supply voltage ramp-up time

–

–40

40

50

–

125

–

°C

µs

0 to 4.3V

a. 500 mA TT junction temp 110°C. Derate to 372 mA for T_j> 125°C.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and

aging.

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10.2 CLDO

Table 11. CLDO Specifications

Specification

Notes

Min

1.2

Typ

Max

1.5

Units

Input supply voltage (V )

Min = 1.2 + 0.1V = 1.3V

1.35

V

in

Dropout voltage requirement must be met under

maximum load.

a

Output current

–

150

mA

V

Output voltage (V )

Programmable in 25 mV steps.

Default = 1.2V

1.1

1.2

1.275

o

Dropout voltage

At max load

–

100

+4

mV

%

Output voltage DC accuracy

Quiescent current

Line regulation

Includes line/load regulation

No load

–4

–

10

–

µA

V

from (V + 0.1V) to 1.5V, maximum load

–

+1.1

0.02

10

%V /V

o

in

o

Load regulation

Load from 1 mA to 150 mA

Power-down

–

%V /mA

o

b

Leakage current

–

µA

dB

Power supply rejection ratio (PSRR)

@1 kHz

20

–

Vin ≥ 1.35V

C = 2.2 µF

o

PMU start-up time

SR_VDDBAT5V up and stable. Time from the VDDIO –

rising edge to the CLDO reaching 1.2V.

–

850

µs

LDO turn-on time

LDO turn-on time when rest of the chip is up

–

180

150

µs

In-rush current during turn-on

Measured when the output capacitor is fully

discharged.

mA

c

External output capacitor, C

External input capacitor

Total ESR: 30–200 mꢀ

1.67

1

–

µF

o

Only use an external input capacitor at the VDD_LDO –

pin if it is not supplied from CBUCK output.

2.2

Total ESR (trace/capacitor): 30 mꢀ–200 mꢀ

Operating temperature

Junction temperature

–40

50

125

°C

a. Output current is measured at 125°C junction temperature.

b. Leakage current is measured by 85°C junction temperature.

c. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and

aging.

10.3 LNLDO

Table 12. LNLDO Specifications

Specification

Notes

Min

1.3

Typ

1.35

Max

1.5

Units

Input supply voltage (V )

Min = 1.2V + 0.1V = 1.3V

V

in

o

Dropout voltage requirement must be met under

maximum load.

Output Current

–

100

mA

V

Output voltage (V )

Programmable in 25 mV steps.

Default = 1.2V

1.1

1.2

1.275

o

Dropout Voltage

At maximum load

includes line/load regulation

No load

–

100

+4

mV

%

Output voltage DC accuracy

Quiescent current

Line regulation

–4

–

44

–

µA

V

from (V + 0.1V) to 1.5V,

–0.3

+0.3

%V /V

in

o

maximum load

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CYW43143

Table 12. LNLDO Specifications

Specification

Load regulation

Notes

Min

Typ

0.02

Max

Units

Load from 1 mA to 300 mA

–

0.05

TBD

10

%V /mA

o

Transient undershoot

Transient overshoot

Leakage current

–

mV

µA

–

Power-down

Output noise

@30 kHz, 60 mA load C = 1 µF

60

30

nV/rt Hz

o

@100 kHz, 60 mA load C = 1 µF

o

PSRR

@ 1kHz, Input > 1.3V, C = 1 µF, V = 1.2V

20

–

dB

µs

o

PMU start-up time

LDO Turn-on Time

In-rush current during turn-on

From power-down

850

180

150

LDO turn-on time when rest of chip is up

–

µs

Measured when the output capacitor is fully

discharged.

–

mA

a

External output capacitor (C )

Total ESR (trace/capacitor): 30 mꢀ–200 mꢀ

0.74

–

1

2.2

µF

o

External input capacitor

Only use an external input capacitor at the

VDD_LDO pin if it is not supplied from CBUCK

output.

Total ESR (trace/capacitor): 30 mꢀ–200 mꢀ

Operating temperature

Junction temperature

–40

50

125

°C

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and

aging.

Document Number: 002-15045 Rev. *F

Page 27 of 44

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CYW43143

11. WLAN Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

11.1 2.4 GHz Band General RF Specifications

Table 13. 2.4 GHz Band General RF Specifications

Item

Condition

Minimum

Typical

Maximum

10

Unit

TX/RX switch time

RX/TX switch time

Including TX ramp down

Including TX ramp up

–

5

μs

5

11.2 2.4 GHz Band Receiver RF Specifications

The receiver specifications including sensitivity are shown in Table 14 and Table 15 on page 28.

Table 14. 2.4 GHz Band Receiver RF Specifications

Characteristic

Cascaded noise figure

Condition

Minimum

Typical

Maximum

Unit

–

4

–

dB

a

Maximum receive level

@ 1, 2 Mbps

@ 5.5, 11 Mbps

@ 54 Mbps

–4

dBm

dB

–10

35

Adjacent channel power rejection

b

RX = –70 dBm

•

DSSS at 11 Mbps

Return loss

Zo = 50ꢀ, across dynamic TBD

range

TBD

>90

TBD

–

dB

Maximum receiver gain

a. When using a suitable external RF switch.

–

b. Difference between interfering and desired signal (>25 MHz apart) at 8% PER for 1024-octet Physical-Layer Service Data Units (PSDUs) with

desired signal level as specified.

Table 15. 2.4 GHz Receiver Sensitivity

Rate/Modulation

Typical Receive Sensitivity^{a b}(dBm)

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps CCK

11 Mbps CCK

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

–97

–95

–91

–89

–91

–90

–88

–86

–84

–81

–78

–76

–91

–88

MCS0 (20 MHz channel)

MCS1 (20 MHz channel)

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CYW43143

Table 15. 2.4 GHz Receiver Sensitivity

Rate/Modulation

MCS2 (20 MHz channel)

MCS3 (20 MHz channel)

MCS4 (20 MHz channel)

MCS5 (20 MHz channel)

MCS6 (20 MHz channel)

MCS7 (20 MHz channel)

MCS0 (40 MHz channel)

MCS1 (40 MHz channel)

MCS2 (40 MHz channel)

MCS3 (40 MHz channel)

MCS4 (40 MHz channel)

MCS5 (40 MHz channel)

MCS6 (40 MHz channel)

MCS7 (40 MHz channel)

Typical Receive Sensitivity^{a b}(dBm)

–86

–83

–81

–77

–75

–73

–90

–86

–84

–82

–78

–74

–72

–70

a. Values are measured at the input of the CYW43143. Thus, they include insertion losses from the integrated baluns and integrated T/R

switches, but exclude losses from the external circuits. For the 1, 2, 5.5, and 11 Mbps rates, sensitivity is defined as an 8% packet error rate

(PER) for 1000-octet PSDUs. For 11g rates (6 Mbps OFDM up to 54 MBps OFDM), sensitivity is defined as a 10% packet error rate (PER) for

1000-octet PSDUs. For 11n rates (MCS0 to MCS7), sensitivity numbers are provide for 10% PER and 4000byte packets.

b. Sensitivity levels at Vcc=3.3V±6%; at Vcc=3.3 ±10%, sensitivity levels may be degraded.

11.3 2.4 GHz Band Transmitter RF Specifications

Table 16. 2.4 GHz Band Transmitter RF Specifications

Characteristic

Condition

Min.

2400

–

Typ.

–

Max.

2500

21.0

Unit

MHz

dBm

RF output frequency range

–

a

Chip output power

20 MHz

DSSS/CCK rates

1, 2, 5.5, and 11 Mbit/s

–

(EVM andACPRcompliant, Vcc=3.3V channel

b

±6% )

802.11g rates

6, 9, 12, 18, 24, and 36 Mpps

20.0

–

802.11g rate 48 Mbps

802.11g rate 56 Mbps

OFDM rates MCS0-MCS5

OFDM rate MCS6

19.0

18.0

20.0

19.0

18.0

19.5

19.0

18.0

17.0

–

OFDM rate MCS7

40 MHz

channel

OFDM rates MCS0- MCS4

OFDM rate MCS5

OFDM rate MCS6

OFDM rate MCS7

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CYW43143

Table 16. 2.4 GHz Band Transmitter RF Specifications (Cont.)

Characteristic Condition

Gain flatness

Min.

Typ.

Max.

Unit

dB

Maximum gain

–

2

Output IP3

Maximum gain

37

27

–

dBm

dBr

dBc

dBr

–

Output P1dB

–

Carrier suppression

15

–

CCK TX spectrum mask @ maximum fc –22 MHz < f < fc –11 MHz

–

–30

–50

–26

–35

–40

35%

5%

–

gain

fc +11 MHz < f< fc +22 MHz

–

f < fc –22 MHz; and f > fc +22 MHz

–

OFDM TX spectrum mask

(chip output power = 16 dBm)

f < fc –11 MHz and f > fc +11 MHz

f < fc –20 MHz and f > fc +20 MHz

f < fc –30 MHz and f > fc +30 MHz

–

TX modulation accuracy (i.e. EVM) at IEEE 802.11b mode

maximum gain

–

IEEE 802.11g mode QAM64 54 Mbps

–

Gain control step size

–

0.25

–

dB/step

dB

c

Amplitude balance

DC input

–1

–1.5

–

1

Phase balance

DC input

–

1.5

–

°

Baseband differential input voltage

TX power ramp up

Shaped pulse

90% of final power

10% of final power

0.6

–

Vpp

sec

–

2

TX power ramp down

–

2

a. Power control will back off output power by 1.5 dB ensuring EVM and ACPR limits are always met.

b. Linear output power at 3.3V ±10% supply voltage may be degraded and EVM/ACPR compliant output power may be lower than listed.

c. At a 3 MHz offset from the carrier frequency.

11.4 2.4 GHz Band Local Oscillator Specifications

Table 17. 2.4 GHz Band Local Oscillator Specifications

Characteristic

VCO frequency range

Condition

Minimum

2412

Typical

Maximum

2484

Unit

–

MHz

a

Reference input frequency range

Reference spurs

–

Various

–

MHz

–

–34

–86.5

dBc

Local oscillator phase noise, single-sided from 1–

300 kHz offset

dBc/Hz

Clock frequency tolerance

–

±20

ppm

a. Reference supported frequencies range from 12 MHz to 52 MHz.

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12. Antenna Specifications

12.1 Voltage Standing Wave Ratio

The Voltage Standing Wave Ratio (VSWR) into the antenna should be less than 2.5:1.

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13. Timing Characteristics

13.1 Power Sequence Timing

The recommended power-up sequence is to bring up the power supplies in the order of the rated voltage. This power-up sequence

minimizes the possibility of a latchup condition.

In the case of a 3.3V supply (see Figure 1), the 3.3V supplied to SR_VDDBAT5V, WRF_PA_VDD3P3, WRF_PAD_VDD3P3, USB_A-

VDD3P3, and VDDIO can ramp at the same time.

In the case of a 5V supply (see Figure 2 on page 32), the 5V first ramps on SR_VDDBAT5V, followed by bring- up of the 3.3V supply

to WRF_PA_VDD3P3, WRF_PAD_VDD3P3, USB_AVDD3P3, and VDDIO. The power-up timing parameters for both configurations

are shown in Table 18 on page 33.

Figure 1. Power-Up Sequence Timing—3V Supply

t₂

t₃

SR_VDDBAT5V

WRF_PA(D)_VDD3P3

USB_AVDD3P3

VDDIO

SR_VLX

VDDC

Internal Reset

Interface

BCM43143 TRI‐STATE

Figure 2. Power-Up Sequence Timing—5V Supply with External DC-DC Conversion

t₁

t₂

t₃

SR_VDDBAT5V

WRF_PA(D)_VDD3P3

USB_AVDD3P3

VDDIO

SR_VLX

VDDC

internal reset

interface

43143 TRI‐STATE

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Table 18. Power-Up Timing Parameters

Symbol Description

SR_VDDBAT5V to 3P3 active

Time from VDDIO rising edge to VDDC reaching 1.2V

Minimum

a

Typical

b

Maximum

Unit

µs

t

0

–

50

–

1

2

3

850

50

µs

Time from VDDC reaching 1.2V to internal reset deactivation 30

35

ms

a. In the case of the 3.3V power supply, t1 = 0 for SR_VDDBAT5V, WRF_PA_VDD3P3, and WRF_PAD_VDD3P3.

b. In the case of the 5V power supply, SR_VDD_BAT5V is directly connected to 5V, but the connection to WRF_PA_VDD3P3,

WRF_PAD_VDD3P3, and VDDIO must be made through a DC-DC converter chip to convert 5V to 3V3. Since the converter chip introduces

a delay in the ramp-up time, t1 = 50 µs (nominal). The actual value of t1 will vary slightly based on the particular DC-DC converter chip used

in the design.

13.2 Serial Flash Timing

Figure 3. Serial Flash Timing Diagram (STMicroelectronics-Compatible)

t_CS

SFLASH_CSN

t_CSH

t_CSS

t_R

t_WL

t_WH

t_F

SFLASH_CLK

t_SU

t_H

VALID IN

SFLASH_SI

SFLASH_SO

t_HO

t_V

High Impedance

VALID ON

Table 19. Serial Flash Timing

Parameter

Descriptions

Minimum

Typical

12.5

Maximum

Units

MHz

f

t

Serial flash clock frequency

–

9

49.2

–

SCK

WH

WL

Serial flash clock high time

–

ns

V/ns

ns

Serial flash clock low time

–

a

b

t , t

Clock rise and fall times

TBD

5

–

R

F

t

Chip select active setup time

Chip select deselect time

Chip select hold time

–

CSS

100

5

–

CS

CSH

SU

H

–

Data input setup time

Data input hold time

2

–

5

–

Data output hold time

Clock low to output valid

0

–

HO

V

–

8

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CYW43143

a. t and t are expressed as a slew-rate.

R

F

b. Peak-to-peak

2

13.3 I S Slave Mode Tx Timing

2

In I S slave mode, the serial clock (I2S_BITCLK) input speed can vary up to a maximum of 12.288 MHz.

2

I S Slave mode timing is illustrated in Figure 4.

Figure 4. I²S Slave Mode Timing

BITCLK

WS

SD

MSB

LSB

MSB

WORD n + 1

WORD n – 1

WORD n

Right Channel

Left Channel

T

t

HC = 0.35T

t

RC

V

t

H = 2.0V

BITCLK

SD/WS

LC = 0.35T

V

t

L = 0.8V

htr = 0

t

dtr = 0.8T

T = clock period

Ttr = minimum allowed clock period for transmitter

T > Ttr

Table 20. Timing for I²S Transmitters and Receivers

Transmitter

Receiver

Lower Limit

Min Max

Parameter

Lower Limit

Min Max

Upper Limit

Min Max

Clock period T

T

tr

Slave Mode:

Clock accepted by transmitter or

receiver:

HIGH t

0.35 T

HC

r

LOW t

LC

rise time t

0.15 T

tr

RC

Transmitter:

delay t

0.8 T

dtr

hold time t

0

htr

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Table 20. Timing for I²S Transmitters and Receivers

Transmitter

Receiver

Parameter

Lower Limit

Min Max

Upper Limit

Lower Limit

Min

Max

Min

Max

Receiver:

setup time t

0.2 T

0

sr

r

hold time t

hr

13.4 SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 5 and Table 21.

Figure 5. SDIO Bus Timing (Default Mode)

f_PP

t_WL

t_WH

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

(max)

(min)

Table 21. SDIO Bus Timing^aParameters (Default Mode)

Parameter

Symbol

Minimum

Typical

Maximum

Unit

SDIO CLK (All values are referred to minimum VIH and maximum VIL^b)

Frequency – data transfer mode

Frequency – identification mode

Clock low time

fPP

0

–

25

MHz

kHz

ns

fOD

tWL

tWH

tTLH

tTHL

0

400

–

10

–

Clock high time

–

ns

Clock rise time

10

ns

Clock low time

–

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

Input hold time

tISU

tIH

5

–

ns

Outputs: CMD, DAT (referenced to CLK)

Output delay time – data transfer mode

Output delay time – identification mode

tODLY

0

–

14

50

ns

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CYW43143

a. Timing is based on CL ≤40 pF load on CMD and data.

b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.

13.5 SDIO High Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 6 and Table 22 on page 36.

Figure 6. SDIO Bus Timing (High-Speed Mode)

f_PP

t_WL

t_WH

50% VDD

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

t_OH

Table 22. SDIO Bus Timing^aParameters (High-Speed Mode)

Parameter Symbol

SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)

Minimum

Typical

Maximum

Unit

MHz

c

Frequency – data transfer mode

Frequency – identification mode

Clock low time

fPP

0

7

–

50

fOD

tWL

tWH

tTLH

tTHL

400

–

kHz

ns

Clock high time

–

ns

Clock rise time

3

ns

Clock low time

3

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

tISU

tIH

6

2

–

ns

Input hold time

Outputs: CMD, DAT (referenced to CLK)

Output delay time – data transfer mode

Output hold time

tODLY

tOH

–

14

–

ns

pF

2.5

–

Total system capacitance (each line)

CL

40

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CYW43143

a. Timing is based on CL ≤40 pF load on CMD and data.

b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.

c. 0 - 46 MHz when running at 1.8V.

13.6 USB Parameters

Table 23. USB Parameters

Parameter

Symbol

Comments

General

Minimum

Typical

2.5

Maximum

Unit

Baud rate

Reference frequency

BPS

Fref

–

Gbaud

MHz

V

From crystal oscillator

LVPECL, AC coupled

–

1

100

–

Reference clock amplitude Vref

Receiver

Differential termination

DC impedance

ZRX-DIFF-DC

ZRX-DC

Differential termination

80

40

100

50

120

60

ꢀ

DC common-mode

impedance

Powered down termination ZRX-HIGH-IMP-DC

Power-down high

impedance

(singled ended to ground)

200k

175

–

ꢀ

Input voltage

VRX-DIFFp-p

AC coupled, differential

p-p

1200

mV

Jitter tolerance

TRX-EYE

Minimum receiver eye width 0.4

–

UI

Differential return loss

RLRX-DIFF

Differential return loss

12

11

dB

Common-mode return loss RLRX-CM

Common-mode return

loss

Unexpected electrical idle TRX-IDEL-DET-DIFF- An unexpected electrical

–

10

ms

enter detect threshold

integration time

ENTERTIME

idle must be recognized no

longer than this time to signal

an unexpected idle

condition.

Signal detect threshold

VRX-IDLE-DET-

DIFFp-p

Electrical idle detect

threshold

65

0

–

175

mV

Transmitter

Output voltage

VTX-DIFFp-p

Differential p-p, program-

mable in 16 steps

1200

Output voltage rise time

Output voltage fall time

De-emphasis (a1)

VTX-RISE

20% to 80%

0.125

0

–

UI

%

VTX-FALL

80% to 20%

–

VTX-DE-RATIO

VTX-RCV-DETECT

Programmable in 16 steps

40

600

RX detection voltage

swing

The amount of voltage

change allowed during

receiver detection.

–

mV

AC peak common-mode

voltage

VTX-CM-Acp

AC peak common-mode

ripple

–

0

–

20

mV

Absolute delta of DC

VTX-CM-DC-ACTIVE- Absolute delta of DC

100

common-mode voltage

during L0 and electrical idle

IDLE-DELTA

common-mode voltage

during L0 and electrical idle.

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CYW43143

Table 23. USB Parameters (Cont.)

Parameter

Symbol

Comments

Minimum

Typical

Maximum

Unit

mV

Absolute delta of DC

common-model voltage

between D+ and D-

VTX-CM-DC-LINE-

DELTA

DC offset between

D+ and D–

0

–

25

Electrical idle differential

peak output voltage

VTX-IDLE-DIFFp

ITX-SHORT

Peak-to-peak voltage

0

–

20

90

mV

mA

TX short circuit current

Currentlimit whenTX output –

is shorted to ground.

Differential termination

Differential return loss

ZTX-DIFF-DC

RLTX-DIFF

Differential termination

Differential return loss

80

100

–

120

–

ꢀ

8

dB

Common-mode return loss RLTX-CM

Common-mode

return loss

–

TX eye width TTX-EYE

Minimum TX eye width

0.7

–

UI

Document Number: 002-15045 Rev. *F

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CYW43143

14. Thermal Information

Table 24. 56-pin QFN Thermal Characteristics^a

Air Velocity m/s

Power W

1.166

T_{J_MAX}°C

T_t°C

JA, °C/W

37.95

_JT°C/W

0

110.3

105.2

4.37

a. 1s1P JEDEC board, package only, no heat sink, TA = 65°C. P = 1.061W (PA on).

Note:

■ Ambient air temperature is 1 mm above the heat shield on top of the chip.

■ Ambient air temperature: TA = 65°C, subject to absolute junction maximum temperature at 125°C.

■ The CYW43143 is designed and rated for operation at a maximum junction temperature not to exceed 125°C.

14.1 Junction Temperature Estimation and PSI Versus Theta

JT

JC

Package thermal characterization parameter Psi-J ( ) yields a better estimation of actual junction temperature (T ) versus using

T

JT

J

the junction-to-case thermal resistance parameter Theta-J ( ). The reason for this is  assumes that all the power is dissipated

C

JC

through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of

the package.  takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating

JT

the device junction temperature is as follows:

T = T + P 

J

T

JT

Where:

■ T = junction temperature at steady-state condition, °C

J

■ T = package case top center temperature at steady-state condition, °C

T

■ P = device power dissipation, Watts

■  = package thermal characteristics (no airflow), °C/W

JT

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15. Package Information

Figure 7. 7 mm × 7 mm, 56-pin QFN package

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CYW43143

16. Ordering Information

Table 25. Ordering Information

Part Number

Package

Ambient Temperature

0 to 65°C (32 to 149°F)

BCM43143KMLG

7 mm × 7 mm, 56-pin QFN (RoHs compliant)

Document Number: 002-15045 Rev. *F

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CYW43143

Document History

Document Title: CYW43143 Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

Document Number: 002-15045

Revision

ECN

Orig. of Change Submission Date

Description of Change

**

–

-

04/26/12

43143-DS100-R:

Initial release

*A

–

-

06/03/13

43143-DS101-R:

Added:

•

Various features on cover, reorganized feature lists.

“Link Power Management (LPM) Support” on page 16.

“I2S Interface” on page 17.

“Serial Flash Timing” on page 47.

“I2S Slave Mode Tx Timing” on page 48.

Updated:

Figure 1 on page 2.

Figure 3 on page 11.

Figure 4 on page 13.

Note in “Crystal Oscillator” on page 15.

Figure 9 on page 24.

Table 2 on page 25.

Table 3 on page 26.

Table 4 on page 28.

Table 5 on page 32.

Table 6 on page 33.

Table 7 on page 34.

Table 9 on page 36.

Table 10 on page 37.

Table 11 on page 39.

Note in Section 14: “Thermal Information,” on page 56.

Table 24 on page 56

*B

*C

-

06/25/13

02/24/14

43143-DS102-R:

Updated

•

Table 7 on page 34.

43143-DS103-R:

Updated:

•

“Reset and Low-Power Off Mode” on page 12

Table 6: “Absolute Maximum Ratings,” on page 30

Table 8: “WLAN Current Consumption in SDIO Mode using

SR_VDDBAT5V,” on page 32

•

Table 9: “WLAN Current Consumption in USB mode using

VDD33,” on page 33

Table 16: “2.4 GHz Band Transmitter RF Specifications,” on

page 40

Section 14: “Thermal Information,” on page 53

Document Number: 002-15045 Rev. *F

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CYW43143

Document Title: CYW43143 Single-Chip IEEE 802.11b/g/n MAC/PHY/Radio with USB/SDIO Host Interface

Document Number: 002-15045

*D

-

11/14/14

43143-DS104-R:

Updated:

•

Table7:“Guaranteed Operating Conditions and DC

Characteristics,” on page32.

Table8:“WLAN Current Consumption in SDIO Mode using

SR_VDDBAT5V,” on page33.

Table9:“WLAN Current Consumption in USB mode using

VDD33,” on page34.

*E

*F

5448745 UTSV

09/28/2016

04/20/2017

Migrated to Cypress Template

5255423 AESATMP7

Updated Cypress Logo and Copyright.

Document Number: 002-15045 Rev. *F

Page 43 of 44

CYW43143

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44

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Document Number: 002-15045 Rev. *F

Revised April 20, 2017

Page 44 of 44

厂商	型号	描述	页数
CYPRESS	CYW134MOXC	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
CYPRESS	CYW134MOXCT	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
CYPRESS	CYW134SOXC	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
CYPRESS	CYW134SOXCT	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
SPECTRALINEAR	CYW137OXC	FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ]	8 页
SPECTRALINEAR	CYW137OXCT	FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ]	8 页
SILICON	CYW150	[ 440BX AGPset Spread Spectrum Frequency Synthesizer ]	15 页
SILICON	CYW150OXC	[ 440BX AGPset Spread Spectrum Frequency Synthesizer ]	15 页
SILICON	CYW150OXCT	[ 440BX AGPset Spread Spectrum Frequency Synthesizer ]	15 页
CYPRESS	CYW15G0101DXB	单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ]	39 页