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UX2013

型号:

UX2013

描述:

TTL输出限幅放大器>TTL输出的限幅放大器(主放大器或者后置放大器)[ TTL output Limiting Amplifier TTL输出的限幅放大器(主放大器或者后置放大器) ]

品牌:

ETC[ ETC ]

页数:

5 页

PDF大小:

191 K

UX 2103  
TTL output Limiting Amplifier  
General Description  
Pin Configuration  
The UX2103 is a high gain limiting amplifier  
designed for PDH fiber optical receiver systems,  
accepting a wide range of input AC voltages and  
providing TTL output level. It integrates a  
signal detector, with programmable LOS  
threshold. It is available in TSSOP 16-pin  
packages.  
Features  
—
—
+3.3V or +5V Power Supply  
1mV Differential Input Sensitivity  
(BER=10-10)  
—
—
CMOS Configuration output with TTL  
level  
Figure 1. Pin Configuration TSSOP 16  
Alarm Level Compatible with PECL, TTL and  
CMOS Level  
Typical Application Circuit  
Figure 2. Typical Application Circuit  
1
2007 Preliminary Datasheet  
www.uxfastic.com  
UX 2103  
TTL output Limiting Amplifier  
Pin Description  
Pin No.  
Name  
Function  
Auto-zero capacitor pin. A capacitor connected between this pin and AZ2 sets the  
time constant of the offset correction loop. The offset correction is disabled when  
the AZ1 and AZ2 pins are shorted together.  
1
AZ1  
See AZ1.  
2
3
4
5
6
7
AZ2  
GNDA  
INP  
Analog Supply Ground. Must be at same potential as GNDE pin.  
Positive data input  
Negative data input  
INN  
Analog Supply Voltage. Must be at the same potential as the VCCE pin.  
VCCA  
CF  
Level-detect filter capacitor pin. Connect a capacitor between this pin and VCCA.  
The squelch function is disabled when JAM is connected to ground. The automatic  
squelch function is enabled when JAM is connected to the LOSP.  
8
JAM  
Positive Loss-of-Signal output, CMOS level, compatible with PECL and TTL. LOSP is  
low when the level of the input signal is above the preset threshold set by the VSET  
input. LOSP is high when the signal level drops below the threshold. Normally  
connected to JAM pin to enable automatic squelch function to operate.  
Negative Loss-of-signal output, CMOS level, compatible with PECL and TTL. LOSN is  
high when the level of the input signal is above the preset threshold set by the VSET  
input. LOSN is low when the signal level drops below the threshold. Indicates Input  
signal level status.  
9
LOSP  
10  
LOSN  
Digital Supply Ground. Must be the same potential as the GNDA pin.  
11  
12  
13  
14  
GNDE  
N.C.  
No Connection.  
Positive data output, CMOS Configuration with TTL level.  
OUTP  
VCCE  
Digital Supply Voltage. Must be at the same potential as the VCCA pin.  
5V to 3V conversion output pin.No connection or can connect a capacitor  
between this pin and GND.  
V3V  
15  
Loss-of-Signal Threshold Pin. Resistor (RSET) to ground sets the LOS threshold. This  
pin can be left open if the LOS detect function is not required and JAM is connected  
to ground, otherwise connect VSET to ground.  
16  
VSET  
Absolute Maximum Ratings  
Symbol  
VCC  
Parameter  
Rating  
6
Units  
V
Power supply(Note 1)  
Operating ambient  
Storage temperature  
TA  
-40 to +85  
-65 to +150  
°C  
TSTG  
°C  
2
2007 Preliminary Datasheet  
www.uxfastic.com  
UX 2103  
TTL output Limiting Amplifier  
Recommended Operating Conditions  
Symbol  
VCC  
Parameter  
Power supply(Note 1)  
Operating ambient  
Rating  
3.0 to 5.5  
-40 to +85  
Units  
V
TA  
°C  
Note 1: Related to Ground  
DC Characteristics  
Symbol  
Parameter  
Min  
Typ  
VCC  
Max  
Units  
mV  
mVP-P  
V
VOS  
VTH  
Equivalent input Offset Voltage  
LOS Sensitivity Range  
High output  
50  
20  
2
VOH  
VOL  
HYS  
Low output  
GND  
0.5  
V
LOS Hysteresis (Note 2)  
1
2
4
dB  
ICC  
Power-Supply Current (Note 3)  
25.3  
mA  
Note 2: Optical, 10log (VDEASSERT/VASSERT).  
Note 3: LOSN is at CMOS level, no load terminated to the outputs, with I/O current in the output buffer.  
AC Characteristics  
(VCC=+3.0V to +5.5V, Typical values are at VCC = +5V, TA = +25°C, unless otherwise noted.)  
Symbol  
Parameter  
Single ended  
Differential  
Min  
0.5  
1
Typ  
20  
Max  
800  
Units  
VIN  
Input signal voltage  
mV  
1600  
RIN  
CIN  
Input Resistance  
Input Capacitance  
K  
pF  
ps  
ps  
μs  
2
TR, TF  
TPWD  
TLOS  
Data Output Transition Time (Note 5)  
Pulse-Width Distortion(Note 6)  
LOS Assert/Deassert Time  
780  
1900  
150  
100  
Note 4: Single ended; the output buffer is CMOS structure, shown in Figure3.  
Note 5: 20% to 80%  
Note 6: TPWD= [(width of wider pulse)-(width of narrower pulse)]/2.  
3
2007 Preliminary Datasheet  
www.uxfastic.com  
UX 2103  
TTL output Limiting Amplifier  
Applications Information  
TTL output  
CMOS structure.,but it operates TTL level,usually  
teminated by a pull up resistor (4.710K), see  
Figure3.  
Figure 3. TTL Termination Circuit at OUT  
terminated by a pull up resistor (4.710K), see  
Figure4, it compatible with TTL level; When  
terminated by 50to (VCC-2V), see Figure5, it  
compatible with PECL level. The corresponding  
logic states list in table LOS Level Status.  
LOS Output Terminations  
In UX2103, the LOS interface operates three logic  
states with different termination techniques  
respectively. When LOSN is connected directly to  
external circuits, it operates CMOS level; When  
Figure 4. Equivalent TTL Termination Circuit  
at LOSN  
Figure 5. Equivalent PECL Termination  
Circuit at LOSN  
LOS level status  
Logic State  
High  
CMOS  
VCC  
PECL  
TTL  
VCC  
VCC-0.9V  
VCC-2.2V  
Low  
Ground  
Ground to 0.5V  
4
2007 Preliminary Datasheet  
www.uxfastic.com  
UX 2103  
TTL output Limiting Amplifier  
Package Outline  
Details of ‘A’ part  
Figure 6. TSSOP16 Package  
5
2007 Preliminary Datasheet  
www.uxfastic.com  
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