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HYMR26416H

型号:

HYMR26416H

描述:

64Mx16 | 2.5V | 40 | X4 |直接RDRAM - 128MB RIMM\n[ 64Mx16|2.5V|40|x4|Direct RDRAM - 128MB RIMM ]

品牌:

ETC[ ETC ]

页数:

18 页

PDF大小:

286 K

TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Revision History  
* Rev. 0.95  
Date : 2001.07.23  
1. Page2, 7, 8, 10, 12 : Add 2D RIMM part  
Rev. 0.95 / July.01  
1
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Overview  
Key Timing Parameters/Part Numbers  
®
TM  
The Rambus RIMM module is a general purpose  
high-performance memory subsystem suitable for use  
in a broad range of applications including computer  
memory, personal computers, workstations, and other  
applications where high bandwidth and low latency are  
required.  
The following table lists the frequency and latency bins  
available from RIMM modules.  
Table 1: Part Number by Frequency and Latency  
t rac (Row  
I/O Freq.  
Access  
Organization  
Part Number  
MHz  
Time) ns  
The Rambus RIMM module consist of 256/288Mb  
Direct Rambus DRAM devices. These are extremely  
high-speed CMOS DRAMs organized as 16M words  
by 16/18 bits. The use of Rambus Signaling Level  
(RSL) technology permits 600MHz ,711MHz or  
800MHz transfer rates while using conventional  
system and board design technologies. RDRAM  
devices are capable of sustained data transfers at 1.25  
ns per two bytes (10ns per 16 bytes).  
HYMR23216(18)H-653  
HYMR23216(18)H-745  
HYMR23216(18)H-845  
HYMR23216(18)H-840  
HYMR26416(18)H-653  
HYMR26416(18)H-745  
HYMR26416(18)H-845  
HYMR26416(18)H-840  
HYMR212816(18)H-653  
HYMR212816(18)H-745  
HYMR212816(18)H-845  
HYMR212816(18)H-840  
HYMR225616(18)H-653  
HYMR225616(18)H-745  
HYMR225616(18)H-845  
HYMR225616(18)H-840  
32M x 16/18  
32M x 16/18  
32M x 16/18  
32M x 16/18  
64M x 16/18  
64M x 16/18  
64M x 16/18  
64M x 16/18  
128M x 16/18  
128M x 16/18  
128M x 16/18  
128M x 16/18  
256M x 16/18  
256M x 16/18  
256M x 16/18  
256M x 16/18  
600  
711  
800  
800  
600  
711  
800  
800  
600  
711  
800  
800  
600  
711  
800  
800  
53  
45  
45  
40  
53  
45  
45  
The RDRAM architecture enables the highest  
sustained bandwidth for multiple, simultaneous  
randomly addressed memory transactions. The  
separate control and data buses with independent row  
and column control yield over 95% bus efficiency. The  
Direct RDRAM's 32-banks architecture supports up to  
four simultaneous transactions per device.  
40  
53  
45  
45  
40  
53  
Features  
45  
w High speed 800,711 and 600 MHz RDRAM storage  
w 184 edge connector pads with 1 mm pad spacing  
w Maximum module PCB size: 133.5mm x 34.93mm x  
1.37mm(5.21” x 1.375” x 0.05” )  
w Gold plated edge connector pad contacts  
w Serial Presence Detect(SPD) support  
w Operates from a 2.5 volt supply (±5%)  
w Powerdown self refresh modes  
45  
40  
Form Factor  
The Rambus RIMM modules are offered in a 184-pad  
1mm edge connector pad pitch from factor suitable for  
either 184 or 168 contact RIMM connectors. The  
RIMM module is suitable for desktop and other system  
applications. Figure 1 below, shows an eight device  
Rambus RIMM module without heat spreader.  
w mBGA Package (92 balls)  
w Separate Row and Column buses for higher  
efficiency  
Figure 1: Rambus RIMM Module without heat spreader  
Rev. 0.95 / July.01  
2
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Table 2: Module Pad Number and Signal Names  
Pin  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Pin Name  
Gnd  
LDQA8  
Gnd  
LDQA6  
Gnd  
LDQA4  
Gnd  
LDQA2  
Gnd  
LDQA0  
Gnd  
LCTMN  
Gnd  
LCTM  
Gnd  
NC  
Gnd  
LROW1  
Gnd  
LCOL4  
Gnd  
LCOL2  
Gnd  
LCOL0  
Gnd  
LDQB1  
Gnd  
LDQB3  
Gnd  
LDQB5  
Gnd  
LDQB7  
Gnd  
LSCK  
Vcmos  
SOUT  
Vcmos  
NC  
Gnd  
NC  
Vdd  
Vdd  
Pin  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Pin Name  
Gnd  
LDQA7  
Gnd  
LDQA5  
Gnd  
LDQA3  
Gnd  
LDQA1  
Gnd  
LCFM  
Gnd  
LCFMN  
Gnd  
NC  
Gnd  
LROW2  
Gnd  
LROW0  
Gnd  
LCOL3  
Gnd  
LCOL1  
Gnd  
LDQB0  
Gnd  
LDQB2  
Gnd  
LDQB4  
Gnd  
LDQB6  
Gnd  
LDQB8  
Gnd  
LCMD  
Vcmos  
SIN  
Vcmos  
NC  
Gnd  
NC  
Vdd  
Vdd  
Pin  
Pin Name  
NC  
NC  
NC  
NC  
Vref  
Gnd  
SCL  
Vdd  
Pin  
Pin Name  
NC  
NC  
NC  
NC  
Vref  
Gnd  
SA0  
Vdd  
SA1  
SVdd  
SA2  
Vdd  
RCMD  
Gnd  
RDQB8  
Gnd  
RDQB6  
Gnd  
RDQB4  
Gnd  
RDQB2  
Gnd  
RDQB0  
Gnd  
RCOL1  
Gnd  
RCOL3  
Gnd  
RROW0  
Gnd  
RROW2  
Gnd  
NC  
Gnd  
RCFMN  
Gnd  
RCFM  
Gnd  
RDQA1  
Gnd  
RDQA3  
Gnd  
RDQA5  
Gnd  
A47  
A48  
A49  
A50  
A51  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
A63  
A64  
A65  
A66  
A67  
A68  
A69  
A70  
A71  
A72  
A73  
A74  
A75  
A76  
A77  
A78  
A79  
A80  
A81  
A82  
A83  
A84  
A85  
A86  
A87  
A88  
A89  
A90  
A91  
A92  
B47  
B48  
B49  
B50  
B51  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
B63  
B64  
B65  
B66  
B67  
B68  
B69  
B70  
B71  
B72  
B73  
B74  
B75  
B76  
B77  
B78  
B79  
B80  
B81  
B82  
B83  
B84  
B85  
B86  
B87  
B88  
B89  
B90  
B91  
B92  
A9  
B9  
SDA  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
SVdd  
SWP  
Vdd  
RSCK  
Gnd  
RDQB7  
Gnd  
RDQB5  
Gnd  
RDQB3  
Gnd  
RDQB1  
Gnd  
RCOL0  
Gnd  
RCOL2  
Gnd  
RCOL4  
Gnd  
RROW1  
Gnd  
NC  
Gnd  
RCTM  
Gnd  
RCTMN  
Gnd  
RDQA0  
Gnd  
RDQA2  
Gnd  
RDQA4  
Gnd  
RDQA6  
Gnd  
RDQA8  
Gnd  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
RDQA7  
Gnd  
Rev. 0.95 / July.01  
3
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Table 3: Module Connector Pad Description  
Signal  
Module Connector Pads  
I/O Type Description  
A1, A3, A5, A7, A9, A11, A13, A15,  
A17, A19, A21, A23, A25, A27, A29,  
A31, A33, A39, A52, A60, A62, A64,  
A66, A68, A70, A72, A74, A76, A78,  
A80, A82, A84, A86, A88, A90, A92,  
B1, B3, B5, B7, B9, B11, B13, B15,  
B17, B19, B21, B23, B25, B27, B29,  
B31, B33, B39, B52, B60, B62, B64,  
B66, B68, B70, B72, B74, B76, B78,  
B80, B82, B84, B86, B88, B90, B92  
Ground reference for RDRAM core and interface.  
72 PCB connector pads.  
Gnd  
B10  
Clock from master. Interface clock used for receiving  
RSL signals from the Channel. Positive polarity.  
LCFM  
I
I
I
I
I
I
RSL  
RSL  
VCMOS  
RSL  
RSL  
RSL  
B12  
Clock from master. Interface clock used for receiving  
RSL signals from the Channel. Negative polarity.  
LCFMN  
LCMD  
B34  
Serial Command used to read from and write to the  
control registers. Also used for power management.  
A20, B20, A22, B22, A24  
Column bus. 5-bit bus containing control and address  
information for column accesses.  
LCOL4..  
LCOL0  
A14  
Clock to master. Interface clock used for transmit-  
ting RSL signals to the Channel. Positive polarity.  
LCTM  
A12  
Clock to master. Interface clock used for transmit-  
ting RSL signals to the Channel. Negative polarity.  
LCTMN  
A2, B2, A4, B4, A6, B6, A8, B8, A10  
Data bus A. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
LDQA8 is non-functional on x16 RDRAM devices.  
LDQA8..  
LDQA0  
I/O RSL  
I/O RSL  
B32, A32, B30, A30, B28, A28, B26,  
A26, B24  
Data bus B. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
LDQB8 is non-functional on x16 RDRAM devices.  
LDQB8..  
LDQB0  
B16, A18, B18  
A34  
Row bus. 3-bit bus containing control and address  
information for row accesses.  
LROW2..  
LROW0  
I
I
RSL  
Serial Clock input. Clock source used to read from  
and write to the RDRAM control registers.  
LSCK  
VCMOS  
A16, B14, A38, B38, A40, B40, A77,  
B79  
These pads are not connected. These 8 connector  
pads are reserved for future use.  
NC  
A43, B43, A44, B44, A45, B45, A46,  
B46, A47, B47, A48, B48, A49, B49,  
A50, B50  
These pads are not connected. These 16connector  
pads art reserved for future use. The 168 contact  
RIMM connector does not connect to these PCB  
pads.  
NC  
B83  
B81  
Clock from master. Interface clock used for receiv-  
ing RSL signals from the Channel. Positive polarity.  
RCFM  
I
I
RSL  
RSL  
Clock from master. Interface clock used for receiv-  
ing RSL signals from the Channel. Negative polar-  
ity.  
RCFMN  
Rev. 0.95 / July.01  
4
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Signal  
Module Connector Pads  
I/O Type Description  
B59  
Serial Command Input used to read from and write  
to the control registers. Also used for power  
management.  
RCMD  
I
VCMOS  
A73, B73, A71, B71, A69  
Column bus. 5-bit bus containing control and  
address information for column accesses.  
RCOL4..  
RCOL0  
I
I
I
RSL  
RSL  
RSL  
A79  
A81  
Clock to master. Interface clock used for transmit-  
ting RSL signals to the Channel. Positive polarity.  
RCTM  
Clock to master. Interface clock used for transmit-  
ting RSL signals to the Channel. Negative polarity.  
RCTMN  
A91, B91, A89, B89, A87, B87, A85,  
B85, A83  
Data bus A. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
RDQA8 is non-functional on x16 RDRAM devices.  
RDQA8..  
RDQA0  
I/O RSL  
I/O RSL  
B61, A61, B63, A63, B65, A65, B67,  
A67, B69  
Data bus B. A 9-bit bus carrying a byte of read or  
write data between the Channel and the RDRAM.  
RDQB8 is non-functional on x16 RDRAM devices.  
RDQB8..  
RDQB0  
B77, A75, B75  
A59  
Row bus. 3-bit bus containing control and address  
information for row accesses.  
RROW2..  
RROW0  
I
I
RSL  
Serial Clock input. Clock source used to read from  
and write to the RDRAM control registers.  
RSCK  
VCMOS  
B53  
B55  
B57  
A53  
A55  
B36  
Serial Presence Detect Address 0.  
Serial Presence Detect Address 1.  
Serial Presence Detect Address 2.  
Serial Presence Detect Clock.  
SA0  
SA1  
SA2  
SCL  
SDA  
SIN  
I
I
I
I
SVDD  
SVDD  
SVDD  
SVDD  
Serial Presence Detect Data (Open Collector I/O)  
I/O SVDD  
I/O VCMOS  
Serial I/O for reading from and writing to the control  
registers. Attaches to SIO0 of the first RDRAM on  
the module.  
A36  
Serial I/O for reading from and writing to the control  
registers. Attaches to SIO1 of the last RDRAM on  
the module.  
SOUT  
I/O VCMOS  
A56, B56  
SPD Voltage. Used for signals SCL, SDA, SWE,  
SA0, SA1 and SA2.  
SVDD  
SWP  
VCMOS  
Vdd  
A57  
Serial Presence Detect Write Protect (active high).  
When low, the SPD can be written as well as read.  
I
I
SVDD  
A35, B35, A37, B37  
CMOS I/O Voltage. Used for signals CMD, SCK,  
SIN, SOUT.  
A41, A42, A54, A58, B41, B42, B54,  
B58  
Supply voltage for the RDRAM core and interface  
logic.  
A51, B51  
Logic threshold reference voltage for RSL signals.  
Vref  
Rev. 0.95 / July.01  
5
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
SIO0  
SIO1  
SCK  
CMD  
Vref  
Direct RDRAM (256/288Mb) U1  
Direct RDRAM (256/288Mb) U2  
Direct RDRAM (256/288Mb) U3  
SIO0  
SIO1  
SCK  
CMD  
Vref  
SIO0  
SIO1  
SCK  
CMD  
Vref  
SIO0  
SIO1  
SCK  
CMD  
Vref  
Direct RDRAM (256/288Mb) UN  
Vdd  
Serial Presence Detect  
VCMOS  
2 per  
1 per  
SVDD  
RDRAM  
0.1Þ§  
2 RDRAMs  
0.1Þ§  
Vcc  
Gnd  
VREF  
Gnd  
SCL  
SWP  
SCL  
WP  
SDA  
SDA  
SVDD  
1 per  
A0A1A2  
2 RDRAMs  
Plus one  
Near Connector  
0.1Þ§  
U0  
0.1Þ§  
SA0  
SA1  
SA2  
Gnd  
Gnd  
Note 1: Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.  
Note 2: See Serial Presence Detection Specification for information on the SPD device and its contents.  
Figure 2: RIMM Module Functional Diagram  
Rev. 0.95 / July.01  
6
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Absolute Maximum Ratings  
Signal  
Parameter  
Min  
Max  
Unit  
Voltage applied to any RSL or CMOS pin with respect to Gnd  
Voltage on VDD with respect to Gnd  
Storage temperature  
VI,ABS  
V
V
- 0.3  
- 0.5  
- 50  
-
V DD + 0.3  
V DD + 1.0  
100  
VDD,ABS  
TSTORE  
TPLATE  
ºC  
ºC  
Plate temperature  
100  
DC Recommended Electrical Conditions  
Signal  
VDD  
Parameter and Conditions  
Min  
Max  
Unit  
Supply voltage  
V
2.50 - 0.13  
2.50 + 0.13  
CMOS I/O power supply at pad for 2.5V controllers:  
CMOS I/O power supply at pad for 1.8V controllers:  
VCMOS  
V
V
2.5 - 0.13  
1.8 - 0.1  
2.5 + 0.25  
1.8 + 0.2  
VREF  
VSPD  
VIL  
Reference voltage  
V
V
1.4 - 0.2  
2.2  
1.4 + 0.2  
3.6  
Serial Presence Detector - Positive power supply  
RSL input low voltage  
V
VREF - 0.5  
VREF + 0.2  
- 0.3  
VREF - 0.2  
VREF + 0.5  
0.5VCMOS - 0.25  
VCMOS + 0.3  
0.3  
VIH  
RSL input high voltage  
V
VIL,CMOS  
CMOS input low voltage  
V
VIH,CMOS CMOS input high voltage  
VOL,CMOS  
V
0.5VCMOS + 0.25  
CMOS output low voltage @ IOL,CMOS = 1mA  
VOH,CMOS CMOS output high voltage @ IOH,CMOS = -0.25mA  
V
V
VCMOS - 0.3  
-10 x no. RDRAMsa  
-10 x no. RDRAMsa  
-10.0  
10 x no. RDRAMsa  
10 x no. RDRAMsa  
10.0  
IREF  
VREF current @ VREF,MAX  
µA  
µA  
µA  
CMOS input leakage current @ (0 £ VCMOS £ VDD  
CMOS input leakage current @ (0 £ VCMOS £ VDD  
)
)
ISCK,CMD  
ISIN,SOUT  
a. The tale below shows the number of 256Mb or 288Mb RDRAM devices contained in a RIMM module of listed memory storage capacity  
512/576MB 384/432MB 256/288MB 128/144MB 64/72MB  
RIMM Module Capacity:  
Number of 256Mb or 288Mb RDRAM devices:  
16  
12  
8
4
2
Rev. 0.95 / July.01  
7
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
RIMM Module Current Profile  
RIMM Module Capacity:  
No. of 256/288Mb RDRAMs:  
512/576MB  
16  
384/423MB  
12  
256/288MB  
8
128/144MB  
4
64/72MB  
2
IDD  
IDD1  
IDD2  
IDD3  
IDD4  
IDD5  
IDD6  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
RIMM Module power conditionsa  
Freq.  
Max  
Max  
Max  
Max  
Max  
800  
711  
600  
800  
711  
600  
800  
711  
600  
800  
711  
600  
800  
711  
600  
800  
711  
600  
798  
746  
782  
730  
767  
714  
751  
698  
742  
679  
584  
1040  
987  
866  
860  
800  
670  
899  
792  
689  
892  
840  
711  
1235  
1120  
1004  
One RDRAM in Readb, balance  
in NAP mode  
641  
625  
609  
593  
2860  
2667  
2406  
3100  
2900  
2350  
956  
2340  
2187  
1996  
2460  
2300  
1870  
940  
1820  
1707  
1526  
1820  
1700  
1390  
924  
1300  
1227  
1086  
1180  
1100  
910  
One RDRAM in Readb, balance  
in Standby mode  
One RDRAM in Readb, balance  
in Active mode  
908  
One RDRAM in Writeb, balance  
in NAP mode  
851  
835  
819  
803  
746  
730  
714  
698  
2868  
2800  
2262  
3055  
2800  
2544  
2303  
2240  
1818  
2535  
2320  
2104  
1738  
1680  
1375  
2015  
1840  
1664  
1174  
1120  
932  
One RDRAM in Writeb, balance  
in Standby mode  
1495  
1360  
1224  
One RDRAM in Writeb, balance  
in Active mode  
a. Actual Power will depend on individual RDRAM component specifications, memory controller and usage patterns. Please refer to  
specific RIMM module vendor data sheets for additional information.  
b. I/O current is a function of the % of 1s’ , to add I/O power for 50% 1s for a x16 need to add 257mA or 290mA for x18 ECC modu le for  
the following : VDD = 2.5V, VTERM = 1.8V, VREF = 1.4V and VDIL = VREF - 0.5V.  
Rev. 0.95 / July.01  
8
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
AC Electrical Specifications  
Parameter and Condition  
Min  
Typ  
Max  
Unit  
Symbol  
ZL  
Module Impedance of RSL Signals  
25.2  
23.8  
28  
28  
30.8  
32.2  
W
W
ZUL-CMOS  
TPD  
Module Impedance of SCK and CMD signals  
Average clock delay form finger to finger of all RSL clock nets  
(CTMN, CFM, and CFMN)  
See  
Tablea  
-
ns  
ps  
ps  
ps  
ps  
%
a,b  
a,b  
Propagation delay variation of RSL signals with respect to TPD  
for 4, 6, 8, and 12 device modules  
DTPD  
-21  
21  
24  
Propagation delay variation of RSL signals with respect to TPD  
for 16 device modules  
-24  
DTPD-CMOS Propagation delay variation of SCK signal with respect to  
-250  
-200  
250  
200  
an average clock delaya  
DTPD-SCK  
Propagation delay variation of CMD signal with respect to  
SCK signal  
,CMD  
See  
Tablea  
V /V  
a
Attenuation Limit  
IN  
Forward crosstalk coefficient (300ps input rise time 20%-80%)  
Backward crosstalk coefficient (300ps input rise time 20%-80%)  
See  
VXF /VIN  
VXB /VIN  
%
Tablea  
See  
Tablea  
%
a. Tpd or Average clock delay is defined as the average delay from finger of all RSL clock nets(CTM, CTMN, CFM, and CFMN)  
b. If the RIMM module meets the following specification, then it is compliant to the specification. If the RIMM module does not meet  
these specifications, then the specification can be adjusted by the “ Adjusted DT  
Specification” table  
PD  
Adjusted  
DTPD Specification  
Absolute  
Min/Max  
Symbol Parameter and Conditions  
Adjusted Min/Max  
Unit  
ns  
Propagation delay variation of RSL signals with respect  
to TPD for 4,6 and 8 device modules  
T
D
+/-[17+(18*N* Z0)]a  
-30  
-40  
-50  
30  
40  
50  
PD  
D
Propagation delay variation of RSL signals with respect  
to TPD for 12 device modules  
+/-[20+(18*N* DZ0)]a  
+/-[24+(18*N* DZ0)]a  
ps  
Propagation delay variation of RSL signals with respect  
to TPD for 16 device modules  
ps  
a. Where : N =Number of RDRAM devices installed on the RIMM module  
DZ0 = delta Z0% = (max Z0 - min Z0)/(min Z0)  
(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)  
Rev. 0.95 / July.01  
9
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
AC Electrical Specifications for RIMM Modules  
RIMM Module Capacity:  
512/576MB 384/432MB 256/288MB 128/144MB 64/72MB  
No. of 256/288Mb RDRAMs:  
16  
12  
8
4
2
Symbol  
Unit  
Parameter and Condition for -800, -711  
& -600 RIMM Module  
Max  
Max  
Max  
Max  
Max  
TPD  
Propagation Delay, all RSL signals  
Attenuation Limit -800, -711  
Attenuation Limit -600  
2.11  
25.0  
18.5  
1.76  
20.0  
15.5  
1.56  
16.0  
12.5  
1.28  
12.0  
10.5  
1.28  
12.0  
10.5  
ns  
%
%
Va / VIN  
Forward crosstalk coefficient (300ps input  
rise time @ 20%-80%) -800, -711, -600  
VXF / VIN  
8.0  
6.0  
4.0  
2.0  
2.0  
%
Backward crosstalk coefficient (300ps input  
rise time @ 20%-80%) -800, -711, -600  
VXB / VIN  
RDC  
2.5  
1.2  
2.3  
1.1  
2.0  
0.8  
1.5  
0.6  
1.5  
0.6  
%
DC Resistance Limit -800, -711, -600  
W
Rev. 0.95 / July.01  
10  
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Physical Dimensions  
The following defines the RIMM module dimensions. All units are in millimeters. The height of the module  
is 31.75mm.  
133.35 ± 0.15  
1.27 ± 0.1  
3.0  
4.0  
± 0.15  
Top Area - N Components  
Detail A  
34.925  
± 0.127  
R 2.0  
17.78  
Detail B  
A1  
A92  
5.675  
11.5  
4.5  
45.0  
27.5  
Max. 7.37  
55.175 ± 0.08  
Including  
Heat spreader  
B92  
B1  
0.8 ± 0.1  
1.0  
2.99 ± 0.05  
R 1.0  
3.0 ± 0.1  
2.0 ± 0.1  
0.15 ± 0.1  
Detail A  
Detail B  
Note 1.Tolerances on all dimensions ± 0.127mm unless otherwise specified.  
2.Thickness(* Mark) includes plating and/or metallization.  
Figure 3: RIMM Module PCB Physical Description  
Module Weight  
The maximum RIMM Module weight is 75gm(2.625oz) with a center of mass 35mm (1.378 in.) upwards  
from bottom edge.  
Rev. 0.95 / July.01  
11  
TM  
RIMM Module  
with 256/288Mb RDRAMs Preliminary  
Standard RIMM Module Marking  
The RIMM modules available from RIMM module  
manufacturers will be marked per Figure 4 below. This  
industry standard marking will help OEMs and users  
identify the Rambus RIMM modules for use in specific  
system application. This marking also assists OEMs  
or users to specify and verify if the correct RIMM  
B
I
F
A
C
HYMR212818H-840 G100  
512MB / 8  
R A M B U S 800-45  
KOREA YWWDV  
S100  
H
J
G
D
E
Label Field  
Description  
Marked Text  
Unit  
Module Memory  
capacity  
Number of 8-bit or 9-bit Mbytes of RDRAM  
storage in RIMM module  
512MB, 384MB  
256MB,128MB,64MB  
A
B
C
MBytes  
Number of  
DRDRAMs  
Number of RDRAM devices contained in the  
RIMM module  
RDRAM  
devices  
/16, /12, /8, /4, /2  
Indicates whether the RIMM module supports  
8-bit (no ECC) or 9-bit (ECC) Bytes  
Blank = 8-bit Byte  
ECC = 9-bit Byte  
ECC support  
D
E
Memory Speed  
tRAC  
Data transfer speed for RDRAM RIMM module 800, 711, 600  
-40, -45, -50, -53 or  
MHz  
ns  
Row Access Time (Optional field)  
blank  
PCB Gerber file revision used on RIMM Module Rev 1.00 = G100 or  
F
Gerber Version  
SPD Version  
(Optional field)  
blank  
Rev 1.00 = S100 or  
blank  
G
SPD Code Version (Optional field)  
H
I
Country  
Vendor  
Vendor  
Country Area  
Korea  
Hynix specific RIMM module Information  
Hynix specific Date code, Ass’y Vender  
Product Part No  
YWWDV  
J
Figure 4: Standard RIMM Module Marking  
Rev. 0.95 / July.01  
12  
HYMR2xxx16(18)H  
Rambus Module Serial Presence Detect  
SPD Specification  
based on 256/288Mb RDRAM  
Version 1.1  
July 2001  
Rev. 1.1/July 01  
1
HYMR2xxx16(18)H  
Rambus Module Serial Presence Detect  
Revision History  
Revision 1.1 (July 2001)  
Added 2D Product.  
- Added 2D items at Byte75, 76, 77 regarding Part Number  
- Added 2D items at Byte99, 101, 102 regarding device number  
- Added 2D checksum data.  
Rev. 1.1/July 01  
2
HYMR2xxx16(18)H  
Rambus Module Serial Presence Detect  
SERIAL PRESENCE DETECT  
FUNCTION  
-845 -745  
Hex VALUE  
-845 -745  
BYTE  
NUMBER  
FUNCTION  
DESCRIPTION  
NOTE  
-840  
-653  
-840  
-653  
BYTE0  
SPD Revision Level  
SPD Revision 1.0  
256Bytes  
02h  
08h  
01h  
01h  
97h  
C5h  
05h  
20h  
02h  
05h  
08h  
14h  
BYTE1  
Total # of Bytes in the SPD  
BYTE2  
Device Type  
Direct RDRAM  
RIMM  
BYTE3  
Module Type  
BYTE4  
Row Address bits[0:3], Column Address bits[0:3]  
Bank Address bits and Type  
Refresh Bank bits  
9bits, 7bits  
BYTE5  
32Banks (5bank bits)  
32 Refresh Bank Sets  
32ms  
BYTE6  
BYTE7  
Refresh Reriod (tREF)  
BYTE8  
Protocol Version  
Protocol Version 1  
DQS=1.5, no-LP, S28, S3  
8cycles  
BYTE9  
Miscellaneous Device Configuration Field  
Minimum Precharge to RAS time(tRP-R,Min)  
Minimum RAS to Precharge time(tRAS-R,Min)  
Minimum RAS to CAS time(tRCD-R,Min)  
Minimum RAS to RAS time(tRR-R,Min)  
Minimum Precharge to Precharge time(tPP-R,Min)  
Min tCYCLE for RangeA  
BYTE10  
BYTE11  
BYTE12  
BYTE13  
BYTE14  
BYTE15  
BYTE16  
BYTE17  
BYTE18  
BYTE19  
BYTE20  
BYTE21  
BYTE22  
BYTE23  
BYTE24  
BYTE25  
BYTE26  
BYTE27  
BYTE28  
BYTE29  
BYTE30  
20cycles  
8cycles  
10cycles  
8cycles  
8cycles  
2.80ns  
3.83ns  
8cycles  
8cycles  
3.33ns  
08h  
0Ah  
08h  
15h  
08h  
1Ah  
08h  
08h  
2.50ns  
13h  
Max tCYCLE for RangeA  
1Eh  
59h  
AAh  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
00h  
tCDLY Range for RangeA  
5tCYCLE ~ 9tCYCLE  
2tCYCLE for tCLS & tCAS  
Reserved  
tCLS and tCAS Range for RangeA  
Min tCYCLE for RangeB  
Max tCYCLE for RangeB  
Reserved  
tCDLY Range for RangeB  
Reserved  
tCLS and tCAS Range for RangeB  
Min tCYCLE for RangeC  
Reserved  
Reserved  
Max tCYCLE for RangeC  
Reserved  
tCDLY Range for RangeC  
Reserved  
tCLS and tCAS Range for RangeC  
Min tCYCLE for RangeD  
Reserved  
Reserved  
Max tCYCLE for RangeD  
Reserved  
tCDLY Range for RangeD  
Reserved  
tCLS and tCAS Range for RangeD  
Reserved  
Power Down Exit Max. time, PhaseA(tPD-  
NXA,Max)  
Power Down Exit Max. time, PhaseB(tPD-  
NXB,Max)  
BYTE31  
BYTE32  
4us  
04h  
8Dh  
9000tCYCLE  
BYTE33  
BYTE34  
Nap Exit Max.time, PhaseA(tNAPXA,Max)  
Nap Exit Max.time, PhaseB(tNAPXB,Max)  
50ns  
40ns  
32h  
28h  
fIMIN[11:8],  
fIMAX[11:8]  
261MHz,  
400MHz  
261MHz,  
357MHz  
261MHz,  
300MHz  
BYTE35  
11h  
05h  
BYTE36  
BYTE37  
BYTE38  
BYTE39  
BYTE40  
fIMIN[7:0]  
261MHz  
357MHz  
Reserved  
fIMAX[7:0]  
400MHz  
300MHz  
90h  
65h  
2Ch  
ODF Mapping  
00h  
64h  
64h  
Max time between Current Control(tCCTRL,Max)  
Max time between Temp. Calibration(tTEMP,Max)  
100ms  
100ms  
Max time between Temp. Calibration Enable and  
Command (tTCEN,Min)  
BYTE41  
BYTE42  
BYTE43  
150tCYCLE  
64us  
96h  
40h  
0Ah  
Maximum RAS to Precharge time(tRAS-R,Max)  
Maximum time that a Device can stay in Nap  
Mode (tNLIMIT,Max)  
10us  
Rev. 1.1/July 01  
3
HYMR2xxx16(18)H  
Rambus Module Serial Presence Detect  
Continued  
FUNCTION  
-845 -745  
Hex VALUE  
-845 -745  
BYTE  
NUMBER  
FUNCTION  
DESCRIPTION  
Opti  
on  
NOTE  
-840  
-653  
-840  
-653  
BYTE44  
BYTE45  
BYTE46  
ACTREFPT[3:0], PCHREFPT[3:0]  
6tCYCLE, 6tCYCLE  
5tCYCLE, 5tCYCLE  
5tCYCLE, 13tCYCLE  
66h  
55h  
5Dh  
CPCHREFPT_DC[3:0], RDREFPT_DC[3:0]  
RETREFPT_DC[3:0], WRREFPT_DC[3:0]  
BYTE47~  
49  
Reserved  
-
00h  
01h  
BYTE50  
BYTE51  
BYTE52  
fRAS[11:8]  
400MHz  
357MHz  
300MHz  
fRAS[7:0]  
90h  
65h  
2Ch  
PMAX,HI,PMAX,LO,Tj  
HeatSpreader, thermal sensor, Tplate  
PSTBY,HI  
0,0,100  
2 4h  
A4h  
BYTE53  
BYTE54  
BYTE55  
BYTE56  
BYTE57  
BYTE58  
BYTE59  
BYTE60  
BYTE61  
BYTE62  
BYTE63  
BYTE64  
1,0,100℃  
120mA  
130mA  
200mA  
750mA  
TBD  
110mA  
180mA  
650mA  
TBD  
82h  
64h  
5Eh  
00h  
00h  
00h  
78h  
5Fh  
58h  
00h  
00h  
00h  
6Eh  
5Ah  
4Bh  
00h  
00h  
00h  
PACTI,HI  
190mA  
700mA  
TBD  
PACTRW,HI  
PSTBY,LO  
PACTI,LO  
TBD  
TBD  
TBD  
PACTRW,HI  
TBD  
TBD  
TBD  
PNAP  
4.2mA  
21h  
00h  
00h  
PRESA(Reserved for a future thermal parameter)  
PRESB(Reserved for a future thermal parameter)  
Checksum for bytes 0 ~ 62  
Reserved  
Reserved  
-
0Bh  
0Dh  
A2h  
19h  
Module Manufacturer ID Code  
Hynix  
ADh  
00h  
BYTE65~  
71  
..... Module Manufacturer ID Code  
Module Manufacturing Location  
Hynix  
Hynix (Korea Area)  
HSA (United States Area)  
HSE (Europe Area)  
HSJ (Japan Area)  
Asia Area  
0*h  
1*h  
2*h  
3*h  
4*h  
BYTE72  
1
BYTE73  
BYTE74  
Module Part Number (Component)  
R (Rambus)  
52h  
32h  
20h  
20h  
31h  
31h  
32h  
33h  
36h  
32h  
39h  
35h  
32h  
34h  
38h  
32h  
36h  
2,3  
2,3  
Module Part Number (256/288Mb based)  
2
2D  
Blank  
4D  
8D  
Blank  
BYTE75  
BYTE76  
BYTE77  
Module Part Number (Memory Width)  
... Module Part Number (Memory Width)  
..... Module Part Number (Memory Width)  
1
1
2
3
6
2
9
5
3
4
8
2
6
2,3  
2,3  
2,3  
12D  
16D  
2D  
4D  
8D  
12D  
16D  
2D  
4D  
8D  
12D  
16D  
Rev. 1.1/July 01  
4
HYMR2xxx16(18)H  
Rambus Module Serial Presence Detect  
Continued  
FUNCTION  
-845 -745  
Hex VALUE  
-845 -745  
BYTE  
NUMBER  
FUNCTION  
DESCRIPTION  
Opti  
on  
NOTE  
2,3  
-840  
-653  
-840  
-653  
16bits  
18bits  
16bits  
18bits  
1
31h  
31h  
36h  
38h  
48h  
2Dh  
BYTE78  
BYTE79  
Module Part Number (Data Width)  
1
6
..... Module Part Number (Data Width)  
2,3  
8
H
BYTE80  
BYTE81  
BYTE82  
BYTE83  
BYTE84  
Module Part Number (Manufacturing Site)  
Module Part Number (Hyphent)  
2,3  
2,3  
2,3  
2,3  
2,3  
-(Hyphen)  
Module Part Number (tRAC & Speed)  
Module Part Number (tRAC & Speed)  
Module Part Number (tRAC & Speed)  
8
4
0
8
4
5
7
4
5
6
5
3
38h  
34h  
30h  
38h  
34h  
35h  
37h  
34h  
35h  
36h  
35h  
33h  
BYTE85  
~90  
Module Part Number  
Module Revision Code  
Blank  
-
20h  
-
2,3  
BYTE91~  
92  
BYTE93  
BYTE94  
Module Manufacturing Year  
Module Manufacturing Week  
Module Serial Number  
-
-
-
-
-
-
BYTE95  
~98  
2D  
4D  
2
02h  
04h  
08h  
0Ch  
10h  
10h  
12h  
03h  
0Fh  
FFh  
FFh  
FFh  
00h  
00h  
00h  
0Fh  
FFh  
4
BYTE99  
BYTE100  
BYTE101  
Number of Devices on module  
Module Data Width  
8D  
8
12D  
16D  
16bits  
18bits  
2D  
12  
16  
16  
18  
All 2Devices  
All 4Devices  
All 8Devices  
All 12Devices  
All 16Devices  
All 2Devices  
All 4Devices  
All 8Devices  
All 12Devices  
All 16Devices  
4D  
Device Enalbes  
8D  
12D  
16D  
2D  
4D  
BYTE102  
..... Device Enalbes  
..... Device Enalbes  
8D  
12D  
16D  
BYTE103  
~104  
-
00h  
BYTE105  
BYTE106  
Module Vdd, Module Voltage Interface Level  
Module Vdd Tolerance  
2.5Vdd,1.8Vterm  
5% DC, 2% AC  
10h  
52h  
BYTE107  
~113  
Reserved  
-
00h  
BYTE114  
BYTE115  
BYTE116  
BYTE117  
BYTE118  
BYTE119  
CDLY0/1 for tCDLY=3  
CDLY0/1 for tCDLY=4  
CDLY0/1 for tCDLY=5  
CDLY0/1 for tCDLY=6  
CDLY0/1 for tCDLY=7  
CDLY0/1 for tCDLY=8  
-
00h  
20h  
30h  
31h  
32h  
42h  
2/0  
3/0  
3/1  
3/2  
4/2  
Rev. 1.1/July 01  
5
HYMR2xxx16(18)H  
Rambus Module Serial Presence Detect  
Continued  
FUNCTION  
-845 -745  
Hex VALUE  
-845 -745  
BYTE  
NUMBER  
FUNCTION  
DESCRIPTION  
Option  
NOTE  
-840  
-653  
-840  
-653  
BYTE120  
BYTE121  
BYTE122  
BYTE123  
BYTE124  
BYTE125  
BYTE126  
CDLY0/1 for tCDLY=9  
CDLY0/1 for tCDLY=10  
CDLY0/1 for tCDLY=11  
CDLY0/1 for tCDLY=12  
CDLY0/1 for tCDLY=13  
CDLY0/1 for tCDLY=14  
CDLY0/1 for tCDLY=15  
5/2  
-
52h  
00h  
00h  
00h  
00h  
00h  
00h  
BEh  
CCh  
C0h  
D3h  
C7h  
C0h  
CEh  
C2h  
D5h  
C9h  
-
-
-
-
-
2D  
2
4D  
8D  
4
16bit  
s
8
12D  
16D  
2D  
12  
16  
2
BYTE127  
Checksum for bytes 99 - 126  
4D  
4
18bit  
s
8D  
8
12D  
16D  
12  
16  
BYTE128  
+
Open for Customer use  
-
Undefined  
Note :  
1. Refer to Hynix Web Site.  
2. ASCII adopted  
3. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90  
Rev. 1.1/July 01  
6
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