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CYW2320ZIT

型号：

CYW2320ZIT

品牌：

ETC[ ETC ]

页数：

9 页

PDF大小：

178 K

下载PDF手册
CYW2320  
Serial Input PLL with 2.0-GHz Prescaler  
Features  
Applications  
• Operating voltage 2.7V to 5.5V  
• Wireless LAN  
• Operating frequency: up to 2.0 GHz with prescaler  
ratios of 64/65 and 128/129  
• Lock detect feature  
• Wireless communication handsets  
• Base Stations  
• Microcells  
• Power-down mode  
• 20-pin TSSOP (Thin Shrink Small Outline Package)  
CYW2320 PLL Block Diagram  
VCC (5)  
VP (4)  
GND (7)  
(6)  
DO  
fp  
Prescaler  
64/65 or  
128/129  
(10)  
Phase  
Detector  
Charge  
Pump  
Binary 7-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
FIN  
(16)  
BISW  
(15)  
FC  
(20)  
(18)  
r
18-Bit  
Latch  
p
fr  
(8)  
(1)  
(3)  
OSC_IN  
LD  
14-Bit  
Reference Counter  
OSC_OUT  
Latch  
Selector  
15-Bit  
Latch  
(14)  
(13)  
LE  
Divider  
(17)  
Output  
(fr/fp)  
MUX  
FOUT  
DATA  
Cntrl 19-Bit  
Shift  
Reg  
(11)  
(19)  
CLOCK  
PWDN  
Pin Configuration  
OSC_IN  
NC  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
r
PWDN  
OSC_OUT  
VP  
3
p
4
Fout  
VCC  
5
BISW  
FC  
DO  
6
GND  
LD  
7
LE  
8
DATA  
NC  
NC  
9
FIN  
10  
CLOCK  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
February 14, 2000, rev. **  
CYW2320  
R4  
R5  
Q1  
(1)  
(2)  
(3)  
(20)  
(19)  
(18)  
R6  
Q2  
1000p  
Crystal  
Osc.  
Input  
OSCIN  
r
NC  
PWDN  
R7  
OSCOUT  
p
Q4  
100p  
Q3  
0.1µ  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
(17)  
(16)  
(15)  
(14)  
(13)  
(12)  
VP  
FOUT  
R8  
R9  
VP  
Vp  
0.1µ  
VCC  
BISW  
FC  
VCC  
100p  
DO  
C1  
C2 R2  
C3  
GND  
LD  
LE  
R3  
DATA  
NC  
VCC  
VP  
100k  
NC  
MMBT200  
LD  
33k  
Lock  
Detect  
0.01 µF  
10k  
(10)  
(11)  
18Ω  
FIN  
CLOCK  
18Ω  
18Ω  
100 pF  
50Ω  
RFOUT  
From  
Controller  
Figure 1. Application Diagram Example - CYW2320 2.0-GHz PLL  
2
CYW2320  
Pin Definitions  
Pin  
No.  
Pin  
Pin Name  
OSC_IN  
NC  
Type  
Pin Description  
1
2
3
4
5
I
Oscillator Input: This input has a V /2 threshold and CMOS logic level sensitivity.  
CC  
No Connect  
OSC_OUT  
O
P
P
Oscillator Output  
V
V
Charge Pump Rail Voltage: This supply for charge pump. Must be > V  
.
CC  
P
Power Supply Connection for PLL: When power is removed from V all latched  
CC  
CC  
data is lost.  
D
6
O
Charge Pump Output: The phase detector gain is I /2π. Sense polarity can be re-  
O
P
versed by setting FC LOW (pin 15).  
GND  
LD  
7
8
G
O
Analog and Digital Ground Connection: This pin must be grounded.  
Lock Detect Pin: This output is HIGH with narrow LOW pulses when the loop is locked.  
No Connect  
NC  
9
F
10  
11  
I
I
Input to Prescaler: Maximum frequency 2.0 GHz.  
IN  
CLOCK  
Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge  
of this signal.  
NC  
12  
13  
14  
No Connect  
DATA  
LE  
I
I
Serial Data Input  
Load Enable: On the rising edge of this signal, the data stored in the Shift Register is  
latched into the counters and configuration controls.  
F
15  
I
Phase Sense Control for Phase Detector with Internal Pull-up: When pulled LOW,  
C
the polarity of the Phase Detector is reversed.  
BISW  
16  
17  
18  
19  
O
O
O
I
Analog Switch Output: Connects to output of charge pump when LE is HIGH.  
Monitor Point for Phase Detector Input  
F
OUT  
P
External Charge Pump Output: Open drain N-Channel FET, pull-up resistor required.  
PWDN  
Power Down Pin with Internal Pull-up: When pin is HIGH, device is in normal state.  
When pin is LOW, device is in power-down mode. When device enters power-down  
mode the charge pump is in the three-state condition.  
20  
O
External Change Pump: (CMOS logic output).  
R
3
CYW2320  
only. Operation of the device at these or any other conditions  
above those specified in the operating sections of this specifi-  
cation is not implied. Maximum conditions for extended peri-  
ods may affect reliability.  
Absolute Maximum Ratings  
Stresses greater than those listed in this table may cause per-  
manent damage to the device. These represent a stress rating  
Parameter  
or V  
Description  
Power Supply Voltage  
Rating  
Unit  
V
V
–0.5 to +6.5  
CC  
P
V
Output Voltage  
–0.5 to V +0.5  
V
OUT  
OUT  
CC  
I
Output Current  
±15  
+260  
mA  
°C  
°C  
T
T
Lead Temperature  
Storage Temperature  
L
–55 to +150  
STG  
Always turn off power before adding or removing devices from  
system.  
Handling Precautions  
Devices should be transported and stored in antistatic con-  
tainers.  
Protect leads with a conductive sheet when handling or trans-  
porting PC boards with devices.  
These devices are static sensitive. Ensure that equipment and  
personnel contacting the devices are properly grounded.  
If devices are removed from the moisture protective bags for  
more than 36 hours, they should be baked at 85°C in a mois-  
ture free environment for 24 hours prior to assembly in less  
than 24 hours.  
Cover workbenches with grounded conductive mats.  
Recommended Operating Conditions  
Parameter  
Description  
Power Supply Voltage  
Test Condition  
Rating  
Unit  
V
V
2.7 to 5.5  
CC  
P
V
Charge Pump Voltage  
Operating Temperature  
V
to +5.5  
V
CC  
T
Ambient air at 0 CFM flow  
–40 to +85  
°C  
A
4
CYW2320  
Electrical Characteristics: V = 3.0V, V = 3.0V, T = –40°C to +85°C, Unless otherwise specified  
CC  
P
A
Parameter  
Description  
Power Supply Current  
Power-down Current  
Test Condition  
Pin  
Min.  
Typ.  
Max.  
Unit  
mA  
I
V
V
7
6
CC  
PD  
CC  
µA  
I
Power-down, V = 3.0V  
100  
CC  
CC  
IN  
F
Maximum Operating  
Frequency  
F
2.0  
GHz  
IN  
F
Oscillator Input Frequency No load on OSC_OUT  
OSC_IN  
60  
25  
4
MHz  
MHz  
dBm  
dBm  
OSC  
PF  
Input Sensitivity  
V
V
= 2.7V  
= 5.5V  
F
IN  
–15  
–10  
0.5  
IN  
CC  
CC  
4
V
Oscillator Input Sensitivity  
Oscillator Input Current  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
High Level Output Voltage  
Low Level Output Voltage  
OSC_IN  
V
P–P  
OSC  
I , I  
–100  
100  
µA  
V
IH IL  
V
= 5.0V  
V
DATA,  
CLOCK,  
LE  
V
* 0.8  
CC  
CC  
IH  
IL  
V
V
* 0.3  
V
CC  
µA  
µA  
V
I
I
–10  
–10  
2.2  
1
1
10  
IH  
IL  
10  
V
F /LD  
O
OH  
V
0.4  
V
OL  
ID  
ID , Source Current  
V = 3.0V, VD = V /2  
D
D
–3.2  
–3.8  
mA  
mA  
O(SO)  
OH(SI)  
O
P
O
P
O
O
V = 5.0V, VD = V /2  
P
O
P
ID  
ID High, Sink Current  
V = 3.0V, VD = V /2  
3.2  
3.8  
mA  
mA  
O
P
O
P
V = 5.0V, VD = V /2  
P
O
P
∆ID  
ID Charge Pump Sink and VD = V /2  
5
%
O
O
O
P
Source Mismatch  
[IID  
I – IID  
I]/  
O(SI)  
O(SO)  
[1/2*{IID  
]I+IID  
I}]*100%  
O(SI)  
O(SO)  
[1]  
%
ID vs T  
Charge Pump Current  
–40°C<T<85°C, V = V /2  
5
O
DO  
P
Variation vs. Temperature  
nA  
ID  
Charge Pump High-  
Impedance Leakage  
Current  
±2.5  
O-tri  
Note:  
1. IDOVS T; Charge pump current variation vs. temperature.  
[IIDO(SI)@TI – IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and  
[IIDO(SO)@TI – IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.  
5
CYW2320  
Timing Waveforms  
Phase Characteristics  
For normal operation, the FC pin is used to select the output polarity of the  
phase detector. Both the internal and any external charge pump are affected.  
(1)  
Depending upon VCO characteristics, FC pin should be set accordingly:  
When VCO characteristics are like (1), FC should be set HIGH or OPEN  
CIRCUIT:  
VCO  
Output  
Frequency  
When VCO characteristics are like (2), FC should be set LOW.  
When FC is set HIGH or OPEN CIRCUIT, F pin is set to the reference  
out  
divider output, F . When FC is set LOW, F pin is set to the programmable  
r
out  
divider output F .  
p
(2)  
VCO Input Voltage  
Phase Comparator Sense  
Phase Detector Output Waveform  
FR  
FP  
tw  
tw  
LD  
D
Charge Pump Output Current Waveform  
O
FR  
FP  
tw  
tw  
Do  
IDO  
Three-state  
6
CYW2320  
Timing Waveforms (continued)  
Serial Data Input Timing Waveform  
[2, 3, 4, 5]  
//  
//  
//  
//  
B11 = MSB  
B10  
B1  
A7  
A1  
CNT = LSB  
DATA  
CLOCK  
//  
//  
//  
t3  
t4  
t5  
t1  
t2  
LE  
//  
Serial Data Input  
Data is input serially using the DATA, CLOCK, and LE pins.  
Two control bits direct data into the locations given in Table 1.  
Table 1. Control Configuration  
CNT  
Function  
1
0
Reference Counter: R = 3 to 16383, set prescaler ratio PRE =0:128/129, PRE=1:64/65  
Program Counter: A = 0 to 127, B = 3 to 2047  
[6]  
Table 2. Shift Register Configuration  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Reference Counter and Configuration Bits  
CNT R1  
R2  
R3  
R4  
R5  
R6  
R7  
R8  
R9 R10 R11 R12 R13 R14 PRE  
Programmable Counter Bits  
CNT A1  
A2  
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9 B10 B11  
Bit(s) Name  
CNT  
Function  
Control Bit: Directs programming data to reference or programmable counters.  
[7]  
R1–R14  
PRE  
Reference Counter Setting Bits: 14 bits, R = 3 to 16383.  
Prescaler Divide Bit: LOW = 128/129 and HIGH = 64/65.  
Swallow Counter Divide Ratio: A = 0 to 127.  
A1–A7  
B1–B11  
Notes:  
[7]  
Programmable Counter Divide Ratio: B = 3 to 2047.  
2. t1–t5 = 50 µs > t > 0.5 µs.  
3. CLOCK may remain HIGH after latching in data.  
4. DATA is shifted in with the MSB first.  
5. For DATA definitions, refer to Table 2.  
6. The MSB is loaded in first.  
7. Low count ratios may violate frequency limits of the phase detector.  
7
CYW2320  
[8]  
Table 3. 7-Bit Swallow Counter (A) Truth Table  
Divide Ratio A  
A7  
0
A6  
0
A5  
0
A4  
0
A3  
0
A2  
0
A1  
0
0
1
0
0
0
0
0
0
1
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
126  
127  
1
1
1
1
1
1
1
[9]  
Table 4. 11-Bit Programmable Counter (B) Truth Table  
Divide Ratio B  
B11  
0
B10  
0
B9  
0
B8  
0
B7  
0
B6  
0
B5  
0
B4  
0
B3  
B2  
1
B1  
1
3
4
0
1
0
0
0
0
0
0
0
0
0
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
2046  
2047  
1
1
1
1
1
1
1
1
1
1
1
[9]  
Table 5. 14-Bit Programmable Reference Counter Truth Table  
Divide Ratio R  
R14  
0
R13  
0
R12  
0
R11  
0
R10  
0
R9  
0
R8  
0
R7  
0
R6  
R5  
0
R4  
0
R3  
0
R2  
1
R1  
3
4
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
:::  
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
1
:::  
0
16382  
16383  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[10]  
Package  
Ordering Code  
CYW2320  
Name  
Package Type  
TR  
ZI  
20-pin TSSOP (0.173” wide) Tape and Reel Option  
Notes:  
8. B is greater than or equal to A.  
9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:  
fvco = {(P * B) + A} * fosc / R where (A < B)  
fvco: Output frequency of the external VCO.  
fosc: The crystal reference oscillator frequency.  
A: Preset divide ratio of the 7-bit swallow counter.  
B: Preset ratio of the 11-bit programmable counter (3 to 2047).  
P: Preset divide ratio of the dual modulus prescaler.  
R: Preset ratio of the 15-bit programmable reference counter (3 to 16383).  
The divide ratio N = (P * B) + A.  
10. Operating temperature range: –40°C to +85°C.  
Document #: 38-00917  
8
CYW2320  
Package Diagram  
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)  
Physical Dimensions In Millimeters  
20 Lead (0.173" Wide) TSSOP Package Order Number X  
20" clear antistatic tubes, 76 units/tube  
JEDEC Outline MO-153  
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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