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UZNBG3116Q20

型号：

UZNBG3116Q20

品牌：

DIODES[ DIODES INCORPORATED ]

页数：

15 页

PDF大小：

622 K

下载PDF手册
FET BIAS CONTROLLER WITH POLARISATION  
SWITCH AND TONE DETECTION  
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
DEVICE DESCRIPTION  
The ZNBG series of devices are designed to meet the  
bias requirements of GaAs and HEMT FETs  
commonly used in satellite receiver LNBs, PMR,  
cellular telephones etc. with a minimum of external  
components.  
Drain current setting of the ZNBG3115/16 is user  
selectable over the range 0 to 15mA, this is achieved  
with addition of a single resistor. The series also offers  
the choice of drain voltage to be set for the FETs, the  
3115 gives 2.2 volts drain whilst the 3116 gives 2 volts.  
With the addition of two capacitors and a resistor the  
devices provide drain voltage and current control for  
three external grounded source FETs, generating  
the regulated negative rail required for FET gate  
biasing whilst operating from a single supply. This  
negative bias, at -2.8 volts, can also be used to  
supply other external circuits.  
These devices are unconditionally stable over the full  
working temperature with the FETs in place, subject to  
the inclusion of the recommended gate and drain  
capacitors. These ensure RF stability and minimal  
injected noise.  
It is possible to use less than the devices full  
complement of FET bias controls, unused drain and gate  
connections can be left open circuit without affecting  
operation of the remaining bias circuits.  
The ZNBG3115/16 includes bias circuits to drive up  
to three external FETs. A control input to the device  
selects either one of two FETs as operational, the  
third FET is permanently active. This feature is  
normally used as an LNB polarisation switch. Also  
specific to Universal LNB applications is the 22kHz  
tone detection and logic output feature which is  
used to enable high and low band frequency  
switching.  
To protect the external FETs the circuits have been  
designed to ensure that, under any conditions including  
power up/down transients, the gate drive from the bias  
circuits cannot exceed the range -3.5V to 1V.  
Additionally each stage has its own individual current  
limiter. Furthermore if the negative rail experiences a  
fault condition, such as overload or short circuit, the  
drain supply to the FETs will shut down avoiding  
excessive current flow.  
The ZNBG3115/16 has been designed to cope with  
DiSEqC™ ready set top boxes and rejects all  
transients from channel switching.  
The ZNBG3115/16 are available in QSOP16 and QSOP20  
for the minimum in device size. Device operating  
temperature is -40 to 80°C to suit a wide range of  
environmental conditions.  
FEATURES  
APPLICATIONS  
Provides bias for GaAs and HEMT FETs  
Satellite receiver LNBs  
•
•
Drives up to three FETs  
Private mobile radio (PMR)  
•
•
Dynamic FET protection  
Cellular telephones  
•
•
Drain current set by external resistor  
•
Regulated negative rail generator requires only  
2 external capacitors  
•
Choice in drain voltage  
•
Wide supply voltage range  
•
Polarisation switch for LNBs  
•
22kHz tone detection for band switching  
•
Tone detector ignores unwanted signals  
•
Support fr MIMIC, FET and Bipolar local  
oscillator devices  
•
Compliant with ASTRA control specifications  
•
QSOP 16 and 20 surface mount packages  
•
1
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage  
Supply Current  
Input Voltage (VPOL  
-0.6V to 12V  
100mA  
25V Continuous  
0 to 15mA  
Power Dissipation (Tamb= 25°C)  
QSOP16  
QSOP20  
500mW  
500mW  
)
Drain Current (per FET)  
(set by RCAL  
)
Operating Temperature  
Storage Temperature  
-40 to 80°C  
-50 to 85°C  
ELECTRICAL CHARACTERISTICS. TEST CONDITIONS  
(Unless otherwise stated):Tamb= 25°C,V =5V,I =10mA (RCAL=33k )  
CC  
CONDITIONS  
D
LIMITS  
TYP. MAX.  
10  
SYMBOL PARAMETER  
UNITS  
V
MIN.  
5
VCC  
ICC  
Supply Voltage  
Supply Current  
ID1 = ID2 (or ID12) = ID3=0  
8.5  
28  
28  
18  
18  
15  
35  
35  
25  
25  
mA  
mA  
mA  
mA  
mA  
I
I
I
I
D1=0, ID2 (or ID12)=ID3=10mA, VPOL=14V  
D2=0,ID1 (or ID12)=ID3=10mA, VPOL=15.5V  
D1 and ID3=0, ILB=10mA  
D1 and ID3=0, IHB=10mA  
VSUB  
Substrate Voltage  
(Internally generated) ICSUB=0  
CSUB=-200µA  
-3.05  
180  
-2.8  
-2.55  
-2.4  
V
V
I
Output Noise  
Drain Voltage  
Gate Voltage  
END  
ENG  
CG=4.7nF, CD=10nF  
CG=4.7nF, CD=10nF  
0.02  
0.005 Vpkpk  
Vpkpk  
fO  
Oscillator Frequency  
330  
800 kHz  
2
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
LIMITS  
SYMBOL PARAMETER  
CONDITIONS  
UNITS  
MIN.  
-30  
TYP. MAX.  
GATE CHARACTERISTICS  
IGO  
Output Current Range  
2000  
NA  
IDx  
(mA)  
VPOL  
(V)  
IGOx  
( A)  
Output Voltage  
VG1O  
VG1L  
VG1H  
Gate 1  
Off  
Low  
High  
I
I
I
D1=0 VPOL=14 IGO1=-10  
D1=12 VPOL=15.5 IGO1=-10  
D1=8 VPOL=15.5 IGO1=0  
-2.5  
-2.5  
0.4  
-2.25 -2.0  
-2.25 -2.0  
0.75 1.0  
V
V
V
Output Voltage  
VG2O  
VG2L  
VG2H  
Gate 2  
Off  
Low  
High  
I
I
I
D2=0 VPOL=15.5 IGO2=-10  
D2=12 VPOL=14 IGO2=-10  
D2=8 VPOL=14 IGO2=0  
-2.5  
-2.5  
0.4  
-2.25 -2.0  
-2.25 -2.0  
0.75 1.0  
V
V
V
Output Voltage  
VG3L  
VG3H  
Gate 3  
Low  
High  
I
I
D3=12  
D3=8  
IGO3=-10  
IGO3=0  
-3.0  
0.4  
-2.75 -2.5  
0.75 1.0  
V
V
DRAIN CHARACTERISTICS  
ID  
Current  
8
0
10  
12  
15  
mA  
mA  
IDrng  
Current range  
Set by Rcal  
Current Change  
with VCC  
VCC= 5 to 10V  
Tj=-40 to +80°C  
0.5  
0.05  
%/V  
%/°C  
DIDV  
DIDV  
with Tj  
Drain 1 Voltage: High  
ZNBG3115  
ZNBG3116  
VD1  
I
I
D1=10mA, VPOL=15.5V  
D1=10mA, VPOL=15.5V  
2.0  
1.8  
2.2  
2.0  
2.4  
2.2  
V
V
VD2  
Drain 2 Voltage: High  
ZNBG3115  
I
I
D2=10mA, VPOL=14V  
D2=10mA, VPOL=14V  
2.0  
1.8  
2.2  
2.0  
2.4  
2.2  
V
V
ZNBG3116  
VD3  
Drain 3 Voltage: High  
ZNBG3115  
I
I
D3=10mA, VPOL=15.5V  
D3=10mA, VPOL=15.5V  
2.0  
1.8  
2.2  
2.0  
2.4  
2.2  
V
V
ZNBG3116  
Voltage Change  
with VCC  
VCC= 5 to 10V  
Tj=-40 to +80°C  
0.5  
50  
%/V  
ppm  
⌬VDV  
⌬VDT  
with Tj  
Leakage Current  
Drain 1 †  
IL1  
IL2  
V
V
D1=0.5V, VPOL=14V  
D2=0.5V, VPOL=15.5V  
10  
10  
NA  
NA  
Drain 2 †  
†QSOP20 only  
3
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
LIMITS  
SYMBOL PARAMETER  
CONDITIONS  
UNITS  
MIN.  
1.75  
TYP. MAX.  
TONE DETECTION CHARACTERISTICS  
VOUT  
Filter Amplifier  
Bias Voltage 5  
Ifin=0  
1.95 2.15  
V
Finz  
AG  
FVT  
Input Impedance  
Amplifier Gain  
V Threshold5  
VFIN=100mV p/p  
150  
30  
Ω
V
FIN=100mV p/p  
V/mA  
mV p/p  
100  
170  
350  
Output Stage  
OV Volt. Range 6  
VLOV  
ILOV  
IL=50mA(LB or HB)  
VLOV=0  
-0.5  
VCC-1.8 V  
L
LOV Bias Current  
LB Output Low  
0.02  
0.15 1.0  
µA  
VLBL  
VLOV=0 IL=0  
Rlb-Csub=1MΩ  
Enabled 6  
Enabled 6  
-3.05  
-0.01  
-2.80 -2.55  
V
V
V
LOV=3V IL=0mA  
0
0.1  
Rlb-Csub=1MΩ  
VLBH  
VHBL  
LB Output High  
HB Output Low  
VLOV=0 IL=10mA  
VLOV=3V IL=50mA  
Disabled 6  
Disabled 6  
Disabled 6  
-0.025  
2.9  
0
3.0  
0.025  
3.1  
V
V
VLOV=0 IL=0  
-3.05  
-2.80 -2.55  
V
Rhb-Csub=1MΩ  
V
LOV=3V IL=0  
Disabled6  
V
V
-0.01  
0
0.1  
Rhb-Gnd=1MΩ  
VHBH  
HB Output High  
VLOV=0 IL=10mA  
VLOV=3V IL=50mA  
Enabled 6  
Enabled 6  
-0.025  
2.9  
0
3.0  
0.025  
3.1  
V
V
POLARITY SWITCH CHARACTERISTICS  
IPOL  
Input Current  
10  
14  
25  
40  
VPOL=25V (Applied via RPOL=2kΩ)  
VPOL=25V (Applied via RPOL=2kΩ)  
VPOL=25V (Applied via RPOL=2kΩ)  
µA  
V
VTPOL  
TSPOL  
NOTES:  
Threshold Voltage  
Switching Speed  
14.75 15.5  
100  
ms  
1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB, of 47nF are required for this  
purpose.  
2. The characteristics are measured using an external reference resistor RCAL of value 33k wired from pins RCAL to ground.  
3. Noise voltage is not measured in production.  
4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all outputs. CG, 4.7nF, are connected between gate outputs and  
ground, CD, 10nF, are connected between drain outputs and ground.  
5 . These parameters are linearly related to VCC  
6. These parameters are measured using Test Circuit 1  
4
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
TEST CIRCUIT 1  
Note: Same circuit used for QSOP16 option but with adjusted pinout.  
5
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
6
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
FUNCTIONAL DIAGRAM  
FUNCTIONAL DESCRIPTION  
The ZNBG devices provide all the bias requirements for external FETs, including the generation of the negative  
supply required for gate biasing, from the single supply voltage.The diagram above shows a single stage from  
the ZNBG series. The ZNBG3115/16 contains 3 such stages. The negative rail generator is common to both  
devices.  
The drain voltage of the external FET QN is set by the ZNBG device to its normal operating voltage. This is  
determined by the on board VD Set reference, for the ZNBG3115 this is nominally 2.2 volts whilst the ZNBG3116  
provides nominally 2 volts.  
The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gate  
of the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an  
external resistor RCAL  
.
Since the FET is a depletion mode transistor, it is often necessary to drive its gate negative with respect to ground  
to obtain the required drain current. To provide this capability powered from a single positive supply, the device  
includes a low current negative supply generator. This generator uses an internal oscillator and two external  
capacitors, CNB and CSUB  
.
7
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
The following schematic shows the function of the VPOL input. Only one of the two external FETs numberd Q1 and  
Q2 are powered at any one time, their selection is controlled by the input VPOL. This input is designed to be wired  
to the power input of the LNB via a high value (10k) resistor. With the input voltage of the LNB set at or below 14V,  
FET Q2 will be enabled. With the input voltage at or above 15.5V, FET Q1 will be enabled. The disabled FET has its  
gate driven low and its drain terminal is switched open circuit. It is permissible to connect the drain pins D1 and  
D2 together if required by the application circuit; this is done internally in the QSOP16 version. FET number Q3 is  
always active regardless of the voltage applied to VPOL  
.
QSOP 20 Version  
Control Input Switch Function  
Input Sense Polarisation Select  
Vertical  
FET Q2  
FET Q1  
≤ 14 volts  
Horizontal  
≥ 15.5 volts  
8
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
For many LNB applications, tone detection for band switching is required. The ZNBG3115/16 includes all the  
circuitry necessary to detect the presence of a 22kHz tone modulated on the supply input to the LNB. The main  
elements of the detector are an op-amp, a rectifier/smoother and a comparitor. The op-amp has a pre-set internal  
feedback resistor so that just a simple RC network wired to the input gives user defined gain and low frequency  
cut filter characteristics. The RC network components also serve two other purposes. The resistor provides  
overvoltage protection for the Vpol pin and the capacitor minimises tone interference of the Vpol threshold. The  
upper frequency roll-off of the op-amp has been set internally at above 100kHz to allow the amplifier to be used  
with other common tone switch frequencies.  
The rectifier/smoother/comparitor function is provided by a complex propriety circuit that allows the  
ZNBG3115/16 to reliably detect wanted tones whilst ignoring low frequency square wave switch box signals,  
DiSEqC™ bursts and supply switching transients common when using DiSEqC-2™ ready set-top boxes. This is  
all achieved without the need for any further external components. The threshold of the comparitor is supply  
dependent, hence the gain of the preceding op-amp must be adjusted in line with supply voltage. See the table  
below for recommended values for 22kHz detection, given for a range of supplies.  
Table_1  
Filter  
Supply Voltage (Vcc)  
Components  
5V  
6V  
7V  
8V  
9V  
10V  
Cf  
4.7nF  
2k  
4.7nF  
1.8k  
4.7nF  
1.5k  
10nF  
1.3k  
10nF  
1.1k  
10nF  
1.0k  
Rvpol (R2)  
Note: Optimised for F(tone) = 22kHz.  
9
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
APPLICATIONS CIRCUIT  
The diagrams below show partial application circuits for the ZNBG series showing all external components  
required for appropriate biasing. The bias circuits are unconditionally stable over the full temperature range with  
the associated FETs and gate and drain capacitors in circuit.  
To minimise board space the ZNBG3115/3116 is offered in a QSOP16 package. To reduce the pin count Drain 1  
and Drain 2 have been internally connected. This is possible because only one of the two bias stages can biased at  
one time.The QSOP16 offers a 40% reduction in size over the QSOP20 version.  
Capacitors C2 and C4 ensure that residual power supply and substrate generator noise is not allowed to affect  
other external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF  
feedthrough between stages via the ZNBG device. These capacitors are required for all stages used. Values of  
10nF and 4.7nF respectively are  
recommended however this is design  
dependent and any value between 1nF  
and 100nF could be used.  
The capacitors CNB and CSUB are an  
integral part of the ZNBGs negative  
supply generator. The negative bias  
voltage is generated on-chip using an  
internal oscillator. The required value  
of capacitors CNB and CSUB is 47nF.  
This generator produces a low current  
supply of approximately -3 volts.  
Although this generator is intended  
purely to bias the external FETs, it can  
be used to power other external  
circuits via the CSUB pin.  
Resistor RCAL sets the drain current at  
which all external FETs are operated. If  
any bias control circuit is not required,  
its related drain and gate connections  
may be left open circuit without  
affecting the operation of the  
remaining bias circuits.  
QSOP16 Applications circuit  
The ZNBG devices have been  
designed to protect the external FETs  
from adverse operating conditions.  
With a JFET connected to any bias  
circuit, the gate output voltage of the  
bias circuit can not exceed the range  
-3.0V to 1V under any conditions,  
including powerup and powerdown  
transients. All the bias stages include  
drain currents limits which work  
independently in each stage. Should  
the negative bias generator be shorted  
or overloaded so that the drain current  
of the external FETs can no longer be  
controlled, the drain supply to FETs is  
shut down to avoid damage to the  
FETs by excessive drain current.  
QSOP20 Applications circuit  
10  
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
APPLICATIONS INFORMATION(cont)  
The following block diagram shows the main section of an LNB designed for use with the Astra series of satellites.  
The ZNBG3115/16 is the core bias and control element of this circuit. The ZNBG provides the negative rail, FET  
bias control, polarisation switch control, tone detection and band switching with the minimum of external  
components. Compared to other discrete component solutions the ZNBG circuit reduces component count and  
overall size required.  
Single Universal LNB Block Diagram  
Regulator  
ZNBG3115/16  
Tone detection and band switching is provided on the ZNBG3115/16 devices. The following diagrams describes  
how this feature operates in an LNB and the external components required. The presence or absence of a 22kHz  
tone applied to pin FIN enables one of two outputs, LB and HB. A tone present enables HB and tone absent enables  
LB. The LB and HB outputs are designed to be compatible with both MMIC and discrete (bipolar or FET) local  
oscillator applications, selected by pin LOV. Referring to Figure 1 wiring pin LOV to ground will force LB and HB to  
switch between -2.6V (disabled) and 0V (enabled). Referring to Figures 2 and 3 wiring pin LOV to a positive voltage  
source (e.g. a potential divider across VCC and ground set to the required oscillator supply voltage, VOSC) will  
force the LB and HB outputs to provide the required oscillator supply, VOSC, when enabled and 0V when disabled.  
Tone Detection Function  
LOV  
FIN  
LB  
HB  
LB  
HB  
GND  
22kHz  
—
Disabled  
Enabled  
Disabled  
Enabled  
Enabled  
Disabled  
Enabled  
Disabled  
-3 volts  
GND  
GND  
-3 volts  
VOSC  
Note 1  
VOSC  
22kHz  
—
Note 1  
VOSC  
Note 1: 0 volts in typical LNB applications but ependent on extenal circuits.  
11  
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
APPLICATIONS Local Oscillator Circuits  
Figure 1  
Figure 2  
Figure 3  
12  
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
CONNECTION DIAGRAM  
QSOP20  
QSOP16  
1
2
1
2
16  
15  
20  
19  
G1  
D12  
G2  
V
G1  
D1  
G2  
D2  
G3  
D3  
V
CC  
CC  
Rcal  
Vpol  
Fin  
R
CAL  
POL  
IN  
3
4
5
6
14  
13  
12  
11  
3
4
5
6
18  
17  
16  
15  
V
G3  
D3  
F
Lov  
HB  
N/C  
N/C  
Lov  
Gnd  
Cnb1  
Cnb2  
7
8
10  
9
LB  
7
14  
13  
G
ND  
Csub  
8
C
C
H
NB1  
B
9
12  
11  
L
B
NB2  
10  
N/C  
C
SUB  
Part Number  
Package  
QSOP16  
QSOP16  
QSOP20  
QSOP20  
Part Mark  
ZNBG3115Q16  
ZNBG3116Q16  
ZNBG3115Q20  
ZNBG3116Q20  
ZNBG3115  
ZNBG3116  
ZNBG3115  
ZNBG3116  
13  
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
QSOP20  
QSOP16  
DIM  
Millimetres  
Inches  
MIN  
DIM  
Millimetres  
Inches  
MIN  
MIN  
8.55  
0.635  
1.47 REF  
0.20  
3.81  
1.35  
0.10  
5.79  
0°  
MAX  
MAX  
0.344  
MIN  
4.80  
0.635  
0.23 REF  
0.20  
3.81  
1.35  
0.10  
5.79  
0°  
MAX  
MAX  
0.196  
A
B
C
D
E
F
8.74  
0.337  
A
B
C
D
E
F
4.98  
0.189  
0.025 NOM  
0.058 REF  
0.025 NOM  
0.009 REF  
0.30  
3.99  
1.75  
0.25  
6.20  
8°  
0.008  
0.15  
0.012  
0.30  
3.99  
1.75  
0.25  
6.20  
8°  
0.008  
0.15  
0.012  
0.157  
0.069  
0.01  
0.244  
8°  
0.157  
0.069  
0.01  
0.244  
8°  
0.053  
0.004  
0.228  
0°  
0.053  
0.004  
0.228  
0°  
G
J
G
J
K
K
Conforms to JEDEC MO-137AD Iss A  
Conforms to JEDEC MO-137AB Iss A  
14  
ISSUE 2 - JUNE 2006  
ZNBG3115  
ZNBG3116  
© Zetex Semiconductors plc 2006  
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United Kingdom  
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Hauppauge, NY 11788  
USA  
3701-04 Metroplaza Tower 1  
Hing Fong Road, Kwai Fong  
Hong Kong  
Telefon: (49) 89 45 49 49 0  
Fax: (49) 89 45 49 49 49  
europe.sales@zetex.com  
Telephone: (1) 631 360 2222  
Fax: (1) 631 360 8222  
usa.sales@zetex.com  
Telephone: (852) 26100 611  
Fax: (852) 24250 494  
asia.sales@zetex.com  
Telephone (44) 161 622 4444  
Fax: (44) 161 622 4446  
hq@zetex.com  
These offices are supported by agents and distributors in major countries world-wide.  
This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced  
for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company  
reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service.  
For the latest product information, log on to www.zetex.com  
ISSUE 2 - JUNE 2006  
7
厂商 型号 描述 页数 下载

ZETEX

 		UZNBG2000X10 [ Analog Circuit, 1 Func, PDSO10, MSOP-10 ] 7 页

ZETEX

 		UZNBG2001X10 [ Analog Circuit, 1 Func, PDSO10, MSOP-10 ] 7 页

ZETEX

 		UZNBG3000Q16 [ Analog Circuit, 1 Func, PDSO16, QSOP-16 ] 9 页

ZETEX

 		UZNBG3001Q16 [ Analog Circuit, 1 Func, PDSO16, QSOP-16 ] 9 页

DIODES

 		UZNBG3110Q20 [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 15 页

ZETEX

 		UZNBG3110Q20TA [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 14 页

ZETEX

 		UZNBG3110Q20TC [ 暂无描述 ] 14 页

DIODES

 		UZNBG3111Q20 [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 15 页

ZETEX

 		UZNBG3111Q20TA [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 14 页

ZETEX

 		UZNBG3111Q20TC [ Analog Circuit, 1 Func, PDSO20, QSOP-20 ] 14 页

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