CYW2325
Pin Definitions
Pin
No.
(TSSOP)
Pin
No.
(MLF)
Pin
Type
Pin Name
Pin Description
OSC_IN
1
18
I
Oscillator Input: This input has a VCC/2 threshold and CMOS logic level
sensitivity.
OSC_OUT
VP
3
4
5
20
1
O
P
P
Oscillator Output
Charge Pump Rail Voltage: This supply for charge pump. Must be > VCC
.
VCC
2
Power Supply Connection for PLL: When power is removed from VCC
all latched data is lost.
DO
6
3
O
Charge Pump Output: The phase detector gain is IP/2π. Sense polarity
can be reversed by setting FC LOW (pin 15).
GND
LD
7
8
4
5
G
O
Analog and Digital Ground Connection: This pin must be grounded.
Lock Detect Pin: This output is HIGH with narrow LOW pulses when the
loop is locked.
FIN
10
11
7
8
I
I
Input to Prescaler: Maximum frequency 2.5 GHz.
CLOCK
Data Clock Input: One bit of data is loaded into the Shift Register on the
rising edge of this signal.
DATA
LE
13
14
10
11
I
I
Serial Data Input
Load Enable: On the rising edge of this signal, the data stored in the Shift
Register is latched into the counters and configuration controls.
FC
15
16
12
13
I
Phase Sense Control for Phase Detector with Internal Pull-up: When
pulled LOW, the polarity of the Phase Detector is reversed.
BISW
O
Analog Switch Output: Connects to output of charge pump when LE is
HIGH.
FOUT
17
18
14
15
O
O
Monitor Point for Phase Detector Input
External Charge Pump Output: Open drain N-Channel FET, pull-up re-
P
sistor required.
PWDN
19
16
I
Power-Down Pin with Internal Pull-up: When pin is HIGH, device is in
normal state. When pin is LOW, device is in power-down mode. When
device enters power-down mode the charge pump is in the High-Imped-
ance condition.
20
17
O
External Change Pump: (CMOS logic output).
R
NC
2, 9, 12
6, 9, 19
No Connect
Document #: 38-07406 Rev. **
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