CYW20736A1KWBGT,PDF,CYW20736A1KWBGT PDF资料,Datasheet,下载CYW20736A1KWBGT技术资料

CYW20736

Single-Chip Bluetooth Low Energy-Only

System-On-ChipwithSupportforWirelessCharging

The Cypress CYW20736 is a an advanced Bluetooth Low Energy (aka Bluetooth Smart) SoC that supports wireless charging. The

CYW20736 is designed to support the entire spectrum of Bluetooth Smart use cases for the medical, home automation, accessory,

sensor, Internet Of Things, and wearable market segments.

The CYW20736 radio has been designed to provide low power, low cost, and robust communications for applications operating in the

globally available 2.4 GHz unlicensed Industrial, Scientific, and Medical (ISM) band.

The single-chip Bluetooth low energy SoC is a monolithic component implemented in a standard digital CMOS process and requires

minimal external components to make a fully compliant Bluetooth device. The CYW20736 is available in a 32-pin,

5 mm × 5 mm 32-QFN package as well as WLCSP and die packages.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

BCM20736

CYW20736

BCM20736A1KML2G

BCM20736A1KWBGT

CYW20736A1KML2G

CYW20736A1KWBGT

Features

Applications

The following profiles are supported¹in ROM:

■ Alliance for Wireless Power (A4WP) wireless charging

■ Bluetooth Low Energy (BLE)-compliant

■ Infrared modulator

■ Battery status

■ Blood pressure monitor

■ Find me

■ IR learning

■ Supports Adaptive Frequency Hopping

■ Excellent receiver sensitivity

■ Heart rate monitor

■ Proximity

■ 10-bit auxiliary ADC with nine analog channels

■ Thermometer

■ Weight scale

■ Time

■ On-chip support for serial peripheral interface (master and

slave modes)

■ Broadcom Serial Communications interface (compatible with

Additional profiles that can be supported¹from RAM include:

NXP I²C slaves)

■ Blood glucose monitor

■ Temperature alarm

■ Location

■ Programmable output power control

■ Integrated ARM Cortex-M3 based microprocessor core

■ Automation Profile

■ Support for secure OTA

■ On-chip power-on reset (POR)

■ Support for EEPROM and serial flash interfaces

■ Integrated low-dropout regulator (LDO)

■ On-chip software controlled power management unit

■ Package type:

❐ 32-pin 32-QFN package (5 mm × 5 mm)

❐ 80-pin WLCSP package (2104 µm × 2085 µm)

■ RoHS compliant

1. Full qualification and use of these profiles may require FW updates from Cypress. Some of these profiles are under development/approval at the Cypress SIG and

conformity with the final approved version is pending. Contact your supplier for updates and the latest list of profiles.

Cypress Semiconductor Corporation

Document Number: 002-14883 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 30, 2016

CYW20736

Figure 1. Functional Block Diagram

Muxed on GPIO

Tx RTS_N

1.2V

UART_TXD

UART_RXD

SDA/

SCL/

Rx

CTS_N

VDD_CORE

1.2V

SCK

MOSI

MISO

1.2V VDD_CORE

Domain

WDT

28 ADC

Inputs

VSS,

VDDO,

VDDC

BSC/SPI

Master

Interface

(BSC is I²C -

compaƟble)

1.2V

POR

Test

UART

Periph 320K

UART ROM

Processing

Unit

(ARM -CM3)

60K

RAM

CT ɇ ѐ

ADC

1.2V

LDO

1.425V to 3.6V

1.62V to 3.6V

3.6V

System Bus

MIA POR

32 kHz

LPCLK

Peripheral

Interface

Block

I/O Ring

Control

Registers

Volt. Trans

hclk

VDD_IO

Domain

(24 MHz to 1 MHz)

RF Control

and Data

I/O Ring Bus

Bluetooth

2.4 GHz

Radio

Baseband

Core

GPIO

Control/

Status

IR

Mod.

and

SPI

PMU

24

MHz

M/S

Learning

Registers

Power

RF I/O

T/R

Switch

Frequency

Synthesizer

32 kHz

LPCLK

WAKE

128 kHz

LPO

High Current

Driver Controls

IR

I/O

14 GPIOs

AutoCal

128 kHz

LPCLK

1.2V VDD_RF

Domain

9 ADC

Inputs

÷ 4

PWM

24 MHz

Ref Xtal

32 kHzꢀyƚĂůꢀ;ŽƉƟŽŶĂůͿꢀ

1.62V to 3.6V

VDD_IO

IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website

(http://community.cypress.com/).

Document Number: 002-14883 Rev. *G

Page 2 of 49

CYW20736

Contents

1. Functional Description .................................................4

1.1 Bluetooth Baseband Core .....................................4

1.2 Infrared Modulator .................................................6

1.3 Infrared Learning ...................................................6

1.4 Wireless Charging .................................................7

1.5 ADC Port ...............................................................7

1.6 Serial Peripheral Interface .....................................8

1.7 Microprocessor Unit ..............................................9

1.8 Integrated Radio Transceiver ..............................10

1.9 Peripheral Transport Unit ....................................11

1.10 Clock Frequencies .............................................12

1.11 GPIO Port ..........................................................13

1.12 PWM ..................................................................14

1.13 Power Management Unit ...................................15

2. Pin Information ...........................................................16

2.1 Pin Descriptions ..................................................16

2.2 Pin Maps .............................................................20

2.3 WLCSP Pin List and Coordinates .......................22

3. GPIO Information ........................................................25

4. Specifications .............................................................34

4.1 Electrical Characteristics .....................................34

4.2 RF Specifications ................................................36

4.3 Timing and AC Characteristics ............................38

4.4 ESD Test Models ................................................41

5. Mechanical Information .............................................42

5.1 QFN .....................................................................42

5.2 WLCSP ................................................................45

6. Ordering Information ..................................................46

A. Appendix: Acronyms and Abbreviations ...............47

Document History ..........................................................48

Document Number: 002-14883 Rev. *G

Page 3 of 49

CYW20736

1. Functional Description

1.1 Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation.

The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, handles

data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into

baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it

independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and security

before sending over the air:

■ Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data dewhitening.

■ Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and data

whitening.

1.1.1 Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,

Bluetooth clock, and device address.

1.1.2 E0 Encryption

The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide

minimal processor intervention.

1.1.3 Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit

(LCU). This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or

configured by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state.

STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, and inquiry

scan.

1.1.4 Adaptive Frequency Hopping

The CYW20736 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map

selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency hop

map.

Document Number: 002-14883 Rev. *G

Page 4 of 49

CYW20736

1.1.5 Bluetooth Low Energy Profiles

The CYW20736 supports Bluetooth low energy, including the following profiles that are supported¹in ROM:

■ Battery status

■ Blood pressure monitor

■ Find me

■ Heart rate monitor

■ Proximity

■ Thermometer

■ Weight scale

■ Time

■ Alliance for Wireless Power (A4WP) wireless charging

■ Automation profile

■ Support for secure OTA

The following additional profiles can be supported¹from RAM:

■ Blood glucose monitor

■ Temperature alarm

■ Location

■ Custom profile

1.1.6 Test Mode Support

The CYW20736 fully supports Bluetooth Test mode, as described in the Bluetooth low energy specification.

1. Full qualification and use of these profiles may require FW updates from Cypress. Some of these profiles are under development/approval at the Bluetooth SIG and

conformity with the final approved version is pending. Contact your supplier for updates and the latest list of profiles.

Document Number: 002-14883 Rev. *G

Page 5 of 49

CYW20736

1.2 Infrared Modulator

The CYW20736 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms.

For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from

firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.

If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20736 IR TX firmware driver

inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun (see

Figure 2).

Figure 2. Infrared TX

1.3 Infrared Learning

The CYW20736 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.

For modulated signals, the CYW20736 can detect carrier frequencies between 10 kHz–500 kHz and the duration that the signal is

present or absent. The CYW20736 firmware driver supports further analysis and compression of learned signal. The learned signal

can then be played back through the CYW20736 IR TX subsystem (see Figure 3).

Figure 3. Infrared RX

Document Number: 002-14883 Rev. *G

Page 6 of 49

CYW20736

1.4 Wireless Charging

The CYW20736 includes support for wireless charging in hardware, software, and firmware. It supports the protocol for implementing

wireless charging solutions based on the specifications written by the Alliance for Wireless Power (A4WP).

The A4WP protocol is embedded in the CYW20736. Hardware and firmware elements required for wireless charging are either

implemented in the CYW20736 or can be obtained through a Cypress technical support representative (see IoT Resources on page 4).

An end-to-end charging solution comprises of the following:

■ Power Transmitting Unit (PTU): The PTU transfers the power to the receiving unit. The receiving unit is any device (phone, wearable,

or other embedded device) that needs to be charged. The PTU is typically plugged into a power source such as a wall outlet. The

CYW20736 includes the peripherals needed to implement and drive a reference charging circuit and otherwise requires only a few

external components. PTU reference designs based on the CYW20736, including bills of material (BOMs), are available through

Cypress technical support. Depending on charging power requirements, a Power Management Unit (PMU) such as the CYW8935X

may be included in the design. However, most PTUs requiring < 5W will not need a PMU. The references designs leverage ADCs,

PWMs, and other internal peripherals to help drive the charging circuitry for energy transfer as well as provide feedback for charging

control. The application and algorithm that drive the reference designs are available on request.

■ Power Receive Unit (PRU): The PRU receives energy from the PTU to charge the local device, and is typically embedded in the

local device. Like the PTU, a separate PMU may or may not be needed depending on power requirements. PRU reference designs

based on the CYW20736, both with and without a PMU, are also available through Cypress technical support.

1.5 ADC Port

The CYW20736 contains a 16-bit ADC (effective number of bits is 10).

Additionally:

■ There are 9 analog input channels in the 32-pin package

■ The following GPIOs can be used as ADC inputs:

❐ P0

❐ P1

❐ P8/P33 (select only one)

❐ P11

❐ P12

❐ P13/P28 (select only one)

❐ P14/P38 (select only one)

❐ P15

❐ P32

■ The conversion time is 10 μs.

■ There is a built-in reference with supply- or bandgap-based reference modes.

■ The maximum conversion rate is 187 kHz.

■ There is a rail-to-rail input swing.

The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes

the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input

multiplexers that select the ADC input signal V_inpand the ADC reference signals V_ref

.

The ADC input range is selectable by firmware control:

■ When an input range of 0–3.6V is used, the input impedance is 3 MΩ.

■ When an input range of 0–2.4V is used, the input impedance is 1.84 MΩ.

■ When an input range of 0–1.2V is used, the input impedance is 680 kΩ.

ADC modes are defined in Table 2.

Document Number: 002-14883 Rev. *G

Page 7 of 49

CYW20736

Table 2. ADC Modes

Mode

ENOB (Typical)

Maximum Sampling Rate (kHz)

Latency^a(μs)

0

1

2

3

4

13

12.6

12

5.859

11.7

171

85

21

11

5

46.875

93.75

187

11.5

10

a. Settling time after switching channels.

1.6 Serial Peripheral Interface

The CYW20736 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.

Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the

CYW20736 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Table 3,

Table 4, and Table 5. The CYW20736 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20736 can also

act as an SPI slave device that supports a 1.8V or 3.3V SPI master.

Table 3. CYW20736 First SPI Set (Master Mode)

Pin Name

SPI_CLK

SPI_MOSI

SPI_MISO

P24

SPI_CS^a

SCL

–

SDA

–

Configured Pin Name

–

P26

–

P32

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Table 4. CYW20736 Second SPI Set (Master Mode)

Pin Name

SPI_CLK

SPI_MOSI

P0

SPI_MISO

SPI_CS^a

P3

–

P1

P25

–

Configured Pin Name

P4

P24

P27

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Table 5. CYW20736 Second SPI Set (Slave Mode)

Pin Name

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS

P2

P3

–

P0

P27

P33

–

P1

–

Configured Pin Name

P24

–

P25

–

P26

P32

Document Number: 002-14883 Rev. *G

Page 8 of 49

CYW20736

1.7 Microprocessor Unit

The CYW20736 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer components.

The microprocessor is based on an ARM Cortex-M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units.

The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code. The SoC

has a total storage of 380 KB, including RAM and ROM.

The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications with

an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is executed

from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can

also support the integration of user applications.

1.7.1 EEPROM Interface

The CYW20736 provides a Broadcom Serial Control (BSC) master interface. BSC is programmed by the CPU to generate four types

of bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and fast mode

devices. BSC is compatible with an NXP I²C slave device, except that master arbitration (multiple I²C masters contending for the bus)

is not supported.

The EEPROM can contain customer application configuration information including application code, configuration data, patches,

pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.

Native support for the Microchip 24LC128, Microchip 24AA128, and ST Micro M24128-BR is included.

1.7.2 Serial Flash Interface

The CYW20736 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB

slave interface, transmit and receive FIFOs, and the SPI core PHY logic.

Devices natively supported include the following:

■ Atmel AT25BCM512B

■ MXIC MX25V512ZUI-20G

1.7.3 Internal Reset

Figure 4. Internal Reset Timing

VDDO POR delay

~ 2 ms

VDDO

VDDO POR threshold

VDDO POR

VDDC POR threshold

VDDC

VDDC POR delay

~ 2 ms

VDDC POR

Crystal

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and

firmware boot

Crystal Enable

Document Number: 002-14883 Rev. *G

Page 9 of 49

CYW20736

1.7.4 External Reset

The CYW20736 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external

active low reset signal, RESET_N, can be used to put the CYW20736 in the reset state. The RESET_N pin has an internal pull-up

resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the

VDDO supply voltage level has been stabilized.

Figure 5. External Reset Timing

Pulse width

>20 µs

RESET_N

Crystal

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and

firmware boot

Crystal Enable

1.8 Integrated Radio Transceiver

The CYW20736 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth wireless systems. It has been designed

to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed

ISM band. It is fully compliant with Bluetooth Radio Specification 4.0 and meets or exceeds the requirements to provide the highest

communication link quality of service.

1.8.1 Transmitter Path

The CYW20736 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes

any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

Power Amplifier

The CYW20736 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.

1.8.2 Receiver Path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation,

enables the CYW20736 to be used in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYW20736 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller

to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the

transmitter should increase or decrease its output power.

Document Number: 002-14883 Rev. *G

Page 10 of 49

CYW20736

1.8.3 Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The

CYW20736 uses an internal loop filter.

1.8.4 Calibration

The CYW20736 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during

normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and

amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and

temperature variations into account, and it takes place transparently during normal operation and hop setting times.

1.8.5 Internal LDO Regulator

The CYW20736 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO regulator

operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.

Note: Always place the decoupling capacitors near the pins as closely together as possible.

1.9 Peripheral Transport Unit

1.9.1 Broadcom Serial Communications Interface

The CYW20736 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external

EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse

devices. The BSC interface is compatible with I²C slave devices. The BSC does not support multimaster capability or flexible wait-

state insertion by either master or slave devices.

The following transfer clock rates are supported by the BSC:

■ 100 kHz

■ 400 kHz

■ 800 kHz (not a standard I²C-compatible speed.)

■ 1 MHz (Compatibility with high-speed I²C-compatible devices is not guaranteed.)

The following transfer types are supported by the BSC:

■ Read (Up to 16 bytes can be read.)

■ Write (Up to 16 bytes can be written.)

■ Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)

■ Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)

Hardware controls the transfers, requiring minimal firmware setup and supervision.

The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20736 are required on

both the SCL and SDA pins for proper operation.

1.9.2 UART Interface

The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 1.5 Mbps. The baud rate can

be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth 3.0 UART HCI (H5) specification. The

default baud rate for H5 is 115.2 kbaud.

Both high and low baud rates can be supported by running the UART clock at 24 MHz.

The CYW20736 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.

Document Number: 002-14883 Rev. *G

Page 11 of 49

CYW20736

1.10 Clock Frequencies

The CYW20736 is set with crystal frequency of 24 MHz.

1.10.1 Crystal Oscillator

The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load

capacitors in the range of 5 pF to 30 pF (see Figure 6) are required to work with the crystal oscillator. The selection of the load

capacitors is crystal-dependent. Table 6 shows the recommended crystal specifications.

Figure 6. Recommended Oscillator Configuration—12 pF Load Crystal

22 pF

XIN

Crystal

XOUT

20 pF

Table 6 shows the recommended crystal specifications.

Table 6. Reference Crystal Electrical Specifications

Parameter

Nominal frequency

Conditions

Minimum

Typical

Maximum

Unit

MHz

–

24.000

–

Oscillation mode

–

Fundamental

Frequency tolerance

Tolerance stability over temp

Equivalent series resistance

Load capacitance

@25°C

–

±10

–

ppm

Ω

@0°C to +70°C

–

60

–

12

–

pF

Operating temperature range

Storage temperature range

Drive level

0

+70

+125

200

±10

2

°C

–40

–

°C

–

μΩ

Aging

–

ppm/year

pF

Shunt capacitance

–

Peripheral Block

The peripheral blocks of the CYW20736 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the

request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.

The keyboard scanner is a special case, in that it may drop its clock request line even when enabled, and then reassert the clock

request line if a keypress is detected.

32 kHz Crystal Oscillator

Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Table 7 lists the oscillator’s characteristics. It is a

standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis was

added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit can be operated

with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are:

R1 = 10 MΩ, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.

Document Number: 002-14883 Rev. *G

Page 12 of 49

CYW20736

Figure 7. 32 kHz Oscillator Block Diagram

C2

32.768 kHz

R1

XTAL

C1

Table 7. XTAL Oscillator Characteristics

Parameter Symbol

Conditions

Minimum

Typical

32.768

100

Maximum

Unit

kHz

ppm

Output frequency F_oscout

–

Frequency

tolerance

–

Crystal dependent

Start-up time

T_startup

P_drv

–

0.5

–

500

–

ms

μΩ

kΩ

XTAL drive level

For crystal selection

XTAL series

resistance

70

R_series

C_shunt

For crystal selection

XTAL shunt

capacitance

–

1.3

pF

1.11 GPIO Port

The CYW20736 has 14 general-purpose I/Os (GPIOs) in the 32-pin package. All GPIOs support programmable pull-up and pull-down

resistors, and all support a 2 mA drive strength except P26, P27, and P28, which provide a 16 mA drive strength at 3.3V supply.

The following GPIOs are available:

■ P0–P4

■ P8/P33 (Dual bonded, only one of two is available.)

■ P11/P27 (Dual bonded, only one of two is available.)

■ P12/P26 (Dual bonded, only one of two is available.)

■ P13/P28 (Dual bonded, only one of two is available.)

■ P14/P38 (Dual bonded, only one of two is available.)

■ P15

■ P24

■ P25

■ P32

For a description of all GPIOs, see Table 11 on page 25.

Document Number: 002-14883 Rev. *G

Page 13 of 49

CYW20736

1.12 PWM

The CYW20736 has four internal PWM channels. The PWM module is described as follows:

■ PWM0–3

■ The following GPIOs can be mapped as PWMs:

❐ P26

❐ P27

❐ P14/P28 (Dual bonded, only one of two is available.)

❐ P13

■ Each of the PWM channels, PWM0–3, contains the following registers:

❐ 10-bit initial value register (read/write)

❐ 10-bit toggle register (read/write)

❐ 10-bit PWM counter value register (read)

■ The PWM configuration register is shared among PWM0–3 (read/write). This 12-bit register is used:

❐ To configure each PWM channel.

❐ To select the clock of each PWM channel.

❐ To change the phase of each PWM channel.

Figure 8 shows the structure of one PWM channel.

Figure 8. PWM Channel Block Diagram

pwm_cfg_adr register

pwm#_init_val_adr register

10

pwm#_togg_val_adr register

10

pwm#_cntr_adr

10

cntr value is CM3 readable

pwm_out

Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)

PWM cntr w/ pwm#_init_val = x (solid line)

10'H3FF

pwm_togg_val_adr

10'Hx

10'H000

pwm_out

Document Number: 002-14883 Rev. *G

Page 14 of 49

CYW20736

1.13 Power Management Unit

The Power Management Unit (PMU) provides power management features that can be invoked by software through power

management registers or packet-handling in the baseband core.

1.13.1 RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-

ceiver, which then processes the power-down functions accordingly.

1.13.2 Host Controller Power Management

Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the

disabling of the on-chip regulator when in deep sleep mode.

1.13.3 BBC Power Management

There are several low-power operations for the BBC:

■ Physical layer packet handling turns RF on and off dynamically within packet TX and RX.

■ Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYW20736 runs on the Low

Power Oscillator and wakes up after a predefined time period.

The CYW20736 automatically adjusts its power dissipation based on user activity. The following power modes are supported:

■ Active mode

■ Idle mode

■ Sleep mode

■ HIDOFF (Deep Sleep) mode

■ Timed Deep Sleep mode

The CYW20736 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered

when user activity resumes.

In HIDOFF (Deep Sleep) mode, the CYW20736 baseband and core are powered off by disabling power to LDOOUT. The VDDO

domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power

consumption and is intended for long periods of inactivity.

Document Number: 002-14883 Rev. *G

Page 15 of 49

CYW20736

2. Pin Information

2.1 Pin Descriptions

Table 8 provides pin descriptions for the QFN package.

Table 8. QFN Package Pin Descriptions

Pin Number

Pin Name

I/O

Power Domain

Radio I/O

Description

6

RF

I/O

VDD_RF

RF antenna port

RF Power Supplies

4

5

7

8

VDDIF

VDDFE

I

VDD_RF

Power Supplies

VDDC

IFPLL power supply

RF front-end supply

VCO, LOGEN supply

VDDVCO

VDDPLL

RFPLL and crystal oscillator supply

11

28

14

VDDC

VDDO

VDDM

I

Baseband core supply

I/O pad and core supply

I/O pad supply

VDDO

VDDM

Clock Generator and Crystal Interface

9

XTALI

I

VDD_RF

Crystal oscillator input. See page 12 for options.

Crystal oscillator output.

10

XTALO

O

Low-power oscillator (LPO) input is used.

Alternative Function:

1

XTALI32K

I

VDDO

■ P11

■ P27

Low-power oscillator (LPO) output.

Alternative Function:

32

XTALO32K

O

■ P12

■ P26

Core

Active-low system reset with open-drain output & internal

pull-up resistor

18

17

RESET_N

TMC

I/O PU

I

VDDO

Test mode control

High: test mode

Connect to GND if not used.

UART

UART serial input – Serial data input for the HCI UART

interface. Leave unconnected if not used.

Alternative function:

12

13

UART_RXD

UART_TXD

I

VDDM

■ GPIO3

UART serial output – Serial data output for the HCI UART

interface. Leave unconnected if not used.

Alternative Function:

O, PU

■ GPIO2

Document Number: 002-14883 Rev. *G

Page 16 of 49

CYW20736

Table 8. QFN Package Pin Descriptions (Cont.)

Pin Number

Pin Name

I/O

Power Domain

Description

BSC

Data signal for an external I²C device.

Alternative function:

■ SPI_1: MOSI (master only)

15

SDA

I/O, PU

VDDM

■ GPIO0

■ CTS

Clock signal for an external I²C device.

Alternative function:

■ SPI_1: SPI_CLK (master only)

16

SCL

I/O, PU

■ GPIO1

■ RTS

LDO Regulator Power Supplies

2

3

LDOIN

I

N/A

Battery input supply for the LDO

LDO output

LDOOUT

O

Table 9 provides pin descriptions for the WLCSP package. The table is ordered by pin name.

Table 9. WLCSP Package Pin Descriptions

Pin Numbers

Pin Name

AVSS

Type

Power Domain

AVSS

Description

57

I

Analog ground

RF front-end supply

Ground

69

FEVDD

FEVSS

IFVDD

FEVDD

VSS

70

67

IFVDD

VSS

IF PLL power supply

Ground

54, 68, 71, 72

IFVSS

76

79

PLLVDD

PLLVSS

PLLVDD

VSS

RF PLL and crystal oscillator supply

Ground

Document Number: 002-14883 Rev. *G

Page 17 of 49

CYW20736

Table 9. WLCSP Package Pin Descriptions (Cont.)

Pin Numbers

21

Pin Name

P0

Type

Power Domain

VDDO

Description

I

26

P1

22

P2

13

P3

31

P4

14

P5

27

P6

18

P7

36

P8

63

P9

53

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

P29

P30

P31

P32

P33

P34

P35

P36

P37

P38

P39

66

55

20

35

52

32

23

41

General purpose I/O

28

(See Table 12: “WLCSP Package GPIO Pin Descrip-

33

tions,” on page 28.)

43

15

48

47

19

30

25

49

44

50

39

38

46

34

29

62

64

24

51

Document Number: 002-14883 Rev. *G

Page 18 of 49

CYW20736

Table 9. WLCSP Package Pin Descriptions (Cont.)

Pin Numbers

Pin Name

Type

Power Domain

Description

73

RF

I/O

VDD_RF

RF antenna port

Active-low system reset with open-drain output & internal

pull-up resistor

16

RST_N

I/O PU

VDDO

Clock signal for an external I²C device.

Alternative function:

■ SPI_1: SPI_CLK (master only)

2

SCL

I/O, PU

VDDM

■ GPIO1

■ RTS

Data signal for an external I²C device.

Alternative function:

■ SPI_1: MOSI (master only)

7

SDA

I/O, PU

VDDM

■ GPIO0

■ CTS

Test mode control

High: test mode

Connect to GND if not used.

11

10

TMC

I

VDDO

VDDM

UART serial input – Serial data input for the HCI UART

interface. Leave unconnected if not used.

Alternative function:

UART_RXD

■ GPIO3

UARTserial output – Serial data output for the HCI UART

interface. Leave unconnected if not used.

Alternative Function:

9

UART_TXD

O, PU

VDDM

■ GPIO2

77, 80

VCOVDD

VCOVSS

VDDC

I

VCOVDD

N/A

VCO and LO generator supply

74

Ground

1, 4

I

VDDC

VDDM

VDDO

VREG

N/A

Baseband core supply

I/O pad supply

3

VDDM

VDDO

I

17, 37, 45, 58

I

I/O pad and core supply

Internal LDO regulator output

Internal LDO regulator input

Ground

65

60

VREG

O

I

VR3V

5, 6, 8

12, 40, 59

42

VSSC

I

N/A

VSSO

I

N/A

Ground

VSS0

I

N/A

Ground

75

XIN

I

VDD_RF

VDDO

Crystal oscillator input. See page 12 for options.

Crystal oscillator output.

Low-power oscillator (LPO) input is used.

Low-power oscillator (LPO) output.

78

XOUT

O

I

61

XTAL32KI

XTAL32KO

56

O

Document Number: 002-14883 Rev. *G

Page 19 of 49

CYW20736

2.2 Pin Maps

Figure 9 shows the ball map of the QFN package.

Figure 9. 32-Pin QFN Ball Map

32

31

30

29

28

27

26

25

P11/P27/XIN32

LDO_IN

LDO_OUT

VDDIF

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P8/P33

P4

P2

P3

VDDFE

P1

RF

P0

VDDVCO

VDDPLL

RST_N

TMC

9

10

11

12

13

14

15

16

Document Number: 002-14883 Rev. *G

Page 20 of 49

CYW20736

Figure 10 shows the bump map of the WLCSP package.

Figure 10. 80-Pin WLCSP Bump Map—Top View of Package with Bumps Facing Down

Document Number: 002-14883 Rev. *G

Page 21 of 49

CYW20736

2.3 WLCSP Pin List and Coordinates

Table 10 provides the WLCSP pin list and coordinates.

Table 10. WLCSP Pin List and Coordinates

Package Bottom View

(Bumps Facing Up)

Package Center (0,0)

Package Top View

(Bumps Facing Down)

Package Center (0,0)

Bump #

Net Name

X Coordinate

Y Coordinate

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

X Coordinate

Y Coordinate

877.2587

677.2587

477.2587

277.2587

77.2587

1

VDDC

SCL

–895.5

–695.5

–495.5

–295.5

–95.5

–895.5

–695.5

–495.5

–295.5

–95.5

2

3

VDDM

VDDC

VSSC

SDA

VSSC

UART_TXD

UART_RXD

TMC

VSSO

P3

4

5

6

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

877.2587

677.2587

477.2587

277.2587

77.2587

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

877.2587

677.2587

477.2587

277.2587

77.2587

P5

P22

RST_N

VDDO

P7

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

877.2587

677.2587

477.2587

277.2587

77.2587

P25

P13

P0

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

877.2587

677.2587

477.2587

277.2587

77.2587

P2

–95.5

P17

–95.5

P38

–95.5

P27

–95.5

P1

104.5

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

104.5

877.2587

677.2587

477.2587

277.2587

77.2587

P6

104.5

P19

104.5

P35

104.5

P26

104.5

P4

304.5

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

304.5

877.2587

677.2587

477.2587

277.2587

77.2587

P16

304.5

P20

304.5

P34

304.5

P14

304.5

Document Number: 002-14883 Rev. *G

Page 22 of 49

CYW20736

Table 10. WLCSP Pin List and Coordinates (Cont.)

Package Bottom View

(Bumps Facing Up)

Package Center (0,0)

Package Top View

(Bumps Facing Down)

Package Center (0,0)

Bump #

Net Name

X Coordinate

Y Coordinate

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

–877.2587

–677.2587

–477.2587

–277.2587

–77.2587

322.7413

422.7413

522.7413

922.7413

722.7413

122.7413

722.7413

122.7413

722.7413

122.7413

922.7413

722.7413

922.7413

722.7413

224.6363

X Coordinate

Y Coordinate

877.2587

677.2587

477.2587

277.2587

77.2587

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

P8

VDDO

P32

504.5

704.5

904.5

794

504.5

704.5

904.5

794

P31

VSSO

P18

877.2587

677.2587

477.2587

277.2587

77.2587

VSS0

P21

P29

VDDO

P33

877.2587

677.2587

477.2587

277.2587

77.2587

P24

P23

P28

P30

P39

–322.7413

–422.7413

–522.7413

–922.7413

–722.7413

–122.7413

–722.7413

–122.7413

–722.7413

–122.7413

–922.7413

–722.7413

–922.7413

–722.7413

–224.6363

P15

594

P10

394

IFVSS

P12

211.14

794

211.14

794

XTAL32KO

AVSS

VDDO

VSSO

VR3V

XTAL32KI

P36

594

394

794

594

394

794

P9

594

P37

594

VREG

P11

394

IFVDD

IFVSS

FEVDD

FEVSS

IFVSS

194

–6

–75.35

–275.35

–75.35

–275.35

Document Number: 002-14883 Rev. *G

Page 23 of 49

CYW20736

Table 10. WLCSP Pin List and Coordinates (Cont.)

Package Bottom View

(Bumps Facing Up)

Package Center (0,0)

Package Top View

(Bumps Facing Down)

Package Center (0,0)

Bump #

Net Name

X Coordinate

Y Coordinate

822.7413

927.0313

154.5313

354.5313

927.0313

154.5313

354.5313

927.0313

X Coordinate

Y Coordinate

–822.7413

–927.0313

–154.5313

–354.5313

–927.0313

–154.5313

–354.5313

–927.0313

73

74

75

76

77

78

79

80

RF

–330.025

–517.5

–330.025

–517.5

VCOVSS

XIN

–651.09

–717.5

–651.09

–717.5

PLLVDD

VCOVDD

XOUT

–851.09

–917.5

–851.09

–917.5

PLLVSS

VCOVDD

Document Number: 002-14883 Rev. *G

Page 24 of 49

CYW20736

3. GPIO Information

Table 11 provides the GPIO alternate function descriptions for the QFN package.

Table 11. QFN Package GPIO Pin Descriptions^a

Default

Direction

After

Power

Pin Number

Pin Name

Alternate Function Description

POR State Domain

■ GPIO: P0

■ A/D converter input

■ Peripheral UART: puart_tx

■ SPI_2: MOSI (master and slave)

■ IR_RX

Input

VDDO

floating

19

P0

Input

■ 60Hz_main

■ Not available during TMC=1

■ GPIO: P1

■ A/D converter input

■ Peripheral UART: puart_rts

■ SPI_2: MISO (master and slave)

■ IR_TX

Input

VDDO

floating

20

P1

Input

■ GPIO: P3

Input

VDDO

floating

21

22

P3

P2

Input

■ Peripheral UART: puart_cts

■ SPI_2: SPI_CLK (master and slave)

■ GPIO: P2

■ Peripheral UART: puart_rx

■ SPI_2: SPI_CS (slave only)

■ SPI_2: SPI_MOSI (master only)

■ GPIO: P4

Input

VDDO

floating

■ Peripheral UART: puart_rx

■ SPI_2: MOSI (master and slave)

■ IR_TX

Input

VDDO

floating

23

P4

P8

Input

■ GPIO: P8

Input

VDDO

floating

■ A/D converter input

■ External T/R switch control: ~tx_pd

■ GPIO: P33

24

■ A/D converter input

■ SPI_2: MOSI (slave only)

■ Auxiliary clock output: ACLK1

■ Peripheral UART: puart_rx

Input

VDDO

floating

P33

Input

Document Number: 002-14883 Rev. *G

Page 25 of 49

CYW20736

Table 11. QFN Package GPIO Pin Descriptions^a(Cont.)

Default

Direction

After

Power

Pin Number

Pin Name

Alternate Function Description

POR State Domain

■ GPIO: P11

Input

VDDO

floating

P11

Input

■ A/D converter input

■ XTALI32K

1

■ GPIO: P27

P27

PWM1

Input

VDDO

floating

■ SPI_2: MOSI (master and slave)

Current: 16 mA

■ GPIO: P12

Input

VDDO

floating

P12

■ A/D converter input

■ XTALO32K

■ GPIO: P26

32

■ SPI_2: SPI_CS (slave only)

P26

PWM0

Input

VDDO

floating

Input

■ SPI_1: MISO (master only)

Current: 16 mA

■ GPIO: P13

P13

PWM3

Input

VDDO

floating

■ A/D converter input

■ GPIO: P28

29

■ A/D converter input

■ LED1

P28

PWM2

Input

VDDO

floating

Input

■ IR_TX

Current: 16 mA

■ GPIO: P14

P14

PWM2

Input

VDDO

floating

Input

■ A/D converter input

■ GPIO: P38

30

■ A/D converter input

■ SPI_2: MOSI (master and slave)

■ IR_TX

Input

VDDO

floating

P38

P15

■ GPIO: P15

■ A/D converter input

■ IR_RX

Input

VDDO

floating

31

Input

■ 60 Hz_main

Document Number: 002-14883 Rev. *G

Page 26 of 49

CYW20736

Table 11. QFN Package GPIO Pin Descriptions^a(Cont.)

Default

Direction

After

Power

Pin Number

Pin Name

Alternate Function Description

POR State Domain

■ GPIO: P24

■ SPI_2: SPI_CLK (master and slave)

■ SPI_1: MISO (master only)

■ Peripheral UART: puart_tx

■ GPIO: P25

Input

VDDO

floating

27

P24

Input

VDDO

floating

26

25

P25

P32

■ SPI_2: MISO (master and slave)

■ Peripheral UART: puart_rx

■ GPIO: P32

■ A/D converter input

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Auxiliary clock output: ACLK0

■ Peripheral UART: puart_tx

Input

VDDO

floating

Input

a. During a power-on reset, all inputs are disabled.

Document Number: 002-14883 Rev. *G

Page 27 of 49

CYW20736

Table 12 provides the GPIO alternate function descriptions for the WLCSP package.

Table 12. WLCSP Package GPIO Pin Descriptions^a

Default

Direction

Power

Domain

Pin Number

Pin Name

After POR

Alternate Function Description

■ GPIO: P0

■ Keyboard scan input (row): KSI0

■ A/D converter input

■ Peripheral UART: puart_tx

■ SPI_2: MOSI (master and slave)

■ IR_RX

21

P0

Input

Floating

VDDO

■ 60 Hz_main

■ Not available during TMC=1

■ GPIO: P1

■ Keyboard scan input (row): KSI1

■ A/D converter input

■ Peripheral UART: puart_rts

■ SPI_2: MISO (master and slave)

■ IR_TX

26

P1

Input

Floating

VDDO

■ GPIO: P2

■ Keyboard scan input (row): KSI2

■ Quadrature: QDX0

22

13

31

P2

P3

P4

Input

Floating

VDDO

■ Peripheral UART: puart_rx

■ SPI_2: SPI_CS (slave only)

■ SPI_2: SPI_MOSI (master only)

■ GPIO: P3

■ Keyboard scan input (row): KSI3

■ Quadrature: QDX1

■ Peripheral UART: puart_cts

■ SPI_2: SPI_CLK (master and slave)

■ GPIO: P4

■ Keyboard scan input (row): KSI4

■ Quadrature: QDY0

■ Peripheral UART: puart_rx

■ SPI_2: MOSI (master and slave)

■ IR_TX

Document Number: 002-14883 Rev. *G

Page 28 of 49

CYW20736

Table 12. WLCSP Package GPIO Pin Descriptions^a(Cont.)

Default

Power

Domain

Pin Number

Pin Name

After POR

Alternate Function Description

Direction

■ GPIO: P5

■ Keyboard scan input (row): KSI5

■ Quadrature: QDY1

14

P5

Input

Floating

VDDO

■ Peripheral UART: puart_tx

■ SPI_2: MISO (master and slave)

■ GPIO: P6

■ Keyboard scan input (row): KSI6

■ Quadrature: QDZ0

P6

PWM2

27

Input

Floating

VDDO

■ Peripheral UART: puart_rts

■ SPI_2: SPI_CS (slave only)

■ 60Hz_main

■ GPIO: P7

■ Keyboard scan input (row): KSI7

■ Quadrature: QDZ1

18

36

P7

Input

Floating

VDDO

■ Peripheral UART: puart_cts

■ SPI_2: SPI_CLK (master and slave)

■ GPIO: P8

■ Keyboard scan output (column): KSO0

■ A/D converter input

P8

P9

■ External T/R switch control: ~tx_pd

■ GPIO: P9

■ Keyboard scan output (column): KSO1

■ A/D converter input

63

53

66

Input

Floating

VDDO

■ External T/R switch control: tx_pd

■ GPIO: P10

P10

PWM3

■ Keyboard scan output (column): KSO2

■ A/D converter input

■ GPIO: P11

■ Keyboard scan output (column): KSO3

■ A/D converter input

P11

■ XTALI32K (40‐QFN only)

Document Number: 002-14883 Rev. *G

Page 29 of 49

CYW20736

Table 12. WLCSP Package GPIO Pin Descriptions^a(Cont.)

Default

Power

Domain

Pin Number

Pin Name

After POR

Alternate Function Description

Direction

■ GPIO: P12

■ Keyboard scan output (column): KSO4

■ A/D converter input

55

P12

Input

Floating

VDDO

■ XTALO32K (40‐QFN only)

■ GPIO: P13

■ Keyboard scan output (column): KSO5

■ A/D converter input

P13

PWM3

20

35

Input

Floating

VDDO

■ Alternative Function: P28

■ GPIO: P14

P14

PWM2

■ Keyboard scan output (column): KSO6

■ A/D converter input

■ GPIO: P15

■ Keyboard scan output (column): KSO7

■ A/D converter input

52

P15

Input

Floating

VDDO

■ IR_RX

■ 60Hz_main

■ Alternative Function: P26

■ GPIO: P16

32

23

P16

P17

Input

Floating

VDDO

■ Keyboard scan output (column): KSO8

■ GPIO: P17

■ Keyboard scan output (column): KSO9

■ A/D converter input

■ GPIO: P18

41

28

33

43

P18

P19

P20

P21

Input

Floating

VDDO

■ Keyboard scan output (column): KSO10

■ A/D converter input

■ GPIO: P19

■ Keyboard scan output (column): KSO11

■ A/D converter input

■ GPIO: P20

■ Keyboard scan output (column): KSO12

■ A/D converter input

■ GPIO: P21

■ Keyboard scan output (column): KSO13

■ A/D converter input

Document Number: 002-14883 Rev. *G

Page 30 of 49

CYW20736

Table 12. WLCSP Package GPIO Pin Descriptions^a(Cont.)

Default

Power

Domain

Pin Number

Pin Name

After POR

Alternate Function Description

Direction

■ GPIO: P22

15

P22

Input

Floating

VDDO

■ Keyboard scan output (column): KSO14

■ A/D converter input

■ GPIO: P23

48

47

P23

P24

Input

Floating

■ Keyboard scan output (column): KSO15

■ A/D converter input

■ GPIO: P24

■ Keyboard scan output (column): KSO16

■ SPI_2: SPI_CLK (master and slave)

■ SPI_1: MISO (master only)

■ Peripheral UART: puart_tx

■ GPIO: P25

VDDO

■ Keyboard scan output (column): KSO17

■ SPI_2: MISO (master and slave)

■ Peripheral UART: puart_rx

■ GPIO: P26

19

P25

Input

Floating

■ Keyboard scan output (column): KSO18

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Optical control output: QOC0

■ Current: 16 mA

P26

PWM0

30

Input

Floating

VDDO

■ Alternative function: P15

■ GPIO: P27

■ Keyboard scan output (column): KSO19

■ SPI_2: MOSI (master and slave)

■ Optical control output: QOC1

■ Current: 16 mA

P27

PWM1

25

Input

Floating

VDDO

■ GPIO: P28

■ Optical control output: QOC2

■ A/D converter input

P28

PWM2

49

Input

Floating

VDDO

■ LED1

■ Current: 16 mA

■ Alternative function: P13

Document Number: 002-14883 Rev. *G

Page 31 of 49

CYW20736

Table 12. WLCSP Package GPIO Pin Descriptions^a(Cont.)

Default

Power

Domain

Pin Number

Pin Name

After POR

Alternate Function Description

Direction

■ GPIO: P29

■ Optical control output: QOC3

■ A/D converter input

■ LED2

P29

PWM3

44

Input

Floating

VDDO

■ Current: 16 mA

■ GPIO: P30

■ A/D converter input

■ Pairing button pin in default FW

■ Peripheral UART: puart_rts

■ GPIO: P31

50

39

P30

P31

Input

Floating

VDDO

■ A/D converter input

■ EEPROM WP pin in default FW

■ Peripheral UART: puart_tx

■ GPIO: P32

■ A/D converter input

■ Quadrature: QDX0

38

P32

Input

Floating

VDDO

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Auxiliary clock output: ACLK0

■ Peripheral UART: puart_tx

■ GPIO: P33

■ A/D converter input

■ Quadrature: QDX1

46

P33

Input

Floating

VDDO

■ SPI_2: MOSI (slave only)

■ Auxiliary clock output: ACLK1

■ Peripheral UART: puart_rx

■ GPIO: P34

■ A/D converter input

■ Quadrature: QDY0

34

P34

Input

Floating

VDDO

■ Peripheral UART: puart_rx

■ External T/R switch control: tx_pd

Document Number: 002-14883 Rev. *G

Page 32 of 49

CYW20736

Table 12. WLCSP Package GPIO Pin Descriptions^a(Cont.)

Default

Power

Domain

Pin Number

Pin Name

After POR

Alternate Function Description

Direction

■ GPIO: P35

■ A/D converter input

■ Quadrature: QDY1

■ Peripheral UART: puart_cts

■ GPIO: P36

29

P35

Input

Floating

VDDO

■ A/D converter input

■ Quadrature: QDZ0

62

P36

Input

Floating

VDDO

■ SPI_2: SPI_CLK (master and slave)

■ Auxiliary Clock Output: ACLK0

■ Battery detect pin in default FW

■ External T/R switch control: ~tx_pd

■ GPIO: P37

■ A/D converter input

■ Quadrature: QDZ1

64

P37

Input

Floating

VDDO

■ SPI_2: MISO (slave only)

■ Auxiliary clock output: ACLK1

■ Alternative function: P38, P39

■ GPIO: P38

■ A/D converter input

■ SPI_2: MOSI (master and slave)

■ IR_TX

24

P38

Input

Floating

VDDO

■ XTALO32K (64‐BGA only)

■ Alternate functions: P37, P39

■ GPIO: P39

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Infrared control: IR_RX

■ External PA ramp control: PA_Ramp

■ XTALI32K (64‐BGA only)

■ 60Hz_main

51

P39

Input

Floating

VDDO

■ Alternative function: P37, P38

a. During a power-on reset, all inputs are disabled.

Document Number: 002-14883 Rev. *G

Page 33 of 49

CYW20736

4. Specifications

4.1 Electrical Characteristics

Table 13 shows the maximum electrical rating for voltages referenced to VDD pin.

Table 13. Maximum Electrical Rating

Rating

DC supply voltage for RF domain

DC supply voltage for core domain

DC supply voltage for VDDM domain (UART/I²C)

DC supply voltage for VDDO domain

DC supply voltage for VR3V

Symbol

Value

1.4

Unit

V

–

1.4

V

–

3.8

V

–

3.8

V

–

3.8

V

DC supply voltage for VDDFE

–

1.4

V

Voltage on input or output pin

–

VSS – 0.3 to VDD + 0.3

–30 to +85

V

Operating ambient temperature range

Storage temperature range

Topr

Tstg

°C

–40 to +125

Table 14 shows the power supply characteristics for the range T_J= 0 to 125°C.

Table 14. Power Supply

Parameter

Minimum^a

Typical

Maximum^a

1.26

Unit

V

DC supply voltage for RF

DC supply voltage for Core

1.14

1.62

1.2

–

1.26

V

DC supply voltage for VDDM (UART/I²C)

3.63

V

DC supply voltage for VDDO

–

3.63

V

DC supply voltage for LDOIN

1.425

1.14

–

1.2^b

3.63

V

DC supply voltage for VDDFE

1.26

V

a. Overall performance degrades beyond minimum and maximum supply voltages.

b. 1.2V for Class 2 output with internal VREG.

Table 15 shows the digital level characteristics for (VSS = 0V).

Table 15. LDO Regulator Electrical Specifications

Parameter

Input voltage range

Default output voltage

Conditions

Min

Typ

Max

3.63

–

Unit

–

1.425

–

V

1.2

Range

0.8

–

1.4

–

V

Output voltage

Step size

40 or 80

mV

%

Accuracy at any step

–5

–

+5

30

Load current

–

mA

%V_O/V

Line regulation

Vin from 1.425 to 3.63V, I_load= 30 mA

–0.2

–

0.2

I_loadfrom 1 µA to 30 mA, Vin = 3.3V, Bonding R

0.1

0.2

%V_O/mA

Load regulation

= 0.3Ω

No load @Vin = 3.3V

*Current limit enabled

–

6

5

–

µA

Quiescent current

Power-down current

Vin = 3.3V, worst@70°C

200

nA

Document Number: 002-14883 Rev. *G

Page 34 of 49

CYW20736

Table 16 shows the specifications for the ADC characteristics.

Table 16. ADC Specifications

Parameter

Number of Input channels

Channel switching rate

Input signal range

Reference settling time

Input resistance

Symbol

Conditions

Min

Typ

9

Max

Unit

–

f_ch

V_inp

–

133.33

kch/s

V

0

–

3.63

Changing refsel

7.5

–

s

R_inp

C_inp

f_C

Effective, single ended

500

–

k

pF

kHz

s

Input capacitance

Conversion rate

–

5

5.859

5.35

–

187

170.7

–

Conversion time

T_C

R

–

Resolution

16

bits

–

See Table 2

on page 8

–

Effective number of bits

In specified performance range

Absolute voltage

measurement error

–

±2

–

%

Using on-chip ADC firmware driver

Current

I

P

I_avdd1p2+ I_avdd3p3

–

1.5

–

1

–

mA

mW

nA

Power

–

Leakage current

Power-up time

Integral nonlinearity³

Differential nonlinearity^a

I_leakage

T_powerup

INL

T = 25°C

–

100

200

1

–

µs

In guaranteed performance range

–1

–

LSB^a

DNL

–

1

a. LSBs are expressed at the 10-bit level.

Table 17 shows the specifications for the digital voltage levels.

Table 17. Digital Levels^a

Characteristics

Input low voltage

Symbol

V_IL

Min

Typ

–

Max

Unit

–

0.4

–

V

Input high voltage

V_IH

0.75 × VDDO

–

Input low voltage (VDDO = 1.62V)

Input high voltage (VDDO = 1.62V)

Output low voltage^b

V_IL

–

0.4

–

V

V_IH

1.2

–

V

V_OL

V_OH

C_IN

–

0.4

–

V

Output high voltage^b

VDDO – 0.4

–

V

Input capacitance (VDDMEM domain)

0.12

–

pF

a. This table is also applicable to VDDMEM domain.

b. At the specified drive current for the pad.

Document Number: 002-14883 Rev. *G

Page 35 of 49

CYW20736

Table 18 shows the specifications for current consumption.

Table 18. Current Consumption ^a

Operational Mode

Receive

Conditions

Typ

9.8

Max

10.0

9.3

Unit

mA

Receiver and baseband are both operating, 100% ON.

Transmit

Transmitter and baseband are both operating, 100% ON.

9.1

Internal LPO is in use.

–

12.0

0.65

13.0

–

Sleep

μA

a. Currents measured between power terminals (Vdd) using 90% efficient DC-DC converter at 3V.

4.2 RF Specifications

Table 19. Receiver RF Specifications

Parameter

Mode and Conditions

Min.

Typ.

Max.

Unit

Receiver Section^a

Frequency range

–

2402

–

–93

–90

–

2480

MHz

dBm

RX sensitivity (standard)

RX sensitivity (low current)

Input IP3

0.1% BER, 1 Mbps, dirty transmitter OFF

–

–16

–10

Maximum input

–

Interference Performance^a,b

C/I cochannel

0.1%BER

–

21

15

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I 3 MHz adjacent channel

C/I image channel

0.1%BER

–17

–27

–9.0

–15

0.1%BER

C/I 1 MHz adjacent to image channel

0.1%BER

Out-of-Band Blocking Performance (CW)^a,b

30 MHz to 2000 MHz

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz

Spurious Emissions

30 MHz to 1 GHz

0.1%BER^c

0.1%BER^d

0.1%BER^e

–

–30.0

–35

–

dBm

–35

–30.0

–

–57.0

–55.0

dBm

1 GHz to 12.75 GHz

a. 30.8% PER.

b. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

c. Measurement resolution is 10 MHz.

d. Measurement resolution is 3 MHz.

e. Measurement resolution is 25 MHz.

Document Number: 002-14883 Rev. *G

Page 36 of 49

CYW20736

Table 20. Transmitter RF Specifications

Parameter

Minimum

Typical

Maximum

Unit

Transmitter Section

Frequency range

2402

–

2480

MHz

dBm

dB

Output power adjustment range

Default output power

–20

–

4

–

4.0

2.0

Output power variation

–

Adjacent Channel Power

|M – N| = 2

–

–20

–30

dBm

|M – N| 3

–

Out-of-Band Spurious Emission

30 MHz to 1 GHz

–

–36.0

–30.0

–47.0

dBm

1 GHz to 12.75 GHz

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

–

LO Performance

Initial carrier frequency tolerance

–

±150

kHz

Frequency Drift

Frequency drift

Drift rate

–

±50

20

kHz

–

Frequency Deviation

225

kHz/50 µs

Average deviation in payload

(sequence used is 00001111)

–

2

275

–

kHz

MHz

Maximum deviation in payload

(sequence used is 10101010)

185

–

Channel spacing

–

Document Number: 002-14883 Rev. *G

Page 37 of 49

CYW20736

4.3 Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

4.3.1 UART Timing

Table 21. UART Timing Specifications

Reference

Characteristics

Min

Max

Unit

1

–

24

Baud out

cycles

Delay time, UART_CTS_N low to UART_TXD valid

Setup time, UART_CTS_N high before midpoint of stop bit

Delay time, midpoint of stop bit to UART_RTS_N high

2

3

–

10

2

ns

Baud out

cycles

Figure 11. UART Timing

Document Number: 002-14883 Rev. *G

Page 38 of 49

CYW20736

4.3.2 SPI Timing

The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when 2.2V > VDDIO

≥ 1.62V.

Figure 12 and Figure 13 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively.

Table 22. SPI Interface Timing Specifications

Reference

Characteristics

Time from CSN asserted to first clock edge

Master setup time

Min

1 SCK

–

Typ

100

Max

∞

1

2

3

4

5

6

½ SCK

–

Master hold time

½ SCK

–

Slave setup time

½ SCK

–

Slave hold time

½ SCK

1 SCK

–

Time from last clock edge to CSN deasserted

10 SCK

100

Figure 12. SPI Timing – Mode 0 and 2

6

SPI_CSN

SPI_CLK

1

(Mode 0)

SPI_CLK

(Mode 2)

2

3

‐

First Bit

Second Bit

Last bit

‐

SPI_MOSI

SPI_MISO

4

5

First Bit

Not Driven

Second Bit

Last bit

Not Driven

Figure 13. SPI Timing – Mode 1 and 3

6

SPI_CSN

SPI_CLK

1

(Mode 1)

SPI_CLK

(Mode 3)

2

3

‐

Invalid bit

‐

First bit

Last bit

SPI_MOSI

SPI_MISO

4

5

Not Driven

Document Number: 002-14883 Rev. *G

Page 39 of 49

CYW20736

4.3.3 BSC Interface Timing

Table 23. BSC Interface Timing Specifications

Reference

Characteristics

Min

Max

100

400

800

1000

–

Unit

1

Clock frequency

–

kHz

2

3

START condition setup time

START condition hold time

Clock low time

650

280

650

280

0

ns

–

4

–

5

Clock high time

–

6

Data input hold time^a

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time^b

–

7

100

280

–

8

–

9

400

–

10

650

a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START

or STOP conditions.

b. Time that the cbus must be free before a new transaction can start.

Figure 14. BSC Interface Timing Diagram

Document Number: 002-14883 Rev. *G

Page 40 of 49

CYW20736

4.4 ESD Test Models

ESD can have serious detrimental effects on all semiconductor ICs and the system that contains them. Standards are developed to

enhance the quality and reliability of ICs by ensuring all devices employed have undergone proper ESD design and testing, thereby

minimizing the detrimental effects of ESD. Three major test methods are widely used in the industry today to describe uniform methods

for assessing ESD immunity at Component level, Human Body Model (HBM), Machine Model (MM), and Charged Device Model

(CDM). The following standards were used to test this device:

4.4.1 Human-Body Model (HBM) – ANSI/ESDA/JEDEC JS-001-2012

The HBM has been developed to simulate the action of a human body discharging an accumulated static charge through a device to

ground, and employs a series RC network consisting of a 100 pF capacitor and a 1500ꢀ (Ohm) resistor. Both positive and negative

polarities are used for this test. Although, a 100 ms delay is allowable per specification, the minimum delay used for testing was set

to 300 ms between each pulse.

4.4.2 Machine Model (MM) – JEDEC JESD22-A115C

The MM has been developed to simulate the rapid discharge from a charged conductive object, such as a metallic tool or fixture. The

most common application would be rapid discharge from charged board assembly or the charged cables of automated testers. This

model consists of a 200 pF capacitor discharged directly into a component with no series resistor (0ꢀ). One positive and one negative

polarity pulses are applied. The minimum delay between pulses is 500 ms.

4.4.3 Charged-Device Model (CDM) - JEDEC JESD22-C101E

CDM simulates charging/discharging events that occur in production equipment and processes. The potential for a CDM ESD events

occurs when there is metal-to-metal contact in manufacturing. CDM addresses the possibility that a charge may reside on the lead

frame or package (e.g., from shipping) and discharge through a pin that subsequently is grounded, causing damage to sensitive

devices in the path. Discharge current is limited only by the parasitic impedance and capacitance of the device. CDM testing consists

of charging package to a specified voltage, then discharging the voltage through relevant package leads. One positive and one

negative polarity pulse is applied. The minimum delay between pulses is 200 ms.

4.4.4 Results Summary

ESD Test Voltage Level Results:

■ HBM +/– 2KV PASS

■ CDM +/– 500V PASS

■ MM +/– 150V PASS

Document Number: 002-14883 Rev. *G

Page 41 of 49

CYW20736

5. Mechanical Information

5.1 QFN

Figure 15. 32-pin QFN

Document Number: 002-14883 Rev. *G

Page 42 of 49

CYW20736

Figure 16. 80-pin WLCSP

Document Number: 002-14883 Rev. *G

Page 43 of 49

CYW20736

Figure 17. WLCSP Keep-Out Areas for PCB Layout (Top View, Bumps Facing Down)

Document Number: 002-14883 Rev. *G

Page 44 of 49

CYW20736

5.1.1 Tape Reel and Packaging Specifications

Table 24. CYW20736 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications

Parameter

Quantity per reel

Reel diameter

Value

2500 pieces

13 inches

7 inches

12 mm

Hub diameter

Tape width

Tape pitch

8 mm

The top left corner of the CYW20736 package is situated near the sprocket holes, as shown in Figure 18.

Figure 18. Pin 1 Orientation

Pin 1: Top left corner of package toward sprocket holes

5.2 WLCSP

Table 25 provides WLCSP package information.

Table 25. WLCSP Package Information

Parameter

Value

65 nm

Wafer process

Chip size without seal ring and scribe line

Chip size with seal ring and scribe line

Module die size

2104 μm × 2085 μm

2224 μm × 2205 μm (S+S 120 μm)

2184 μm × 2165 μm

88 μm

UBM size

Bump height

90 μm

Bump diameter

115 μm

Bump pitch

200 μm (minimum)

Document Number: 002-14883 Rev. *G

Page 45 of 49

CYW20736

6. Ordering Information

Table 26. Ordering Information

Part Number

CYW20736A1KML2G

CYW20736A1KWBGT

Package

32-pin QFN

Ambient Operating Temperature

–30°C to +85°C

80-pin WLCSP

Document Number: 002-14883 Rev. *G

Page 46 of 49

CYW20736

A. Appendix: Acronyms and Abbreviations

The following list of acronyms and abbreviations may appear in this document.

Term

Description

ADC

AFH

AHB

APB

APU

analog-to-digital converter

adaptive frequency hopping

advanced high-performance bus

advanced peripheral bus

audio processing unit

Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable

Broadcom Serial Control

Bluetooth controller

ARM7TDMI-S

BSC

BTC

COEX

DFU

DMA

EBI

coexistence

device firmware update

direct memory access

external bus interface

Host Control Interface

high voltage

HCI

HV

IDC

initial digital calibration

intermediate frequency

interrupt request

IF

IRQ

JTAG

LCU

LDO

LHL

Joint Test Action Group

link control unit

low drop-out

lean high land

LPO

LV

low power oscillator

LogicVision

MIA

multiple interface agent

pulse code modulation

phase locked loop

PCM

PLL

PMU

POR

PWM

QD

power management unit

power-on reset

pulse width modulation

quadrature decoder

RAM

RF

random access memory

radio frequency

ROM

RX/TX

SPI

read-only memory

receive, transmit

serial peripheral interface

software

SW

UART

UPI

universal asynchronous receiver/transmitter

µ-processor interface

watchdog

WD

Document Number: 002-14883 Rev. *G

Page 47 of 49

CYW20736

Document History

Document Title: CYW20736 Single-Chip Bluetooth Low Energy-Only System-On-Chip with Support for Wireless Charging

Document Number: 002-14883

Orig. of Submission

Revision

ECN

Description of Change

Change

Date

20736-DS100-R:

Initial release.

**

–

01/03/2014

20736-DS101-R:

Updated:

*A

*B

–

07/11/2014

08/15/2014

•

Ordering Information on page 46.

20736-DS102-R:

Updated:

•

“List of Tables”.

20736-DS103-R:

Updated:

•

Table 6 on page 12.

*C

*D

–

04/10/2015

04/21/2015

Pin Information on page 16 with new WLCSP content.

By moving GPIO Information to the following new GPIO Information on page 25.

20736-DS104-R:

Updated:

•

Table 19 on page 36

20736-DS105-R:

Updated:

Features on page 1: added WLCSP package information.

Table 6 on page 12 and Table 6 on page 12: corrected an error in the unit of measure for

drive level and XTAL drive level, respectively.

Ordering Information on page 46.

*E

–

04/27/2015

Added:

Figure 16 on page 43.

Figure 17 on page 44 (Top View, Bumps Facing Down).

20736-DS106-R:

*F

–

02/16/2016 Added:

ESD Test Models on page 41.

09/30/2016 Updated to Cypress template.

*G

5446877

UTSV

Document Number: 002-14883 Rev. *G

Page 48 of 49

CYW20736

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Lighting & Power Control

Memory

Technical Support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

49

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-14883 Rev. *G

Revised September 30, 2016

Page 49 of 49

厂商	型号	描述	页数
CYPRESS	CYW134MOXC	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
CYPRESS	CYW134MOXCT	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
CYPRESS	CYW134SOXC	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
CYPRESS	CYW134SOXCT	直接Rambus ™时钟发生器[ Direct Rambus⑩ Clock Generator ]	12 页
SPECTRALINEAR	CYW137OXC	FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ]	8 页
SPECTRALINEAR	CYW137OXCT	FTG移动440BX和全美达的Crusoe CPU[ FTG for Mobile 440BX & Transmeta’s Crusoe CPU ]	8 页
SILICON	CYW150	[ 440BX AGPset Spread Spectrum Frequency Synthesizer ]	15 页
SILICON	CYW150OXC	[ 440BX AGPset Spread Spectrum Frequency Synthesizer ]	15 页
SILICON	CYW150OXCT	[ 440BX AGPset Spread Spectrum Frequency Synthesizer ]	15 页
CYPRESS	CYW15G0101DXB	单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ]	39 页