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AZT70QG

型号：

AZT70QG

描述：

可编程电容调谐IC[ Programmable Capacitive Tuning IC ]

品牌：

AZM[ ARIZONA MICROTEK, INC ]

页数：

12 页

PDF大小：

622 K

下载PDF手册
AZT70  
www.azmicrotek.com  
Programmable Capacitive Tuning IC  
DESCRIPTION  
FEATURES  
The AZT70 is a digitally programmed capacitor specifically designed to  
tune a crystal or SAW based oscillator to a desired center frequency. The  
desired capacitance value for production trimming is set by a serial data  
stream when placed into a programming mode. The AZT70 is designed to  
be a labor and cost saving device within the oscillator production process.  
•
Capacitive tuning range of  
2.8pF to 14.55pF  
(See AZT71 for different values)  
•
•
0.063pF minimum step size  
Reprogrammable through  
nonvolatile EEPROM  
storage  
Using EEPROM technology, the capacitance can be re-tuned as needed  
during the production process by repeating the programming steps thereby  
increasing production yield.  
•
May be placed in parallel for  
greater capacitance values  
Very low supply current  
2.5V to 3.6V supply voltage  
The AZT70 is available in an SON8 package (1.5mm x 1.0mm) for very  
small form factor oscillators.  
•
•
BLOCK DIAGRAM  
APPLICATIONS  
•
Fast production tuning of  
crystal or SAW oscillators  
Filters requiring capacitive  
tuning  
•
PACKAGE AVAILABILITY  
SON8  
•
o
o
1.5mm x 1.0mm x 0.4mm  
Green/RoHS Compliant/Pb-Free  
Order Number  
Package  
Marking  
T <Date Code>2  
AZT70QG1  
SON8  
1
2
Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in  
See www.azmicrotek.com for date code format  
www.azmicrotek.com  
+1-480-962-5881  
1630 S Stapley Dr, Suite 127  
Mesa, AZ 85204 USA  
Request a Sample  
May 2012, Rev 1.2  
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
PIN DESCRIPTION AND CONFIGURATION  
Table 1 - Pin Description  
X1  
NC  
VSS  
VDD  
1
8
7
6
5
PV  
Pin  
1
Name  
X1  
Type  
Output  
n/a  
Function  
Capacitance  
2
NC  
not connected  
2
3
4
NC  
CLK  
DA  
3
VSS  
VDD  
DA  
CLK  
NC  
Power  
Power  
Input  
Input  
n/a  
Negative Supply (GND)  
Positive Supply  
4
5
Programming Data Input  
Programming Clock Input  
not connected  
6
7
8
PV  
Input  
Programming Voltage  
Figure 1 – Pin Configuration  
ENGINEERING NOTES  
CAPACITOR STRUCTURE  
The AZT70 capacitance value is composed of three parallel capacitor banks, CF is a fixed capacitor value of 2.8pF and  
Cmid & Clo are variable capacitors of differing ranges and resolutions as seen in Table 2. Capacitors composing Cmid and  
Clo are set with a binary control word through an 11-bit shift register described in PROGRAMMING the AZT70. The  
values of each Clo and Cmid stepping are detailed in the complete Nominal Capacitance Binary Mapping spreadsheet.  
CTotal = CF + Cmid + Clo  
Table 2 - AZT70 Capacitor Structure  
Internal  
Capacitor  
Min Value  
(pF)  
Max Value  
(pF)  
Step Size  
(pF)  
CF  
Cmid  
Clo  
2.8  
0
0
2.8  
9.8  
1.953  
n/a  
1.4  
0.063  
Total  
2.8  
14.553  
www.azmicrotek.com  
+1-480-962-5881  
2
Request a Sample  
May 2012, Rev 1.2  
 
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
PROGRAMMING THE AZT70  
CONTROL WORD  
The capacitance in the AZT70 is controlled by an 11-bit shift register with the data input bit definitions shown in Table 3.  
The control word data is inputted serially on the rising edge of the CLK signal with bit0 first and bit10 last.  
Table 3 - AZT70 Control Word Definition  
11-bit Control Word  
bit10  
bit9  
bit8  
bit7  
bit6  
bit5  
bit4  
---  
bit3  
bit2  
---  
bit1  
LSB  
bit0  
Cmid  
---  
Clo  
---  
Not Used  
Not Used  
Not Used  
MSB  
LSB  
MSB  
The control word mapping is a binary word for each of Cmid and Clo where higher number bits are more significant. Figure  
2 shows the capacitance value mapping for the AZT70. The detailed Nominal Capacitance Binary Mapping can be located  
on the AZM website.  
Figure 2 – AZT70 Capacitance Value Mapping  
www.azmicrotek.com  
+1-480-962-5881  
3
Request a Sample  
May 2012, Rev 1.2  
 
 
 
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
AZT70 FUNCTIONAL MODES  
The AZT70 is designed to be used in 2 functional modes, Programming and Operational.  
In the Programming mode, the AZT70 is used by the manufacturer to set the capacitance value to control the desired  
center frequency of the oscillator. The programming mode uses either the shift registers or EEPROM (detailed later) and  
gives the manufacturer access to pins DA, CLK, and PV which allow the AZT70 to be programmed with an  
accompanying programming board (Figure 3). Arizona Microtek can provide this board (AZPB70) along with software  
that works through all the programming steps/functions described in the next sections.  
In the Operational mode, the EEPROM internal to the AZT70 has already been programmed with the desired factory  
settings. Pins DA, CLK, and PV are to be disconnected, thereby allowing the AZT70’s internal pull-downs to place the  
pins at ground potential. In the operational mode, only 3 pins are necessary for hookup (Figure 4).  
VDD  
DA  
CLK  
PV  
DA  
AZT70  
X1  
Programming  
Board  
CLK  
PV  
(PRT70)  
VSS  
OUT  
OSCILLATOR  
RESONATOR  
Figure 3 – AZT70 in Programming Mode  
VDD  
NC  
NC  
NC  
DA  
AZT70  
X1  
CLK  
PV  
VSS  
OUT  
OSCILLATOR  
RESONATOR  
Figure 4 – AZT70 in Operational Mode  
www.azmicrotek.com  
+1-480-962-5881  
4
Request a Sample  
May 2012, Rev 1.2  
 
 
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
PROGRAMMING MODES  
The AZT70 has two capacitance setting modes from which bits are set and the matching capacitors are selected.  
•
Reading directly from the shift register  
o
This is useful for testing the capacitance and subsequent oscillator frequency. This mode is active after  
the last bit is shifted in and when the CLK pin is left logic high. For the shift register, capacitors are  
selected when bits are active HIGH.  
•
Reading from the value contained in the EEPROM  
o
Prevents customer adjustment and retains factory programming and is active when the CLK pin is at logic  
low or not connected. For the EEPROM, capacitors are selected when bits are active LOW.  
PROGRAMMING FROM THE SHIFT REGISTER  
To initially determine the capacitance value for the desired center frequency of the oscillator one should set the  
capacitance of the AZT70 directly from the active shift register bits. To accomplish this, the CLK pin is left high after the  
last control word bit has been shifted in. Figure 5 shows the control word 11001100100 has been serially entered into the  
register. Note that bit0 is the 1st bit to enter and bit10 is the last. In the AZT70, bit0, bit9 & bit10 do not affect the  
capacitance value but still must be included in the serial bit stream. For the shift register, capacitors are selected when bits  
are active HIGH.  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
Register data  
active when  
CLK is high  
DA  
bit 0  
loaded 1st  
CLK  
t
Figure 5 - Shift register programming  
WRITING DATA TO THE EEPROM  
Once the desired capacitance value has been determined, the digital control word can be written or re-written into the  
EEPROM. By storing the control word in the EEPROM, the customer is prevented from making adjustments from the  
factory set programming data. This is accomplished within the AZT70 with internal pull-downs on the DA, PV, and CLK  
pins. The detailed sequence for writing data to the EEPROM within the AZT70 is described in Table 4. Note that with  
EEPROM, capacitors are selected when bits are active LOW.  
www.azmicrotek.com  
+1-480-962-5881  
5
Request a Sample  
May 2012, Rev 1.2  
 
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
Table 4 – Data writing sequence for EEPROM  
Step  
Action  
Determine the desired capacitor control word with the operational power supply voltage and  
desired oscillator conditions  
1
2
3
4
Set the VDD supply voltage to +5.0V  
If EEPROM is not already erased, erase EEPROM (see ERASING THE EEPROM)  
Read the current state of the EEPROM bits (see READING BACK FROM THE EEPROM)  
Compare the desired control word to the stored EEPROM control word. Count the number of  
differences so as to prevent double/redundant writing  
5
6
7
One bit at a time, load the first desired control word bit (bit selection for EEPROM is active LOW)  
Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 8)  
Progress through all necessary control word bits by repeating steps 5 & 6 until all bits are set to the  
desired control word.  
8
9
Verify the correct EEPROM contents by reading back the individual bits  
For an example of writing bits into the EEPROM, suppose the desired capacitance is 3.43pF. The control word becomes  
‘00000010100’ (Figure 6). Also suppose the EEPROM bits have been erased and therefore logic high (The AZT70 is  
initially shipped in this condition). Since bit0 is the first bit to be loaded, the bit sequence becomes 0-0-1-0-1-0-0-0-0-0-0.  
However, as described before, selecting bits for the EEPROM are active LOW, which will invert the logical values in the  
sequence to 1-1-0-1-0-1-1-1-1-1-1 (Figure 7). Note the differences between the EEPROM bits and the converted control  
word. Since there are 2 differences, two write cycles are required as only 1 bit should be written at a time. Figure 8 shows  
the timing for bit2 while Figure 9 shows the timing for bit4.  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
Figure 6 – Desired control word  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
DA  
difference  
difference  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
EEPROM  
Figure 7 – Converted control word and differences from known EEPROM states  
www.azmicrotek.com  
+1-480-962-5881  
6
Request a Sample  
May 2012, Rev 1.2  
 
 
 
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
DA  
CLK  
PV  
bit 0  
loaded 1st  
bit 10  
loaded last  
10ms  
min  
≥5.6V,  
≤6.1V  
4µs  
min  
t
Figure 8 – First programming cycle to program bit2 into the EEPROM  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
DA  
CLK  
PV  
bit 0  
loaded 1st  
bit 10  
loaded last  
10ms  
min  
≥5.6V,  
≤6.1V  
4µs  
min  
t
Figure 9 – Second programming cycle to program bit4 into the EEPROM  
READING BACK FROM THE EEPROM  
During programming, the PV pin is used to program the necessary control bits into the EEPROM. However, it is also used  
to read the bits currently programmed into the EEPROM. When the PV pin is not used during programming, the AZT70  
provides a weak pull-up and pull-down on the pin. This allows the EEPROM data to be shifted out to the PV pin and read  
after the CLK sequence is complete and when the DA & CLK pins are high (Figure 10). Each EEPROM bit is selected by  
setting the DA signal low (EEPROM selection is active low) during the CLK sequence. With an external 68kΩ resistor  
pull-up to VDD on the PV pin, a low EEPROM bit produces ≤ 0.4V level while a high EEPROM bit produces a ≥ 0.6*VDD  
level.  
www.azmicrotek.com  
+1-480-962-5881  
7
Request a Sample  
May 2012, Rev 1.2  
 
 
 
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
bit5  
selected  
DA  
CLK  
PV  
bit0  
bit10  
loaded last  
loaded 1st  
Resulting voltage if  
bit5 was high in  
EEPROM  
With an external 68kΩ resistor pull-up to VDD  
≥ 0.6*VDD  
≤ 0.4V  
Resulting voltage if  
bit5 was low in  
EEPROM  
indeterminate  
t
Figure 10 – Timing diagram to read bits from EEPROM  
ERASING THE EEPROM  
The EEPROM can be erased by initiating a programming cycle with all DA bits set high, including bit9 and bit10. After  
the programming cycle, all the EEPROM bits are set low (logical high) except for the check bit (bit0), which remains  
high.  
Table 5 – Erase sequence for EEPROM  
Step  
Action  
1
Set the VDD supply voltage to +5.0V  
2
3
4
Load the programming word bits all high.  
Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 11)  
Verify the correct EEPROM contents by reading back the individual bits  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
bit 8  
bit 9  
bit 10  
EEPROM has  
been erased  
(no capacitors  
selected)  
DA  
CLK  
PV  
bit0  
loaded 1st  
bit10  
loaded last  
10ms  
min  
≥5.6V,  
≤6.1V  
4µs  
min  
t
Figure 11 – Programming Sequence for erasing the EEPROM  
www.azmicrotek.com  
+1-480-962-5881  
8
Request a Sample  
May 2012, Rev 1.2  
 
 
 
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
PROGRAMMING VOLTAGE LIMIT CIRCUIT  
Some existing programming circuits use a current source connected to a 6.5 – 8.0 V supply. That circuit produces an  
excessive voltage on the PV pin, which can damage the AZT70. A simple modification eliminates the issue and maintains  
full programming compatibility with existing programming methods. A 5.6 V, ½ watt Zener, 1N5232B or equivalent,  
placed between the PV pin and ground will limit the voltage while still allowing the programming circuit to generate the  
current required for programming fuse link type parts.  
www.azmicrotek.com  
+1-480-962-5881  
9
Request a Sample  
May 2012, Rev 1.2  
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
PERFORMANCE DATA  
Table 6 – Absolute Maximum Ratings  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
Characteristic  
Power Supply  
Rating  
0 to +6.5  
Unit  
V
VDD  
VI1  
Input Voltage  
-0.5 to VDD + 0.5  
-40 to +85  
-65 to +150  
TBD  
V
TA  
Operating Temperature Range  
Storage Temperature Range  
Human Body Model  
°C  
°C  
V
TSTG  
ESDHBM  
ESDMM  
Machine Model  
TBD  
TBD  
V
V
ESDCDM  
Charged Device Model  
1 PV Pin can exceed VDD by 1.2V during the programming interval  
Table 7 – DC Characteristics  
DC Characteristics (VDD = 2.375V to 5.5V unless otherwise specified, TA = -40 to 85 °C)  
Symbol  
Characteristic  
Conditions  
Min  
Typ  
Max  
Unit  
Nominal capacitance variation across  
process  
CPV  
-15  
+15  
%
Capacitance variation across output  
voltage  
CVV  
Voltage variation at X1 pin, 100MHz  
100MHz - Zero Code  
±150 ppm/V  
ppm/°C  
325  
40  
Capacitance variation across  
temperature  
CTV  
100MHz - Mid Code1  
100MHz - Full Scale  
130  
VIH  
VIL  
Input HIGH Voltage  
Input LOW Voltage  
Pull-down Resistor  
Pull-down Resistor  
Pull-down Resistor  
Output High Voltage  
DA, CLK  
DA, CLK  
DA  
0.8 * VDD  
0.2 * VDD  
V
V
Ω
Ω
Ω
V
RPD,D  
RPD,CLK  
RPD,PV  
VOH  
55k  
75k  
CLK  
PV  
170k  
0.6 * VDD  
PV Pin when reading EEPROM bits  
68kΩ pull-up resistor to VDD  
VOL  
VPP  
Output Low Voltage  
0.4  
V
Programming Voltage (VDD=5.0V)  
PV pin when programming EEPROM  
5.6  
6.0  
7.0  
6.1  
V
IDD  
IDDPROG  
tMEM  
Power Supply Current  
Power Supply Current  
EEPROM Data Retention  
Normal Operation  
50  
20  
µA  
µA  
yrs  
Programming Mode  
20  
25  
Tprog  
Programming Temperature  
Programming Cycle  
°C  
k
Cyprog  
10  
1 Bit4, Bit7 High  
www.azmicrotek.com  
+1-480-962-5881  
10  
Request a Sample  
May 2012, Rev 1.2  
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
Table 8 – AC Characteristics  
AC Characteristics (VDD = 2.375V to 5.5V unless otherwise specified, TA = -40 to 85 °C)  
Symbol  
Characteristic  
Fixed Capacitance  
Step Size  
Conditions  
Min  
Typ  
2.8  
Max  
Unit  
CF  
pF  
1.4  
pF  
pF  
Cmid  
Max Value  
9.8  
Step Size  
0.063  
1.953  
pF  
Clo  
Max Value  
pF  
CLK  
Tprog  
Max CLK rate  
50% duty cycle  
5
MHz  
Programming Time (VDD=5.0V, PV=6.0V)  
per bit programmed  
10  
ms  
20MHz - Full Scale  
20MHz - Mid Scale  
100MHz - Full Scale  
100MHz - Mid Scale  
200MHz - Full Scale  
200MHz - Mid Scale  
800MHz - Full Scale  
800MHz - Mid Scale  
200  
100  
50  
50  
25  
35  
8
320  
200  
80  
70  
40  
50  
12  
15  
Q
Q Value  
10  
www.azmicrotek.com  
+1-480-962-5881  
11  
Request a Sample  
May 2012, Rev 1.2  
Arizona Microtek, Inc.  
AZT70  
Programmable Capacitive Tuning IC  
PACKAGE DIAGRAM  
SON8 (1.5x1.0x0.4mm)  
Green/RoHS compliant/Pb-Free  
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.  
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for  
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of  
any product or circuit and specifically disclaims any and all liability, including without limitation special,  
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of  
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems  
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.  
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona  
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all  
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of  
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.  
www.azmicrotek.com  
+1-480-962-5881  
12  
Request a Sample  
May 2012, Rev 1.2  
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