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IZD1520U

型号：

IZD1520U

描述：

点阵液晶显示控制器与驱动程序[ DOT MATRIX LIQUID CRYSTAL DISPLAY CONTROLLER & DRIVER ]

品牌：

INTEGRAL[ INTEGRAL CORP. ]

页数：

12 页

PDF大小：

222 K

下载PDF手册
IZD1520U  
DOT MATRIX LIQUID CRYSTAL DISPLAY CONTROLLER &  
DRIVER  
FEATURES  
• CMOS LSI chips  
• Many command set  
• Total 80 (segment+common) drive sets  
• Low power consumption - 30µW maximum at 2kHz  
external clock  
• Connection with CPU  
Can be directly coupled with 80-port or 68-port system  
• Available in chip form or in 100-pin plastic QFP  
• Pin-to-Pin Replacement for SED1520 Series  
• Power supply VDD - VSS : 2.4 to -7.0V  
VDD - V5 : 3.5 to -13.0V  
DESCRIPTION  
The IZD1520 family of dot matrix LCD (Liquid Crystal Display) drivers are designed for the  
display of characters and graphics.  
The drivers generate LCD drive signals derived from bit mapped data stored in an internal  
RAM.  
The IZD1520 family drivers incorporate innovative circuit design strategies to achieve very  
low power dissipation at a wide range of operating voltages.  
These features give the designer a flexible means of implementing small to medium size  
LCD displays for compact, low power systems.  
The IZD1520 which is able to drive two lines of twelve characters each.  
The IZD1521 which is able to drive 80 segments for extention.  
ABSOLUTE MAXIMUM RATINGS  
Characteristic  
Symbol  
Value  
Unit  
Supply Voltage (1)  
VSS  
V5  
V1, V2, V3, V4  
- 8.0 ~ 0.3  
- 16.5 ~ 0.3  
V5 ~ 0.3  
VSS - 0.3 ~ 0.3  
VSS - 0.3 ~ 0.3  
250  
- 10 ~ + 75  
- 65 ~ + 150  
260  
V
V
V
V
V
mW  
oC  
oC  
oC  
Supply Voltage (2)  
Supply Voltage (3)  
Input Voltage  
VI  
VO  
PD  
Ta  
Tstg  
Tsol  
Output Voltage  
Power Dissipation  
Operating Temperature  
Storage Temperature  
Soldering temperature time (10 sec  
max)  
Notes:  
1.  
2.  
All voltages are specified relative to VDD = 0V.  
The following relation must be always hold  
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥V5.  
3.  
Exceeding the absolute maximum ratings may cause permanent damage to  
the device. Functional operating under these  
conditions is not implied.  
1
IZD1520U  
LINE-UP  
Product  
Name  
Clock Frequency  
Applicable Driver  
Number of  
Number of  
Duty  
SEGMENT  
COMMON  
On-chip External  
Drivers  
61  
Drivers  
IZD1520OA  
IZD1521OA  
IZD1520AA  
IZD1521AA  
18kHz  
18kHz  
18kHz  
2kHz  
IZ1520OA , IZ1521OA  
IZ1520OA  
IZ1520AA , IZ1521AA  
IZ1520AA  
16  
0
16  
0
1/16, 1/32  
1/8 ~ 1/32  
1/16, 1/32  
1/8 ~ 1/32  
-
-
-
80  
61  
2kHz  
80  
BLOCK DIAGRAM IZ1520AA  
LCD drive circuit  
Common counter  
Display data latch circuit  
Display data RAM  
(2560-bit)  
Column address decoder  
CL  
FR  
Display  
timing  
generator  
circuit  
Column address counter  
Column address register  
Command  
decoder  
Status  
MPU interface  
BLOCK DIAGRAM IZD1520OA  
2
IZD1520U  
LCD drive circuit  
Common counter  
Display data latch circuit  
Display data RAM  
(2560-bit)  
Column address decoder  
OSC2  
FR  
Display  
timing  
generator  
circuit  
Column address counter  
Column address register  
Command  
decoder  
Status  
MPU interface  
3
IZD1520U  
BLOCK DIAGRAM IZD1521AA, IZD1521OA  
LCD drive circuit  
Display data latch circuit  
Display data RAM  
(2560-bit)  
Column address decoder  
CL  
FR  
Display  
timing  
generator  
circuit  
Column address counter  
Column address register  
Command  
decoder  
Status  
MPU interface  
ELECTRICAL CHARACTERISTICS  
(Ta = 25oC, VDD = 0V, VSS = -5.0V unless otherwise specified)  
4
IZD1520U  
Characteristic  
Symbol  
Test Condition  
Applicable Termi-  
nals  
Min  
Typ  
Max  
Unit  
Operating Recommended  
Voltage(1)  
Note 1  
Recommended  
Operating  
-5.5  
-7.0  
-5.0  
-4.5  
-2.4  
VSS  
V5  
VSS  
V5  
V
V
-13.0  
-13.0  
-3.5  
Voltage(2) Permitted  
Permitted  
V1, V2  
V3, V4  
V1, V2  
V3, V4  
A0,Di, E, R/W, CS  
0.6 x V5  
V5  
VSS+2.0  
VDD  
0.4xV5  
VDD  
HIGH Input Voltage  
VIH  
V
V
CL, FR, M/S, RES 0.2 x VSS  
VDD  
A0, Di, E, R/W, CS  
VSS  
VSS+0.8  
0.8+VSS  
LOW Input Voltage  
VIL  
CL, FR, M/S, RES  
D0 ÷ D7  
FR  
VSS  
VSS+2.4  
VSS+2.4  
0.2 x VSS  
IOH = -3.0 mA  
IOH = -2.0 mA  
HIGH Output Voltage  
LOW Output Voltage  
VOH  
V
V
OSC2  
I
OH = -120 µA  
IOL = 3.0 mA  
IOL = 2.0 mA  
VSS+0.4  
VSS+0.4  
0.8xVSS  
1.0  
D0 ÷ D7  
FR  
OSC2  
VOL  
I
OL = 120µA  
Input Leakage Current  
Output Leakage Current  
ILI  
A0, E, R/W, CS, CL,  
M/S, RES  
-1.0  
-3.0  
µA  
µA  
ILO  
Outputs are high imped-  
ance  
3.0  
7.5  
D0 ÷ D7, FR  
LCD Driver ON Resistance  
Note 2  
Supply Current, Static  
SEG0 ~ SEG79  
COM0 ~ COM15  
VDD  
5.0  
KΩ  
µA  
µA  
RON  
IDDQ  
V5=-5.0V  
CS = CL = VDD  
fCL=2kHz  
0.05  
2.0  
1.0  
5.0  
During  
Note 3  
display  
V5=-5.0V  
VDD  
9.5  
5.0  
300  
15.0  
10.0  
500  
Rf =1MΩ  
Note 4  
Supply Current, Dynamic  
Input Terminal Capacity  
IDD  
fCL=18KHz  
Note 5  
During access  
cyc=200KHz  
f = 1 MHz  
µA  
f
CIN  
All inputs  
RES  
5.0  
18  
8.0  
21  
pF  
15  
Rf =1MΩ±2%  
Oscillator Frequency  
Reset Time  
fOSC  
tR  
KHz  
µs  
1.0  
1000  
Notes: 1. Operating over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during  
CPU access.  
2. For a voltage differential of 0.1V between input (V1, …, V4) and output (COM, SEC) pins. All voltages within specified  
operating voltage range.  
3.  
4.  
5.  
IZ1520AA and IZ1521AA only. Does not include transient currents due to stray and panel capacitances.  
IZ1521OA only. Does not include transient currents due to stray and panel capacitances.  
IZ1520OA only. Does not include transient currents due to stray and panel capacitances.  
5
IZD1520U  
• Read/Write timing for the 80-port MPU  
Characteristic  
Address hold time  
Address setup time  
System cycle time  
Control pulse width  
Data setup time  
Data hold time  
VDD access time  
Output Disable time  
Low-level pulsewidth  
High-level pulsewidth  
Rise time  
Symbol  
Signal  
Condition  
Min  
Typ  
Max  
Unit  
tAH8  
tAW8  
tCYC8  
tCC8  
tDS8  
tDH8  
tACC8  
tOH8  
tWLCL  
tWHCL  
tr  
A0, CS  
10  
20  
1000  
200  
80  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
ns  
ns  
µs  
µs  
WR, RD  
10  
90  
60  
D0 ÷ D7  
CL = 100pF  
10  
35  
35  
CL  
30  
30  
0.2  
150  
150  
2.0  
Fall time  
tf  
tFDR  
tFDR  
FR delay time  
FR delay time  
Note 1  
Note 2  
FR (Input)  
FR (Input)  
-2.0  
0.2  
2.0  
• Read/Write timing for the 68-port MPU  
Characteristic  
System cycle time  
Address setup time  
Address hold time  
Data setup time  
Data hold time  
Symbol  
Signal  
Condition  
Min  
Typ  
Max  
Unit  
tCYC6  
tAW6  
tAH6  
tDS6  
tDH6  
tOH6  
tACC6  
tEW  
A0  
R/W  
1000  
20  
10  
80  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
ns  
ns  
µs  
µs  
Output disable time  
Access time  
10  
60  
90  
D0 ÷ D7  
CL = 100pF  
Enable  
pulse width  
READ  
WRITE  
E
100  
80  
35  
Low-level pulsewidth  
High-level pulsewidth  
Rise time  
tWLCL  
tWHCL  
tr  
tf  
tFDR  
CL  
35  
30  
30  
0.2  
150  
150  
2.0  
Fall time  
FR delay time  
FR delay time  
Note 1  
Note 2  
FR (Input)  
FR (Input)  
-2.0  
tFDR  
0.2  
2.0  
* The rating when VSS = -3.0V are approximately 100% higher that when VSS = -5.0V  
Notes: 1. The listed input tFDR applies to IZ1520 and IZ1521 in slave mode.  
2. The listed input tFDR applies to IZ1520 and IZ1521 in master mode.  
6
IZD1520U  
• TIMING CHART  
• Read/Write timing for the 80-port MPU  
t
AH8  
AO, CS  
t
CYC8  
t
AW8  
WR, RD  
tCC8  
t
DS8  
t
DH8  
D0~D7  
(WRITE)  
t
OH8  
t
ACC8  
D0~D7  
(READ)  
• Read/Write timing for the 68-port MPU  
• Read/Write timing for the 80-port/68-port display  
CL  
t
WHCL  
t
WLCL  
t
f
tr  
tDFR  
FR  
7
IZD1520U  
TERMINAL DESCRIPTION  
Terminal Name  
Function  
Data I/O  
D0 ÷ D7  
A0  
Select display data or functions.  
HIGH: Display data  
LOW : Instructions  
Resets the system and selects the interface type for a 68-port/80-port MPU  
HIGH: 68-port MPU interface  
LOW : 80-port MPU interface  
Input. Active low. Effective for an external clock operation model only.  
Chip Select input  
RES  
CS  
OSC1  
E
(RD)  
LOW : Active level sensing  
Read/Write Enable signal when a 68-port MPU is connected.  
(Active LOW Read Enable signal when an 80-port MPU is connected)  
Read/Write Select signal when a 68-port MPU is connected.  
HIGH: Read Select  
R/W  
LOW : Write Select  
(WR)  
(Active LOW Write Enable input when an 80-port MPU is connected Rising  
edge sensing)  
CL  
OSC2  
FR  
SEGn  
COMn  
M/S  
Input. Effective for an external clock operation model only.  
External clock input (only effective with external clock types)  
LCD Frame (AC- conversion) signal input/output  
Segment output for driving the LCD  
Common output for driving the LCD  
Master/Slave Select signal  
VDD  
5V power supply  
VSS  
0V power supply (GND level)  
V1, V2, V3, V4, V5  
Power supplies for driving the LCD. VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5  
8
IZD1520U  
DISPLAY COMMANDS  
(Based on the 80-port MPU; the RD and WR commands differ for the 68-port MPU)  
RD WR A0 D7 D6 D5 D4 D3 D2 D1 D0  
Command  
Function  
1
0
0
1
0
1
0
1
1
1
0/1  
1
Display ON/OFF  
Switches the entire display ON or OFF regard-  
less of the Display RAM’s data or the internal  
status. *Note  
1
1
1
0
0
0
0
0
0
1
1
0
1
0
0
1
Display START  
address (0 ÷ 31)  
2
3
4
Display START  
Line  
Determines the line of RAM data to be dis-  
played at the display’s top line (COM0)  
1
1
0
Page  
Page Address  
Set  
Sets the page of the Display RAM in the page  
address register  
Column address  
(0 ÷ 79)  
Column (Seg-  
ment) Address  
Set  
Sets the column address of the Display RAM  
in the column address register  
0
1
0
5
Status Read  
Reads the status.  
BUSY 1: Busy (internal processing) 0: READY  
status  
ADC  
1: Rightward (forward) output  
0: Leftward (reverse) output  
0
0
0
0
ON/OFF 1: Display OFF 0: Display ON  
RESET 1: Resetting  
0: Normal  
1
0
0
1
1
1
Write Data  
Read Data  
6
7
Write Display  
Data  
Writes the data on  
These commands ac-  
the data bus to RAM cess a previously speci-  
fied address  
Read Display  
Data  
Reads data from the of the Display RAM,  
Display RAM onto  
the data bus  
after which the column  
address is incremented  
one  
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0/1  
0/1  
8
9
ADC Select  
Used to reverse the correspondence between  
the Display RAM’s column addresses and  
segment driver output ports  
0: Rightward (forward) output 1: Leftward (re-  
verse)  
0
Static Drive  
ON/OFF  
Selects normal display operation or static all-fit  
drive display operation  
1: Static drive (Power Save) 0: Normal display  
Selects the duty factor for driving LCD cells  
1: 1/32 duty 0: 1/16 duty  
Increments the column address counter by  
one only when display data is written but not  
when it is read  
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
0
0/1  
0
10 Duty Select  
11 Read Modify  
Write  
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
1
1
0
0
12 End  
13 Reset  
Cancels the Ready Modify Write mode  
Resets the Display START line to the 1-st line  
in the register.  
Resets the column address counter and page  
address register to 0.  
Note: Power Save mode is entered by selecting static drive in the Display OFF status.  
9
IZD1520U  
REFERENCE CIRCUITRY EXAMPLES  
• 16 x 61 dots  
• 16 x 141 dots  
1/16 duty  
1/16 duty  
1
LCD Cell  
16 x 61 dots  
1 - 61  
1
LCD Cell  
16 x 141 dots  
16  
1 - 61  
SEG  
62 - 141  
SEG  
16  
SEG  
COM  
COM  
VDD  
V
DD  
M/S  
M/S  
M/S  
OSC2  
A0  
D
A
0
OSC1  
FR  
FR CL  
D
A
0
OSC1  
D
OSC2  
Rf  
MPU  
CB  
Rf  
MPU  
CB  
DB  
DB  
A
0
A0  
• 32 x 202 dots  
1
1/32 Duty  
LCD Cell  
32 x 202 dots  
16  
17  
32  
1 - 16  
SEG  
62-141  
SEG  
142 - 202  
SEG  
COM  
COM  
V
DD  
M/S  
M/S  
M/S  
OSC2  
OSC1  
FR  
FR  
D
CL FR  
CL FR  
D
A
0
D
A0  
A
0
MPU  
CB  
DB  
A
0
Note: If a system has two or more slave drivers a CMOS buffer will be required for clock  
signal.  
10  
IZD1520U  
PAD LAYOUT  
(6500, 5000)  
51  
79  
80  
78  
77  
76  
75  
74  
72  
71  
70  
69  
68  
67  
66  
65 64 63  
62  
60  
59  
58  
56  
55  
54  
53  
52  
73  
61  
57  
81  
82  
83  
50  
49  
48  
84  
85  
86  
47  
46  
45  
44  
87  
88  
89  
90  
Y
43  
42  
41  
(0,0)  
X
91  
40  
39  
38  
37  
36  
35  
34  
92  
93  
94  
95  
96  
PAD  
DIAGRAM  
BT1520  
Chip size : 6500 x 5000  
Pad size  
Unit  
:
120 x 120  
:
µm  
97  
98  
99  
33  
32  
31  
100  
1
3
4
5
6
7
8
9
11  
12  
13  
14  
15  
16 17  
18  
19  
20  
21  
22  
23  
24  
26  
27  
28  
29  
30  
2
10  
25  
PAD LOCATION ( Unit: µm)  
Pad  
No.  
Pad Name  
X
Y
Pad  
No.  
Pad Name  
X
Y
Pad  
No.  
Pad Name  
X
Y
1
COM5  
-2994  
-2717  
-2510  
-2302  
-2132  
-1924  
-1754  
-1547  
-1377  
-1167  
-998  
-790  
-620  
-413  
-242  
-35  
-2243  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-1857  
-1648  
-1474  
-1270  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
SEG32  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
SEG25  
SEG24  
SEG23  
SEG22  
SEG21  
SEG20  
SEG19  
SEG18  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
1494  
2434  
2226  
2056  
1848  
1678  
1470  
1300  
1012  
922  
-1100  
-892  
-722  
-515  
-344  
-136  
33  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
SEG3  
SEG2  
SEG1  
SEG0  
A0  
-650  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
1895  
1695  
1497  
1297  
1097  
916  
2
COM6  
-798  
3
COM7  
-968  
4
COM8  
-1177  
-1368  
-1569  
-1761  
-1953  
-2142  
-2348  
-2646  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-2994  
-2994  
-2994  
-2994  
-2994  
5
COM9  
6
COM10  
COM11  
COM12  
COM13  
COM14  
COM15  
SEG60  
SEG59  
SEG58  
SEG57  
SEG56  
SEG55  
SEG54  
SEG53  
SEG52  
SEG51  
SEG50  
SEG49  
SEG48  
SEG47  
SEG46  
SEG45  
SEG44  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
OSC1 [CS]  
OSC2 [CL]  
E [RD]  
R/W (WR)  
GND  
DB0  
7
8
241  
9
412  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
620  
790  
998  
DB1  
1170  
1376  
1544  
1754  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
DB2  
DB3  
DB4  
DB5  
135  
DB6  
344  
DB7  
514  
VCC  
737  
722  
RES  
542  
892  
FR  
342  
1100  
1270  
1478  
1607  
1856  
2026  
2234  
2477  
3020  
3010  
3010  
3010  
3010  
V5  
162  
V3  
-18  
V2  
-198  
-398  
-603  
-806  
-996  
-1166  
-1375  
-1544  
-1753  
M/S  
V4  
V1  
714  
COM0  
COM1  
COM2  
COM3  
COM4  
544  
SEG8  
336  
SEG7  
166  
SEG6  
-42  
SEG5  
-213  
-420  
SEG4  
Note: Pads 74,75 are OSC1, OSC2 for BT5150OA and CS, CL for IZ1520AA respectively. All other pad names are identical.  
11  
IZD1520U  
PAD LAYOUT  
(6500, 5000)  
51  
79  
80  
78  
77  
76  
75  
74  
72  
71  
70  
69  
68  
67  
66  
65 64  
63  
62  
60  
59  
58  
56  
55  
54  
53  
52  
73  
61  
57  
81  
82  
83  
50  
49  
48  
84  
85  
86  
47  
46  
45  
44  
87  
88  
89  
90  
Y
43  
42  
41  
(0,0)  
X
91  
40  
39  
38  
37  
36  
35  
34  
92  
93  
94  
95  
96  
PAD  
DIAGRAM  
BT1521  
Chip size : 6500 x 5000  
Pad size  
Unit  
:
120 x 120  
:
µm  
97  
98  
99  
33  
32  
31  
100  
1
3
4
5
6
7
8
9
11  
12  
13  
14  
15  
16 17  
18  
19  
20  
21  
22  
23  
24  
26  
27  
28  
29  
30  
2
10  
25  
PAD LOCATION ( Unit: µm)  
Pad  
No.  
Pad Name  
X
Y
Pad  
No.  
Pad Name  
X
Y
Pad  
No.  
Pad Name  
X
Y
1
2
3
4
5
SEG71  
SEG70  
SEG69  
SEG68  
SEG67  
-2994  
-2717  
-2510  
-2302  
-2132  
-2243  
-2244  
-2244  
-2244  
-2244  
35  
36  
37  
38  
39  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
3010  
3010  
3010  
3010  
3010  
-1100  
-892  
-722  
-515  
-344  
69  
70  
71  
72  
73  
SEG3  
SEG2  
SEG1  
SEG0  
A0  
-650  
2242  
2242  
2242  
2242  
2242  
-798  
-968  
-1177  
-1368  
6
SEG66  
SEG65  
SEG64  
SEG63  
SEG62  
SEG61  
SEG60  
SEG59  
SEG58  
SEG57  
SEG56  
SEG55  
SEG54  
SEG53  
SEG52  
SEG51  
SEG50  
SEG49  
SEG48  
SEG47  
SEG46  
SEG45  
SEG44  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
-1924  
-1754  
-1547  
-1377  
-1167  
-998  
-790  
-620  
-413  
-242  
-35  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-1857  
-1648  
-1474  
-1270  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
SEG32  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
SEG25  
SEG24  
SEG23  
SEG22  
SEG21  
SEG20  
SEG19  
SEG18  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
1494  
2434  
2226  
2056  
1848  
1678  
1470  
1300  
1012  
922  
-136  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
CS  
-1569  
-1761  
-1953  
-2142  
-2348  
-2646  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-2994  
-2994  
-2994  
-2994  
-2994  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
1895  
1695  
1497  
1297  
1097  
916  
7
33  
CL  
8
9
241  
E RD  
R/W (WR)  
GND  
DB0  
412  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
620  
790  
998  
DB1  
1170  
1376  
1544  
1754  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
DB2  
DB3  
DB4  
DB5  
135  
DB6  
344  
DB7  
514  
VCC  
737  
722  
RES  
542  
892  
FR  
342  
1100  
1270  
1478  
1607  
1856  
2026  
2234  
2477  
3020  
3010  
3010  
3010  
3010  
V5  
162  
V3  
-18  
V2  
-198  
-398  
-603  
-806  
-996  
-1166  
-1375  
-1544  
-1753  
SEG79  
SEG78  
SEG77  
SEG76  
SEG75  
SEG74  
SEG73  
SEG72  
714  
544  
SEG8  
336  
SEG7  
166  
SEG6  
-42  
SEG5  
-213  
-420  
SEG4  
12  
厂商 型号 描述 页数 下载

INTEGRAL

 		IZD1520 CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

INTEGRAL

 		IZD1520AA CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

INTEGRAL

 		IZD1520OA CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

INTEGRAL

 		IZD1521AA CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

INTEGRAL

 		IZD1521OA CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

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