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IZD1521OA

型号：

IZD1521OA

描述：

CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ]

品牌：

INTEGRAL[ INTEGRAL CORP. ]

页数：

13 页

PDF大小：

155 K

下载PDF手册
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
FEATURES  
• Many command set  
• CMOS LSI chips  
• Total 80 (segment+common) drive sets  
• Connection with CPU  
• Low power consumption - 30µW maximum at 2kHz  
external clock  
Can be directly coupled with 80-port or 68-port system  
• Available in chip form or in 100-pin plastic QFP  
• Pin-to-Pin Replacement for SED1520 Series  
• Power supply VDD - VSS : 2.4 to -7.0V  
VDD - V5 : 3.5 to -13.0V  
DESCRIPTION  
The IZD1520 family of dot matrix LCD (Liquid Crystal Display) drivers are designed for the display of characters and graphics.  
The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM.  
The IZD1520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages.  
These features give the designer a flexible means of implementing small to medium size LCD displays for compact, low power systems.  
The IZD1520 which is able to drive two lines of twelve characters each.  
The IZD1521 which is able to drive 80 segments for extension.  
ABSOLUTE MAXIMUM RATINGS  
Characteristic  
Symbol  
Value  
Unit  
Supply Voltage (1)  
Supply Voltage (2)  
Supply Voltage (3)  
Input Voltage  
VSS  
- 8.0 ~ 0.3  
- 16.5 ~ 0.3  
V5 ~ 0.3  
V
V
V5  
V1, V2, V3, V4  
V
VI  
VO  
PD  
VSS - 0.3 ~ 0.3  
VSS - 0.3 ~ 0.3  
250  
V
Output Voltage  
V
Power Dissipation  
mW  
oC  
oC  
oC  
Operating Temperature  
Ta  
- 10 ~ + 75  
- 65 ~ + 150  
260  
Storage Temperature  
Tstg  
Tsol  
Soldering temperature time (10 sec max)  
Notes:  
1.  
2.  
All voltages are specified relative to VDD = 0V.  
The following relation must be always hold  
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥V5.  
3.  
Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional operating under these  
conditions is not implied.  
LINE-UP  
Product  
Name  
Clock Frequency  
Number of  
SEGMENT  
Drivers  
Number of  
COMMON  
Drivers  
Applicable Driver  
Duty  
On-chip  
External  
IZD1520OA  
IZD1521OA  
IZD1520AA  
IZD1521AA  
18kHz  
18kHz  
18kHz  
2kHz  
IZD1520OA , IZD1521OA  
61  
80  
61  
80  
16  
0
1/16, 1/32  
1/8 ~ 1/32  
1/16, 1/32  
1/8 ~ 1/32  
-
-
-
IZD1520OA  
IZD1520AA , IZD1521AA  
IZD1520AA  
16  
0
2kHz  
1
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
BLOCK DIAGRAM IZD1520AA  
LCD drive circuit  
Com m on counter  
D isplay data latch circuit  
D isplay data RA M  
(2560-bit)  
Colum n address decoder  
CL  
FR  
D isplay  
tim ing  
generator  
circuit  
Colum n address counter  
Colum n address register  
Com m and  
decoder  
Status  
M PU interface  
2
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
BLOCK DIAGRAM IZD1520OA  
LCD drive circuit  
Com m on counter  
D isplay data latch circuit  
D isplay data RA M  
(2560-bit)  
Colum n address decoder  
OSC2  
FR  
D isplay  
tim ing  
generator  
circuit  
Colum n address counter  
Colum n address register  
Com m and  
decoder  
Status  
M PU interface  
3
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
BLOCK DIAGRAM IZD1521AA, IZD1521OA  
LCD drive circuit  
D isplay data latch circuit  
D isplay data RA M  
(2560-bit)  
Colum n address decoder  
CL  
D isplay  
Colum n address counter  
Colum n address register  
tim ing  
generator  
circuit  
FR  
Com m and  
decoder  
Status  
M PU interface  
4
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
ELECTRICAL CHARACTERISTICS  
(Ta = 25oC, VDD = 0V, VSS = -5.0V unless otherwise specified)  
Characteristic  
Symbo  
l
Test Condition  
Applicable Terminals  
Min  
Typ  
Max  
Unit  
Operating  
Recommended  
Recommended  
-5.5  
-7.0  
-5.0  
-4.5  
-2.4  
Voltage(1)  
Note 1  
VSS  
V5  
VSS  
V5  
V
V
-13.0  
-13.0  
-3.5  
Operating  
Voltage(2)  
Permitted  
Permitted  
V1, V2  
V3, V4  
V1, V2  
V3, V4  
0.6 x V5  
V5  
VDD  
0.4xV5  
VDD  
A0,Di, E, R/W, CS  
VSS+2.0  
HIGH Input Voltage  
LOW Input Voltage  
VIH  
V
V
CL, FR, M/S, RES  
A0, Di, E, R/W, CS  
0.2 x VSS  
VSS  
VDD  
VSS+0.8  
0.8+VSS  
VIL  
CL, FR, M/S, RES  
D0 ÷ D7  
FR  
VSS  
VSS+2.4  
VSS+2.4  
0.2 x VSS  
IOH = -3.0 mA  
IOH = -2.0 mA  
IOH = -120 µA  
IOL = 3.0 mA  
IOL = 2.0 mA  
IOL = 120µA  
HIGH Output Voltage  
VOH  
V
OSC2  
VSS+0.4  
VSS+0.4  
0.8xVSS  
1.0  
D0 ÷ D7  
FR  
LOW Output Voltage  
Input Leakage Current  
VOL  
V
OSC2  
ILI  
A0, E, R/W, CS, CL,  
M/S, RES  
-1.0  
-3.0  
µA  
Output Leakage Current  
LCD Driver ON Resistance  
Note 2  
ILO  
Outputs are high impedance  
V5=-5.0V  
3.0  
7.5  
D0 ÷ D7, FR  
SEG0 ~ SEG79  
COM0 ~ COM15  
VDD  
µA  
5.0  
KΩ  
RON  
Supply Current, Static  
IDDQ  
CS = CL = VDD  
fCL=2kHz  
0.05  
2.0  
1.0  
5.0  
µA  
µA  
During  
Note 3  
display  
VDD  
9.5  
5.0  
15.0  
10.0  
Rf =1MΩ  
Note 4  
V5=-5.0V  
Supply Current, Dynamic  
Input Terminal Capacity  
IDD  
fCL=18KHz  
Note 5  
During access fcyc=200KHz  
300  
5.0  
18  
500  
8.0  
µA  
CIN  
fOSC  
tR  
f = 1 MHz  
All inputs  
RES  
pF  
15  
21  
Rf =1MΩ±2%  
Oscillator Frequency  
Reset Time  
KHz  
1.0  
1000  
µs  
Notes: 1. Operating over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during  
CPU access.  
2. For a voltage differential of 0.1V between input (V1, …, V4) and output (COM, SEC) pins. All voltages within specified  
operating voltage range.  
3.  
4.  
5.  
IZD1520AA and IZD1521AA only. Does not include transient currents due to stray and panel capacitances.  
IZD1521OA only. Does not include transient currents due to stray and panel capacitances.  
IZD1520OA only. Does not include transient currents due to stray and panel capacitances.  
5
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
• Read/Write timing for the 80-port MPU  
Characteristic  
Address hold time  
Symbol  
Signal  
Condition  
Min  
Typ  
Max  
Unit  
tAH8  
tAW8  
tCYC8  
tCC8  
tDS8  
tDH8  
tACC8  
tOH8  
tWLCL  
tWHCL  
tr  
A0, CS  
10  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
ns  
ns  
µs  
µs  
Address setup time  
System cycle time  
Control pulse width  
Data setup time  
Data hold time  
WR, RD  
1000  
200  
80  
10  
VDD access time  
Output Disable time  
Low-level pulsewidth  
High-level pulsewidth  
Rise time  
90  
60  
D0 ÷ D7  
CL = 100pF  
10  
35  
35  
CL  
30  
30  
150  
150  
2.0  
Fall time  
tf  
FR delay time  
FR delay time  
Note 1  
Note 2  
tFDR  
tFDR  
FR (Input)  
FR (Input)  
-2.0  
0.2  
0.2  
2.0  
• Read/Write timing for the 68-port MPU  
Characteristic  
System cycle time  
Symbol  
Signal  
Condition  
Min  
Typ  
Max  
Unit  
tCYC6  
tAW6  
tAH6  
tDS6  
A0  
1000  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
ns  
ns  
µs  
µs  
Address setup time  
Address hold time  
Data setup time  
Data hold time  
R/W  
10  
80  
tDH6  
tOH6  
tACC6  
tEW  
10  
Output disable time  
Access time  
10  
60  
90  
D0 ÷ D7  
CL = 100pF  
Enable  
READ  
WRITE  
E
100  
80  
pulse width  
Low-level pulsewidth  
High-level pulsewidth  
Rise time  
tWLCL  
tWHCL  
tr  
35  
CL  
35  
30  
30  
150  
150  
2.0  
Fall time  
tf  
FR delay time  
FR delay time  
Note 1  
Note 2  
tFDR  
tFDR  
FR (Input)  
FR (Input)  
-2.0  
0.2  
0.2  
2.0  
* The rating when VSS = -3.0V are approximately 100% higher that when VSS = -5.0V  
Notes: 1. The listed input tFDR applies to IZD1520 and IZD1521 in slave mode.  
2. The listed input tFDR applies to IZD1520 and IZD1521 in master mode.  
6
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
• Timing Chart  
• Read/Write timing for the 80-port MPU  
tA H 8  
A O, CS  
t
CY C8  
tA W 8  
W R, RD  
tCC8  
tD S8  
t
D H 8  
D0~D7  
(W R IT E )  
t
O H 8  
tA CC8  
D0~D7  
(R E A D )  
• Read/Write timing for the 68-port MPU  
• Read/Write timing for the 80-port/68-port display  
CL  
t
W H CL  
t
W
LCL  
t
f
t
r
t
D FR  
FR  
7
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
TERMINAL DESCRIPTION  
Terminal Name  
Function  
Data I/O  
D0 ÷ D7  
A0  
Select display data or functions.  
HIGH: Display data  
LOW : Instructions  
Resets the system and selects the interface type for a 68-port/80-port MPU  
HIGH: 68-port MPU interface  
RES  
CS  
LOW : 80-port MPU interface  
Input. Active low. Effective for an external clock operation model only.  
Chip Select input  
OSC1  
E
LOW : Active level sensing  
Read/Write Enable signal when a 68-port MPU is connected.  
(Active LOW Read Enable signal when an 80-port MPU is connected)  
Read/Write Select signal when a 68-port MPU is connected.  
HIGH: Read Select  
(RD)  
R/W  
LOW : Write Select  
(WR)  
(Active LOW Write Enable input when an 80-port MPU is connected Rising edge sensing)  
Input. Effective for an external clock operation model only.  
External clock input (only effective with external clock types)  
LCD Frame (AC- conversion) signal input/output  
Segment output for driving the LCD  
CL  
OSC2  
FR  
SEGn  
COMn  
M/S  
Common output for driving the LCD  
Master/Slave Select signal  
VDD  
5V power supply  
VSS  
0V power supply (GND level)  
V1, V2, V3, V4, V5  
Power supplies for driving the LCD. VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5  
8
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
DISPLAY COMMANDS  
(Based on the 80-port MPU; the RD and WR commands differ for the 68-port MPU)  
Command  
RD WR A0  
D7 D6 D5 D4 D3 D2 D1 D0  
Function  
1
2
Display ON/OFF  
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
1
0/1  
Switches the entire display ON or OFF regardless of  
the Display RAM’s data or the internal status. *Note  
Display START Line  
Page Address Set  
Display START  
Determines the line of RAM data to be displayed at the  
display’s top line (COM0)  
address (0 ÷ 31)  
3
4
5
1
1
0
0
0
1
0
0
0
1
0
0
1
1
1
0
Page  
Sets the page of the Display RAM in the page address  
register  
Column (Segment)  
Address Set  
Column address  
Sets the column address of the Display RAM in the  
column address register  
(0 ÷ 79)  
Status Read  
Reads the status.  
BUSY 1: Busy (internal processing) 0: READY  
status  
ADC  
1: Rightward (forward) output  
0: Leftward (reverse) output  
0
0
0
0
ON/OFF 1: Display OFF  
RESET 1: Resetting  
0: Display ON  
0: Normal  
6
7
Write Display Data  
Read Display Data  
1
0
0
1
1
1
Write Data  
Read Data  
Writes the data on the  
data bus to RAM  
These commands access a  
previously specified  
address  
Reads data from the  
Display RAM onto the  
data bus  
of the Display RAM,  
after which the column  
address is incremented  
one  
8
9
ADC Select  
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0/1  
0/1  
Used to reverse the correspondence between the  
Display RAM’s column addresses and segment driver  
output ports  
0: Rightward (forward) output 1: Leftward (reverse)  
Static Drive ON/OFF  
1
Selects normal display operation or static all-fit drive  
display operation  
1: Static drive (Power Save) 0: Normal display  
Selects the duty factor for driving LCD cells  
10  
11  
Duty Select  
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
0
0/1  
0
1: 1/32 duty  
0: 1/16 duty  
Read Modify Write  
Increments the column address counter by one only  
when display data is written but not when it is read  
12  
13  
End  
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
1
1
0
0
Cancels the Ready Modify Write mode  
Reset  
Resets the Display START line to the 1-st line in the  
register.  
Resets the column address counter and page address  
register to 0.  
Note: Power Save mode is entered by selecting static drive in the Display OFF status.  
9
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
REFERENCE CIRCUITRY EXAMPLES  
• 16 x 61 dots  
• 16 x 141 dots  
1 /1 6 d u ty  
1/16 duty  
1
LC  
16 x61 dots  
- 61  
D
C ell  
1
LC D C ell  
16  
1
16 x141 dots  
1 -61  
SEG  
62 -141  
SEG  
16  
SEG  
C
O M  
C O M  
V
DD  
V
DD  
M /S  
M
/S  
M /S  
A
0
O SC1  
D
O SC2  
A
0
D
A
0
O SC 1 O SC 2 FR  
FR  
C L  
D
Rf  
Rf  
M
PU  
M PU  
C B  
C
B
DB  
DB  
A
0
A
0
• 32 x 202 dots  
1
1/32 Duty  
LC D C ell  
32 x 202 dots  
16  
17  
32  
1 -16  
SEG  
62-141  
142 -202  
SEG  
SEG  
C
O M  
C
O M  
V
DD  
M /S  
M /S  
M /S  
O SC 2  
D
A
0
O SC 1  
FR  
FR  
D
0
C L  
FR  
D
A
0
C L  
FR  
A
M PU  
C B  
DB  
A
0
Note: If a system has two or more slave drivers a CMOS buffer will be required for clock signal.  
10  
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
PAD LAYOUT  
(6500,5000)  
79  
80  
78  
77  
76  
75  
74  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
60  
59  
58  
56  
55  
54  
53  
52  
51  
73  
61  
57  
81  
82  
83  
50  
49  
48  
84  
85  
47  
46  
86  
87  
88  
89  
90  
45  
44  
Y
43  
42  
41  
(0 ,0 )  
X
91  
92  
40  
39  
38  
PAD  
DIAG RAM IZD1520  
93  
94  
95  
C hip size : 6500 x5000  
Pad size : 120 x120  
Unit  
37  
36  
:
µ
m
96  
97  
35  
34  
98  
99  
33  
32  
31  
100  
1
3
4
5
6
7
8
9
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
26  
27  
28  
29  
30  
2
10  
25  
PAD LOCATION  
( Unit: µm)  
Pad  
No.  
Pad  
No.  
Pad Name  
X
Y
Pad  
No.  
Pad Name  
SEG37  
X
Y
Pad Name  
SEG3  
SEG2  
SEG1  
SEG0  
A0  
OSC1 [CS]  
OSC2 [CL]  
E [RD]  
R/W (WR)  
GND  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
VCC  
RES  
FR  
V5  
V3  
V2  
M/S  
V4  
V1  
COM0  
COM1  
COM2  
COM3  
COM4  
X
Y
1
COM5  
-2994  
-2717  
-2510  
-2302  
-2132  
-1924  
-1754  
-1547  
-1377  
-1167  
-998  
-790  
-620  
-413  
-242  
-35  
-2243  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-1857  
-1648  
-1474  
-1270  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
1494  
2434  
2226  
2056  
1848  
1678  
1470  
1300  
1012  
922  
-1100  
-892  
-722  
-515  
-344  
-136  
33  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
-650  
-798  
-968  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
1895  
1695  
1497  
1297  
1097  
916  
2
3
4
5
6
7
8
9
COM6  
COM7  
COM8  
COM9  
COM10  
COM11  
COM12  
COM13  
COM14  
COM15  
SEG60  
SEG59  
SEG58  
SEG57  
SEG56  
SEG55  
SEG54  
SEG53  
SEG52  
SEG51  
SEG50  
SEG49  
SEG48  
SEG47  
SEG46  
SEG45  
SEG44  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
SEG36  
SEG35  
SEG34  
SEG33  
SEG32  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
SEG25  
SEG24  
SEG23  
SEG22  
SEG21  
SEG20  
SEG19  
SEG18  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
-1177  
-1368  
-1569  
-1761  
-1953  
-2142  
-2348  
-2646  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-2994  
-2994  
-2994  
-2994  
-2994  
241  
412  
620  
790  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
998  
1170  
1376  
1544  
1754  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
135  
344  
514  
722  
737  
542  
342  
162  
892  
1100  
1270  
1478  
1607  
1856  
2026  
2234  
2477  
3020  
3010  
3010  
3010  
3010  
-18  
-198  
-398  
-603  
-806  
-996  
-1166  
-1375  
-1544  
-1753  
714  
544  
336  
166  
SEG8  
SEG7  
SEG6  
SEG5  
-42  
-213  
-420  
SEG4  
Note: Pads 74,75 are OSC1, OSC2 for BT5150OA and CS, CL for IZ1520AA respectively. All other pad names are identical.  
11  
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
PAD LAYOUT  
(6500,5000)  
79  
80  
78  
77  
76  
75  
74  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
60  
59  
58  
56  
55  
54  
53  
52  
51  
73  
61  
57  
81  
82  
83  
50  
49  
48  
84  
85  
47  
46  
86  
87  
88  
89  
90  
45  
44  
Y
43  
42  
41  
(0,0)  
X
91  
92  
40  
39  
38  
IZD1521  
PAD  
DIAG RAM  
93  
94  
95  
C hip size : 6500 x5000  
Pad size : 120 x120  
37  
36  
35  
34  
Unit  
:
µm  
96  
97  
98  
99  
33  
32  
31  
100  
1
3
4
5
6
7
8
9
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
26  
27  
28  
29  
30  
2
10  
25  
PAD LOCATION  
( Unit: µm)  
Pad  
Pad  
No.  
Pad Name  
X
Y
Pad  
No.  
Pad Name  
X
Y
Pad Name  
X
Y
No.  
1
SEG71  
-2994  
-2717  
-2510  
-2302  
-2132  
-2243  
-2244  
-2244  
-2244  
-2244  
35  
36  
37  
38  
39  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
3010  
3010  
3010  
3010  
3010  
-1100  
-892  
-722  
-515  
-344  
69  
70  
71  
72  
73  
SEG3  
SEG2  
SEG1  
SEG0  
A0  
-650  
-798  
-968  
-1177  
-1368  
2242  
2
3
4
5
SEG70  
SEG69  
SEG68  
SEG67  
2242  
2242  
2242  
2242  
6
7
8
9
SEG66  
SEG65  
SEG64  
SEG63  
SEG62  
SEG61  
SEG60  
SEG59  
SEG58  
SEG57  
SEG56  
SEG55  
SEG54  
SEG53  
SEG52  
SEG51  
SEG50  
SEG49  
SEG48  
SEG47  
SEG46  
SEG45  
SEG44  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
-1924  
-1754  
-1547  
-1377  
-1167  
-998  
-790  
-620  
-413  
-242  
-35  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-2244  
-1857  
-1648  
-1474  
-1270  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
SEG32  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
SEG25  
SEG24  
SEG23  
SEG22  
SEG21  
SEG20  
SEG19  
SEG18  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
3010  
1494  
2434  
2226  
2056  
1848  
1678  
1470  
1300  
1012  
922  
-136  
33  
241  
412  
620  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
CS  
CL  
E RD  
R/W (WR)  
GND  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
VCC  
RES  
FR  
V5  
V3  
-1569  
-1761  
-1953  
-2142  
-2348  
-2646  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-3009  
-2994  
-2994  
-2994  
-2994  
-2994  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
1895  
1695  
1497  
1297  
1097  
916  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
790  
998  
1170  
1376  
1544  
1754  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
2242  
135  
344  
514  
722  
737  
542  
342  
162  
892  
1100  
1270  
1478  
1607  
1856  
2026  
2234  
2477  
3020  
3010  
3010  
3010  
3010  
-18  
V2  
-198  
-398  
-603  
-806  
-996  
-1166  
-1375  
-1544  
-1753  
SEG79  
SEG78  
SEG77  
SEG76  
SEG75  
SEG74  
SEG73  
SEG72  
714  
544  
336  
166  
-42  
-213  
-420  
SEG8  
SEG7  
SEG6  
SEG5  
SEG4  
12  
CMOS DOT MATRIX LCD DRIVER  
IZD1520  
13  
厂商 型号 描述 页数 下载

INTEGRAL

 		IZD1520 CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

INTEGRAL

 		IZD1520AA CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

INTEGRAL

 		IZD1520OA CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

INTEGRAL

 		IZD1520U 点阵液晶显示控制器与驱动程序[ DOT MATRIX LIQUID CRYSTAL DISPLAY CONTROLLER & DRIVER ] 12 页

INTEGRAL

 		IZD1521AA CMOS点阵LCD驱动器[ CMOS DOT MATRIX LCD DRIVER ] 13 页

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