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IZ74LV273

型号：

IZ74LV273

描述：

八路D触发器与普通时钟和复位[ Octal D Flip-Flop with Common Clock and Reset ]

品牌：

INTEGRAL[ INTEGRAL CORP. ]

页数：

7 页

PDF大小：

135 K

下载PDF手册
TECHNICAL DATA  
IN74LV273  
Octal D Flip-Flop with Common Clock and Reset  
The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and  
function compatible with the 74HC/HCT273.  
The IN74LV273 has eight edge-triggered, D-type flip-flops with  
individual D inputs and Q outputs. The common clock (CP) and master  
reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The  
N SUFFIX  
PLASTIC DIP  
state of each D input, one set-up time before the LOW-to-HIGH clock  
transition, is transferred to the corresponding output (Qn) of the flip-  
20  
1
DW SUFFIX  
SO  
flop. All outputs will be forced LOW independently of clock or data  
inputs by a LOW voltage level on the MR input. The device is useful for  
applications where the true output only is required and the clock and  
master reset are common to all storage elements.  
20  
1
·
Output voltage levels are compatible with input levels of CMOS,  
NMOS and TTL ICS  
Supply voltage range: 1.2 to 5.5 V  
Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ  
High Noise Immunity Characteristic of CMOS Devices  
ORDERING INFORMATION  
IN74LV273N  
IN74LV273DW  
IZ74LV273  
Plastic DIP  
SOIC  
chip  
·
·
·
TA = -40° to 125° C for all packages  
PIN ASSIGNMENT  
RESET  
Q0  
1
20  
19  
V
CC  
Q7  
LOGIC DIAGRAM  
2
D0  
3
18 D7  
17 D6  
16 Q6  
15 Q5  
14 D5  
13 D4  
12 Q4  
11 CLOCK  
D1  
4
Q1  
5
Q2  
6
D2  
7
D3  
8
Q3  
9
10  
GND  
FUNCTION TABLE  
Inputs  
Clock  
X
Output  
Reset  
D
X
H
L
Q
L
H
H
H
H
L
H
L
L
X
X
no change  
no change  
PIN 20=VCC  
PIN 10 = GND  
H= high level  
L = low level  
X = don’t care  
Z = high impedance  
INTEGRAL  
1
IN74LV273  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to +7.0  
±20  
Unit  
V
VCC  
DC supply voltage  
Input diode current  
Output diode current  
1
IIK  
*
mA  
mA  
mA  
mA  
mA  
mW  
2
IOK  
*
±50  
IO *3  
Output source or sink current  
VCC current  
±25  
ICC  
±50  
IGND  
PD  
GND current  
±50  
Power dissipation per package:  
Plastic DIP *4  
750  
500  
SO *4  
Tstg  
TL  
Storage Temperature  
-65 to +150  
260  
°C  
°C  
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO  
Package) from Case for 4 Seconds  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
1
*
*
V < -0.5 V or V > VCC + 0.5 V.  
I I  
VO < -0.5 V or VO > VCC + 0.5 V.  
2
*3 -0.5 V < VO < VCC + 0.5 V.  
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C  
SO Package: - 8 mW/°C from 70° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
1.2  
0
Max  
5.5  
Unit  
V
VCC  
DC Supply Voltage  
DC Input Voltage  
DC Output Voltage  
V
I
VCC  
V
VO  
TA  
0
VCC  
V
Operating Temperature, All Package Types  
Input Rise and Fall Time (Figure 1)  
-40  
+125  
°C  
ns  
0 V £ VCC £ 2.0 V  
2.0 V £ VCC £ 2.7 V  
2.7 V £ VCC £ 3.6 V  
tr, tf  
0
0
0
0
500  
200  
100  
50  
3.6 V £ VCC £ 5.5 V  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages  
to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range GND£(V or  
IN  
IN  
VOUT)£VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused  
outputs must be left open.  
INTEGRAL  
2
IN74LV273  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
Test  
VCC  
V
Guaranteed Limit  
-40°C 85°C  
max min max  
Symbol Parameter  
conditions  
25°C  
min  
125°C  
Unit  
min  
max min max  
V
IH  
HIGH level  
input  
voltage  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
0.9  
1.4  
2.0  
2.0  
2.0  
-
-
-
-
-
-
-
0.9  
1.4  
2.0  
2.0  
2.0  
-
-
-
-
-
-
-
0.9  
1.4  
2.0  
2.0  
2.0  
-
-
-
-
-
-
-
0.9  
1.4  
2.0  
2.0  
2.0  
-
-
-
-
-
-
-
V
3.15  
3.85  
3.15  
3.85  
3.15  
3.85  
3.15  
3.85  
V
LOW level  
output  
voltage  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
-
-
-
-
-
-
-
0.3  
0.6  
0.8  
0.8  
0.8  
-
-
-
-
-
-
-
0.3  
0.6  
0.8  
0.8  
0.8  
-
-
-
-
-
-
-
0.3  
0.6  
0.8  
0.8  
0.8  
-
-
-
-
-
-
-
0.3  
0.6  
0.8  
0.8  
0.8  
V
V
IL  
1.35  
1.65  
1.35  
1.65  
1.35  
1.65  
1.35  
1.65  
VOH  
HIGH level V = V or V  
IL  
output  
voltage  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
1.05  
1.85  
2.55  
2.85  
3.45  
4.35  
5.35  
-
-
-
-
-
-
-
1.05  
1.85  
2.55  
2.85  
3.45  
4.35  
5.35  
-
-
-
-
-
-
-
1.0  
1.8  
2.5  
2.8  
3.4  
4.3  
5.3  
-
-
-
-
-
-
-
1.0  
1.8  
2.5  
2.8  
3.4  
4.3  
5.3  
-
-
-
-
-
-
-
I
IH  
IO = -100 mÀ  
V = V or V  
IL  
3.0  
2.48  
-
2.48  
-
2.40  
-
2.20  
-
V
V
V
I
IH  
IO = -6 mÀ  
V = V or V  
IL  
4.5  
3.70  
-
3.70  
-
3.60  
-
3.50  
-
I
IH  
IO = -12 mÀ  
LOW level V = V or V  
IL  
VOL  
1.2  
2.0  
2.7  
3.0  
3.6  
4.5  
5.5  
-
-
-
-
-
-
-
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
-
-
-
-
-
-
-
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
0.15  
-
-
-
-
-
-
-
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
-
-
-
-
-
-
-
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
I
IH  
output  
voltage  
IO = 100 mÀ  
V = V or V  
IL  
3.0  
4.5  
5.5  
5.5  
-
-
-
-
-
0.33  
0.40  
±0.1  
8.0  
-
-
-
-
-
0.33  
0.40  
±0.1  
8.0  
-
-
-
-
-
0.40  
0.55  
±1.0  
80  
-
-
-
-
0.50  
V
V
I
IH  
IO = 6 mÀ  
V = V or V  
IL  
0.65  
I
IH  
IO = 12 mÀ  
II  
Input  
current  
V = VCC or 0 V  
I
±1.0 mÀ  
160 mÀ  
0.85 mA  
ICC  
ICC1  
Supply  
current  
V =VCC or 0 V  
I
IO = 0 mÀ  
Additional V = VCC – 0.6V 2.7  
0.2  
0.2  
0.5  
I
supply  
3.6  
current per  
input  
INTEGRAL  
3
IN74LV273  
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=2.5 ns)  
Test  
VCC  
V
Guaranteed Limit  
Symbol  
Parameter  
conditions  
-40°C to  
25°C  
85°C  
125°C  
max  
Unit  
min max  
min  
max min  
tPHL, tPLH Propagation delay , Clock V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
-
-
-
-
-
150  
30  
22  
17  
14  
-
-
-
-
-
150  
32  
24  
19  
16  
-
-
-
-
-
150  
41  
30  
24  
20  
ns  
I
1
to Q  
Figures 1,4  
tPHL  
Propagation delay , Reset V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
-
-
-
-
-
160  
40  
30  
23  
19  
-
-
-
-
-
160  
44  
33  
26  
22  
-
-
-
-
-
160  
56  
41  
33  
28  
ns  
I
1
to Q  
Figures 2,4  
CI  
Input capacitance  
5.0  
5.5  
-
-
6.0*  
40*  
-
-
-
-
-
-
-
-
pF  
pF  
CPD  
Power dissipation  
V = 0 V or VCC  
I
capacitance (per flip-flop)  
* T = 25oC  
TIMING REQUIREMENTS(CL=50 pF, tr=tf=2.5 ns)  
Test  
VCC  
Guaranteed Limit  
Symbol  
Parameter  
conditions  
V
-40°C to  
25°C  
85°C  
125°C  
Unit  
min max  
min  
max min  
max  
Pulse Width, Clock (low or  
high), Reset (low)  
tw  
V = 0 V or V  
Figures 1,2,4  
1.2  
2.0  
2.7  
3.0  
4.5  
60  
28  
21  
16  
12  
-
-
-
-
-
70  
34  
25  
20  
16  
-
-
-
-
-
80  
41  
30  
24  
20  
-
-
-
-
-
ns  
I
1
Setup Time, Data to Clock  
tsu  
trem  
th  
V = 0 V or V  
Figures 3,4  
1.2  
2.0  
2.7  
3.0  
4.5  
40  
18  
13  
11  
9
-
-
-
-
-
50  
22  
16  
13  
11  
-
-
-
-
-
60  
26  
19  
15  
13  
-
-
-
-
-
ns  
ns  
ns  
I
1
Removal Time, Reset to  
Clock  
V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
5
5
5
5
5
-
-
-
-
-
5
5
5
5
5
-
-
-
-
-
5
5
5
5
5
-
-
-
-
-
I
1
Figures 2,4  
Hold Time, Clock to Data  
V = 0 V or V  
1.2  
2.0  
2.7  
3.0  
4.5  
50  
5
5
5
5
-
-
-
-
-
50  
5
5
5
5
-
-
-
-
-
50  
5
5
5
5
-
-
-
-
-
I
1
Figures 3,4  
INTEGRAL  
4
IN74LV273  
Clock Frequency  
fc  
V = 0 V or V  
Figures 1,4  
1.2  
2.0  
2.7  
3.0  
4.5  
-
-
-
-
-
2
-
-
-
-
-
1
-
-
-
-
-
1
MHz  
I
1
17  
23  
30  
32  
14  
19  
24  
27  
12  
16  
20  
24  
VOL and VOH are the typical output voltage drop that occur with the output load.  
Figure 1. Switching Waveforms  
Figure 2. Switching Waveforms  
INTEGRAL  
5
IN74LV273  
Figure 3. Switching Waveforms  
Level of a signal, V  
Symbol  
1,2  
1,2  
0,6  
2,0  
2,0  
1,0  
2,7  
2,7  
1,5  
3,0  
2,7  
1,5  
4,5  
4,5  
VCC  
V
1
2,25  
VM  
TEST POINT  
DEVICE  
OUTPUT  
UNDER  
TEST  
*
L
C
* Includes all probe and jig capacitance  
Figure 4. Test Circuit  
EXPANDED LOGIC DIAGRAM  
INTEGRAL  
6
IN74LV273  
CHIP PAD DIAGRAM  
17  
15  
18  
16  
13  
14  
19  
20  
12  
11  
01  
10  
09  
Chip marking  
25LV273  
02  
03  
04  
06  
08  
05  
07  
Y
(0,0)  
1.48 + 0.03  
X
Location of marking (mm): left lower corner x=0.119, y=0.082.  
Chip thickness: 0.46 ± 0.02 mm, (0.35 ± 0.02 mm – for SOIC).  
PAD LOCATION  
Location (left lower corner), mm  
Pad No  
Symbol  
Pad size, mm  
X
0.1415  
0.1415  
0.1375  
0.4535  
0.6245  
0.7800  
0.9520  
1.2685  
1.2480  
1.2650  
1.2650  
1.2425  
1.2465  
0.9520  
0.7800  
0.6245  
0.4535  
0.1160  
0.1440  
0.1190  
Y
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Reset  
Q 0  
D 0  
D 1  
Q 1  
Q 2  
D 2  
D 3  
Q 3  
GND  
Clock  
Q 4  
D 4  
D 5  
Q 5  
Q 6  
D 6  
D 7  
Q 7  
VCC  
0.6270  
0.3880  
0.1515  
0.1190  
0.1190  
0.1190  
0.1180  
0.1185  
0.2960  
0.5160  
0.8430  
1.0820  
1.3165  
1.3120  
1.3110  
1.3110  
1.3110  
1.3115  
1.1350  
0.9140  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
0.100 x0.100  
Note: Pad location is given as per passivation layer.  
INTEGRAL  
7
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