TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VIN = 15VDC, ILOAD = ±15mA unless otherwise noted.
THE OUTPUT VOLTAGE CAN BE ADJUSTED
±3% BY VARYING THE DRIVER FREQUENCY
OUTPUT VOLTAGE DRIFT WITH A ±15mA LOAD
15.5
16
15.5
15.25
15
15
14.5
14
14.75
14.5
1
1.5
1.6
2
–25
0
25
50
75
100
TTLIN Frequency (MHz)
Temperature (°C)
THEORY OF OPERATION
The PWS750 components are basic building blocks to be
used with other standard components to build an isolated
push-pull DC/DC converter. The oscillator runs at 800kHz
nominal, making it possible to reduce the size of the trans-
former and lower the output ripple voltage.
During overload conditions the output drive shuts off for
approximately 80µs, then turns back on for 20µs, resulting
in a 25% power up duty cycle. If the overload condition still
exists, then the output will shut off again. When the fault or
the excessive load is removed, the converter resumes normal
operation.
PWS750-1U OSCILLATOR PIN FUNCTIONS
The T and T pins are the complementary FET drive outputs
and are tied directly to the corresponding FET gate. The
connection must be as short as possible. For multiple chan-
nel operation they cannot be located above any ground or
power planes, because capacitive loading will not allow fast
enough charging of the FET gate.
TTLIN is used to control the driver frequency with an
external TTL level frequency source. The input frequency
must be twice the desired driver frequency, since there is an
internal divide-by-2 circuit to produce a 50% duty cycle
output. The input duty cycle can vary from 12% to 95% (see
Typical Performance Curves). When in the free running
mode, the TTLIN pin must be tied to ground.
PWS750-2U AND PWS750-4U
TRANSFORMER PIN FUNCTIONS
TTLOUT is used when it is desired to synchronize the outputs
of multiple PWS750-1Us to minimize beat frequency prob-
lems. A standard open collector output is provided, therefore
a 330Ω to 3.3kΩ pull-up resistor will be necessary depend-
ing on stray capacitance on the sync line. A maximum of
eight PWS750-1Us can be connected without the use of an
external TTL buffer.
On the primary side the VD pin of the PWS750-2U is tied
directly to the VD pin of the PWS750-1U. Remember to
place a 0.1µF capacitor as close to the PWS750-2U VD pin
as possible. The TO and TO pins are connected to the drains
of the corresponding FETs, whose sources are connected to
ground. On the secondary side of the transformer, the Gnd
pin is tied directly to the isolated ground. AC pins are
800kHz square wave signals at twice the output voltage, and
are connected directly to the corresponding pin on the
PWS750-3U. Pins 2 and 4 can be interchanged for ease of
hook up. The connection to the diode bridge must be as
direct as possible to minimize radiated noise.
An Enable pin is provided so that the driver (T, T) can be
shut down to minimize power use if required. A TTL low
applied to the pin will shut down the driver within one cycle.
A TTL high will enable the driver within one cycle. The
TTLOUT will still have an 800kHz signal when a master
driver is disabled, so other synchronized drivers will not be
shut down. The pin can be left open for normal operation.
The winding ratio for the PWS750-2U is 1:1. This means
that the output would normally be less than the input due to
voltage drops in the FETs, transformer and diode bridge.
Since the DC/DC converter is operating at 800kHz, the
transformer is starting to operate close to the resonant
frequency, which causes the output to increase in magni-
tude.
The +VIN pin supplies power to the oscillator. The VD pin
connects the power to the transformer through the internal
overcurrent sense resistor. The other end of the overcurrent
sense resistor is tied to +VIN. A 0.3µF bypass capacitor must
be connected to the VD pin to reduce the ripple current
through the shunt resistor; otherwise false current limit
conditions can occur due to ripple voltage peaks.
®
5
PWS750
