3.3V 1M x 64-Bit SDRAM Module
3.3V 1M x 72-Bit SDRAM Module
HYS64V1000GS-10/-12/-15
HYS72V1000GS-10/-12/-15
168 pin unbuffered DIMM Modules
Target Information
• 168 Pin JEDEC Standard, Unbuffered 8 Byte
Dual-In-Line SDRAM Module
• 1 bank 1M x 64, 1M x 72 organisation
• Optimized for byte-write non-parity or ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Performance:
-10
-12
83
-15
66
Units
fCK
Clock frequency
Clock cycle time
100
MHz
ns
tCK3
tAC3
10
9
12
11
15
13
Clock access time
CAS latency = 3
ns
• Single +3.3V(± 0.3V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial presence detects
• Utilizes four / five 1M x 16 SDRAMs in TSOPII-50 packages
• 4096 refresh cycles every 64 ms
• Gold contact pad
• Card Size: 133,35mm x 25,40mm x 3,00 mm
• This SDRAM product familiy is intended to be fully pin and architecture compatible with the 168
pin Unbuffered DRAM DIMM module family.
Semiconductor Group
1
4.96