CYRF7936
and 2.7V. VREG may be used to provide up to 15 mA (average
load) to external devices. It is possible to disable the PMU and
provide an externally regulated DC supply voltage to the device’s
main supply in the range 2.4V to 3.6V. The PMU also provides a
regulated 1.8V supply to the logic.
Interrupts
The device provides an interrupt (IRQ) output, which is
configurable to indicate the occurrence of different events. The
IRQ pin may be programmed to be either active HIGH or active
LOW, and be either a CMOS or open drain output. The available
interrupts are described in the section Register Descriptions on
page 12.
The PMU is designed to provide high boost efficiency (74–85%
depending on input voltage, output voltage, and load) when
using a Schottky diode and power inductor, eliminating the need
for an external boost converter in many systems where other
components require a boosted voltage. However, reasonable
efficiencies (69–82% depending on input voltage, output voltage,
and load) may be achieved when using low cost components
such as SOT23 diodes and 0805 inductors.
The CYRF7936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled or disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is necessary
to read the relevant status register to determine which event
caused the IRQ pin to assert. Even when a given interrupt source
is disabled, the status of the condition that would otherwise
cause an interrupt can be determined by reading the appropriate
status register. It is therefore possible to use the devices without
the IRQ pin, by polling the status registers to wait for an event,
rather than using the IRQ pin.
The current through the diode must stay within the linear
operating range of the diode. For some loads the SOT23 diode
is sufficient, but with higher loads it is not and a SS12 diode must
be used to stay within this linear range of operation. Along with
the diode, the inductor used must not saturate its core. In higher
loads, a lower resistance/higher saturation coil such as the
inductor from Sumida must be used.
The PMU also provides a configurable low battery detection
function, which may be read over the SPI interface. One of seven
thresholds between 1.8V and 2.7V may be selected. The
interrupt pin may be configured to assert when the voltage on the
VBAT pin falls below the configured threshold. LV IRQ is not a
latched event. Battery monitoring is disabled when the device is
in sleep mode.
Clocks
A 12 MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external
capacitors. A digital clock out function is provided, with
selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This
output may be used to clock an external microcontroller (MCU)
or ASIC. This output is enabled by default, but may be disabled.
Receiver Front End
The requirements to directly connect the crystal to the XTAL pin
and GND are:
The gain of the receiver can be controlled directly by writing to
the Low Noise Amplifier (LNA) bit and the Attenation (ATT) bit of
the RX_CFG_ADR register. Clearing the LNA bit reduces the
receiver gain approximately 20 dB, allowing accurate reception
of very strong received signals (for example, when operating a
receiver very close to the transmitter). Approximately 30 dB of
receiver attenuation can be added by setting the Attenuation
(ATT) bit. This limits data reception to devices at very short
ranges. Enabling LNA is recommended, unless receiving from a
device using external PA.
■ Nominal Frequency: 12 MHz
■ Operating Mode: Fundamental Mode
■ Resonance Mode: Parallel Resonant
■ Frequency Stability: ±30 ppm
■ Series Resistance: <60 ohms
■ Load Capacitance: 10 pF
When the device is in receive mode the RSSI_ADR register
returns the relative signal strength of the on-channel signal
power.
■ Drive Level: 100 µW
Power Management
When receiving, the device automatically measures and stores
the relative strength of the signal being received as a five bit
value. An RSSI reading is taken automatically when the SOP is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI_ADR register. This
allows the background RF energy level on any given channel to
be easily measured when RSSI is read while no signal is being
received. A new reading can occur as fast as once every 12 µs.
The operating voltage of the device is 1.8V to 3.6V DC, which is
applied to the VBAT pin. The device can be shut down to a fully
static sleep mode by writing to the FRC END = 1 and
END STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 µs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing the packet transmission or
reception. When in sleep mode, the on-chip oscillator is stopped,
but the SPI interface remains functional. The device wakes from
sleep mode automatically when the device is commanded to
enter transmit or receive mode. When resuming from sleep
mode, there is a short delay while the oscillator restarts. The
device can be configured to assert the IRQ pin when the
oscillator has stabilized.
The output voltage (VREG) of the Power Management Unit
(PMU) is configurable to several minimum values between 2.4V
Document Number: 001-48013 Rev*B
Page 7 of 21
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