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HYS64D16020GDL-8-A

型号：

HYS64D16020GDL-8-A

描述：

无缓冲DDR SDRAM SO模块[ Unbuffered DDR SDRAM SO Modules ]

品牌：

INFINEON[ Infineon ]

页数：

22 页

PDF大小：

665 K

下载PDF手册
Data Sheet, Rev. 1.02, Jan. 2004  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
DDR SDRAM SO  
Memory Products  
N e v e r s t o p t h i n k i n g .  
Edition 2004-01  
Published by Infineon Technologies AG,  
St.-Martin-Strasse 53,  
E
81669 München, Germany  
P
© Infineon Technologies AG 2004.  
S
All Rights Reserved.  
8
©Attentionplease!
A
The information herein is given to describe certain components and shall not be considered as a guarantee of  
characteristics.  
A
Terms of delivery and rights to technical change reserved.  
T
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding  
c
circuits, descriptions and charts stated herein.  
T
Infineon Technologies is an approved CECC manufacturer.  
W
c
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
I
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide  
F(www.infineon.com).
I
Warnings  
W
Due to technical requirements components may contain dangerous substances. For information on the types in  
D
question please contact your nearest Infineon Technologies Office.  
q
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
In  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the  
afailureofthatlife-supportdeviceorsystem, ortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifee  
ot  
support devices or systems are intended to be implanted in the human body, or to support and/or maintain and  
d
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other  
apersonsmaybeendangered.
b
Data Sheet, Rev. 1.02, Jan. 2004  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
DDR SDRAM SO  
Memory Products  
N e v e r s t o p t h i n k i n g .  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
HYS64D16020GD(L)-[7/8]-A  
Revision History:  
Rev. 1.02  
Rev. 1.01  
2004-01  
Previous Version:  
Page  
all  
Subjects (major changes since last revision)  
Editorial Changes ; final revision  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc.mp@infineon.com  
Data Sheet  
4
Rev. 1.02, 2004-01  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
3.1  
3.2  
3.3  
4
5
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Data Sheet  
5
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Overview  
1
Overview  
1.1  
Features  
•
•
•
•
•
•
•
•
•
•
•
•
200-pin Unbuffered 8-Byte Dual-In-Line DDR SDRAM non-parity Small Outline Modules  
One rank 16M x 64 organization  
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)  
Single + 2.5 V (± 0.2 V) power supply  
Built with 128 Mbit DDR SDRAMs organised as x 16 in 66-Lead TSOPII packages  
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)  
Auto Refresh (CBR) and Self Refresh  
All inputs and outputs SSTL_2 compatible  
Serial Presence Detect with E2PROM  
JEDEC standard form factor: 67.60 mm × 31.75 mm × 3.00 / 3.80 mm  
JEDEC standard reference layout Raw Card A  
Gold plated contacts  
Table 1  
Performance -8/-7  
Part Number Speed Code  
–7  
–8  
Unit  
—
Speed Grade  
Component  
Module  
DDR266A  
PC2100-2033  
143  
DDR200  
PC1600-2022  
125  
—
max. Clock Frequency  
@CL2.5  
@CL2  
fCK2.5  
fCK2  
MHz  
MHz  
133  
100  
1.2  
Description  
The HYS64/72D16000GU and HYS64/72D32020GU are industry standard 184-pin 8-byte Dual in-line Memory  
Modules (DIMMs) organized as 16M x 64 and 32M × 64 for non-parity and 16M x 72 and 32M x 72 for ECC main  
memory applications. The memory array is designed with 128Mbit Double Data Rate Synchronous DRAMs. A  
variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based  
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration  
data and the second 128 bytes are available to the customer.  
Data Sheet  
6
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Overview  
Table 2  
Type  
Ordering Information  
Compliance Code  
PC2100-20330-A  
PC1600-20220-A  
Description  
SDRAM Technology  
PC2100 (CL=2):  
HYS64D16020GDL-7-A  
two ranks 128 MB SO-DIMM 128 Mbit (x16)  
PC1600 (CL=2):  
HYS64D16020GDL-8-A  
two ranks 128 MB SO-DIMM 128 Mbit (x16)  
Note: All part numbers end with a place code, designating the silicon-die revision. Reference information available  
on request. Example: HYS 64D32020GDL-8-B, indicating Rev.B die are used for DDR-SDRAM  
components. The Compliance Code which is printed on the module labels describes the speed sort class  
(“for example PC2100”), the latencies (for example 20330 means CAS latency = 2, trcd latency = 3 and trp  
latency = 3) and the Raw Card used for this module  
Data Sheet  
7
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Pin Configuration  
2
Pin Configuration  
Table 3  
Pin Definitions and Functions  
Symbol  
Type1)  
Function  
A0 - A11  
BA0, BA1  
DQ0 - DQ63  
CB0 - CB7  
I
Address Inputs  
I
Bank Selects  
I/O  
I/O  
Data Input/Output  
Check Bits (×72 organization only)  
Command Inputs  
RAS, CAS, WE  
CKE0 - CKE1  
DQS0 - DQS8  
CK0 - CK2,  
I
I
Clock Enable  
I/O  
SDRAM low data strobes  
SDRAM clock (positive lines)  
SDRAM clock (negative lines)  
I
I
CK0 - CK2  
DM0 - DM8  
DQS9 - DQS17  
I
SDRAM low data mask/  
high data strobes  
I/O  
S0, S1  
VDD  
I
Chip Selects for Rank0 and Rank1  
Power (+2.5 V)  
PWR  
GND  
PWR  
PWR  
AI  
VSS  
Ground  
VDDQ  
VDDID  
VREF  
I/O Driver power supply  
VDD Indentification flag  
I/O reference supply  
Serial EEPROM power supply  
Serial bus clock  
VDDSPD  
SCL  
PWR  
I
SDA  
I/O  
Serial bus data line  
slave address select  
Not Connected  
SA0 - SA2  
NC  
I
NC  
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not  
Connected  
Note: S1 and CKE1 are used on two rank modules only  
Data Sheet  
8
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Pin Configuration  
Table 4  
Pin Configuration  
PIN#  
Frontside  
Backside  
PIN#  
Symbol  
Symbol  
PIN#  
Symbol  
PIN#  
Symbol  
1
VREF  
48  
A0  
93  
VSS  
140  
NC /  
DM8/DQS17  
2
DQ0  
VSS  
49  
50  
51  
52  
NC / CB2  
VSS  
94  
DQ4  
141  
142  
143  
144  
A10  
3
95  
DQ5  
NC / CB6  
VDDQD  
4
DQ1  
DQS0  
DQ2  
VDD  
NC / CB3  
BA1  
96  
VDDQD  
DM0/DQS9  
DQ6  
5
97  
NC / CB7  
Key  
6
Key  
98  
7
99  
DQ7  
8
DQ3  
NC  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DQ32  
VDDQ  
DQ33  
DQS4  
DQ34  
VSS  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
VSS  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
VSS  
9
NC  
DQ36  
DQ37  
VDD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
NC  
NC  
VSS  
NC  
DQ8  
DQ9  
DQS1  
VDDQ  
CK1  
CK1  
VSS  
VDDQ  
DM4/DQS13  
DQ38  
DQ39  
VSS  
DQ12  
DQ13  
DM1/DQS10  
VDD  
BA0  
DQ35  
DQ40  
VDDQ  
WE  
DQ44  
RAS  
DQ14  
DQ15  
CKE1  
VDDQ  
DQ45  
VDDQ  
DQ10  
DQ11  
CKE0  
VDDQ  
DQ16  
DQ17  
DQS2  
VSS  
DQ41  
CAS  
VSS  
S0  
NC (BA2)  
DQ20  
NC / A12  
VSS  
S1  
DQS5  
DQ42  
DQ43  
VDD  
DM5/DQS14  
VSS  
DQ46  
DQ47  
NC  
DQ21  
A11  
NC  
A9  
DQ48  
DQ49  
VSS  
DM2/DQS11  
VDD  
VDDQ  
DQ18  
A7  
DQ52  
DQ53  
NC (A13)  
VDD  
DQ22  
A8  
VDDQ  
DQ19  
A5  
CK2  
CK2  
DQ23  
VSS  
VDDQ  
DQS6  
DQ50  
DQ51  
VSS  
DM6/DQS15  
DQ54  
DQ55  
VDDQ  
DQ24  
VSS  
A6  
DQ28  
DQ29  
VDDQ  
DQ25  
DQS3  
A4  
NC  
VDDID  
DQ56  
DQ57  
DM3/DQS12  
A3  
DQ60  
DQ61  
VSS  
VDD  
DQ26  
DQ30  
Data Sheet  
9
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Pin Configuration  
Table 4  
Pin Configuration (cont’d)  
Frontside  
Backside  
PIN#  
40  
Symbol  
PIN#  
85  
Symbol  
PIN#  
132  
133  
134  
135  
136  
137  
138  
139  
Symbol  
VSS  
PIN#  
177  
178  
179  
180  
181  
182  
183  
184  
Symbol  
DM7/DQS16  
DQ62  
DQ63  
VDDQ  
DQ27  
A2  
VDD  
41  
86  
DQS7  
DQ58  
DQ59  
VSS  
DQ31  
NC / CB4  
NC / CB5  
VDDQ  
42  
VSS  
87  
43  
A1  
88  
44  
NC / CB0  
NC / CB1  
VDD  
89  
SA0  
45  
90  
NC  
CK0  
SA1  
46  
91  
SDA  
SCL  
CK0  
SA2  
47  
NC / DQS8  
92  
VSS  
VDDSPD  
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on ×64 organised non-ECC  
modules.  
Table 5  
Address Format  
Density Organization Memory SDRAMs # of  
SDRAM # of  
Refresh Period Interval  
Ranks  
SDRAMs density row/rank/  
columns  
bits  
128 MB 16M × 64  
2
8M × 16  
8
128Mbit 12/2/9  
4K  
64 ms 15.6 µs  
Note: Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 89 and 91 are reserved for x72 variants of this module and are  
not used on the x64 versions. Pin 86 is reserved for a registered variant of this module and is not used on  
the unbuffered version  
front side  
back side  
Figure 1  
Pin Configuration  
Data Sheet  
10  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Pin Configuration  
S1  
S0  
S
S
S
S
DQS0  
DM0  
LDQS  
LDM  
LDQS  
LDM  
DQS4  
DM4  
LDQS  
LDM  
LDQS  
LDM  
DQ32  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
D2  
D6  
D4  
D0  
I/O 5  
I/O 6  
I/O 7  
UDQS  
UDM  
I/O 8  
UDQS  
UDM  
I/O 8  
UDQS  
UDM  
I/O 8  
UDQS  
UDM  
I/O 8  
DQS1  
DM1  
DQS5  
DM5  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
I/O 9  
I/O 9  
I/O 9  
I/O 9  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
S
LDQS  
LDM  
S
S
S
DQS2  
DM2  
LDQS  
LDM  
DQS6  
DM6  
LDQS  
LDM  
LDQS  
LDM  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
7
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
7
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
D5  
D1  
D3  
D7  
I/O 5  
I/O 6  
I/O 7  
DQS3  
DM3  
UDQS  
UDM  
I/O 8  
UDQS  
UDM  
I/O 8  
UDQS  
UDM  
I/O 8  
UDQS  
UDM  
DQS7  
DM7  
Serial Presence Detect (SPD)  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O  
I/O  
8
9
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 9  
I/O 9  
I/O 9  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
SCL  
SA0  
SA1  
SA2  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
A0  
A1  
A2  
SDA  
WP  
#Unless otherwise noted, resistor values are 22 Ω ± 5%  
SDRAMS D0-D7  
CK0  
CK0  
4 loads  
4 loads  
BA0-BA1  
A0-An  
RAS  
SDRAMS D0-D7  
SDRAMS D0-D7  
SDRAMS D0-D7  
SDRAMS D0-D7  
CK1  
CK1  
CAS  
WE  
CK2  
CK2  
SDRAMS D0-D3  
SDRAMS D4-D7  
0 loads  
CKE0  
CKE1  
SPD  
SDRAMS D0-D7  
VDDSPD  
VREF  
Note: DQ wiring may differ from that described  
in this drawing; however DQ/DM/DQS  
relationships are maintained as shown.  
VDDID strap connections:  
VDD and VDD  
Q
SDRAMS D0-D7  
VDD  
(for memory device VDD, VDDQ)  
Strap out (open): VDD = VDD  
Q
Q
SDRAMS D0-D7, SPD  
VSS  
Strap in (closed): VDD VDD  
≠
VDDID  
Figure 2  
Block Diagram: Two Rank 16M x 64 DDR-SDRAM SO-DIMM Modules using x16 Organized  
128Mbit SDRAMs on Raw Card Version A  
Data Sheet  
11  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Electrical Characteristics  
3
Electrical Characteristics  
3.1  
Operating Conditions  
Table 6  
Absolute Maximum Ratings  
Parameter  
Symbol  
Values  
typ.  
–
Unit Note/ Test  
Condition  
min.  
VIN, VOUT –0.5  
max.  
Voltage on I/O pins relative to VSS  
VDDQ  
+
V
–
0.5  
Voltage on inputs relative to VSS  
Voltage on VDD supply relative to VSS  
Voltage on VDDQ supply relative to VSS  
Operating temperature (ambient)  
Storage temperature (plastic)  
VIN  
–0.5  
–0.5  
–0.5  
0
–
+3.6  
+3.6  
+3.6  
+70  
+150  
–
V
–
–
–
–
–
–
–
VDD  
VDDQ  
TA  
–
V
–
V
–
°C  
°C  
W
mA  
TSTG  
PD  
-55  
–
–
Power dissipation (per SDRAM component)  
Short circuit output current  
2.0  
50  
IOUT  
–
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This  
is a stress rating only, and functional operation should be restricted to recommended operation  
conditions. Exposure to absolute maximum rating conditions for extended periods of time may  
affect device reliability and exceeding only one of the values may cause irreversible damage to  
the integrated circuit.  
Data Sheet  
12  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Electrical Characteristics  
Table 7  
Electrical Characteristics and DC Operating Conditions  
Parameter  
Symbol  
Values  
Typ.  
Unit Note/Test Condition 1)  
Min.  
2.3  
Max.  
2.7  
2.7  
3.6  
0
Device Supply Voltage  
Output Supply Voltage  
EEPROM supply voltage  
VDD  
2.5  
2.5  
2.5  
V
2)  
VDDQ  
2.3  
V
VDDSPD 2.3  
V
V
—
—
Supply Voltage, I/O Supply VSS,  
0
Voltage  
VSSQ  
VREF  
VTT  
3)  
4)  
Input Reference Voltage  
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ  
V
I/O Termination Voltage  
(System)  
V
REF – 0.04  
V
REF + 0.04 V  
7)  
7)  
7)  
Input High (Logic1) Voltage VIH(DC)  
Input Low (Logic0) Voltage VIL(DC)  
V
REF + 0.15  
V
V
V
DDQ + 0.3  
V
–0.3  
REF – 0.15 V  
Input Voltage Level,  
CK and CK Inputs  
VIN(DC) –0.3  
DDQ + 0.3  
DDQ + 0.6  
V
7)5)  
6)  
Input Differential Voltage, VID(DC) 0.36  
CK and CK Inputs  
V
V
VI-Matching Pull-up  
Current to Pull-down  
Current  
VIRatio  
0.71  
–2  
1.4  
2
—
Input Leakage Current  
II  
µA Any input 0 V ≤ VIN ≤ VDD;  
All other pins not under test  
= 0 V 7)8)  
Output Leakage Current  
IOZ  
IOH  
IOL  
–5  
5
µA DQs are disabled;  
7)  
0 V ≤ VOUT ≤ VDDQ  
Output High Current,  
Normal Strength Driver  
—
–16.2  
—
mA  
mA  
V
OUT = 1.95 V 7)  
OUT = 0.35 V 7)  
Output Low  
16.2  
V
Current, Normal Strength  
Driver  
1) 0 °C ≤ TA ≤ 70 °C  
2) Under all conditions, VDDQ must be less than or equal to VDD  
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ  
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal  
to VREF, and must track variations in the DC level of VREF  
.
.
.
5) VID is the magnitude of the difference between the input level on CK and the input level on CK.  
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire  
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the  
maximum difference between pull-up and pull-down drivers due to process variation.  
7) Inputs are not recognized as valid until VREF stabilizes.  
8) Values are shown per component  
Data Sheet  
13  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Electrical Characteristics  
3.2  
Current Specification and Conditions  
Table 8  
IDD Conditions  
Parameter  
Symbol  
Operating Current 0  
IDD0  
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;  
address and control inputs changing once every two clock cycles.  
Operating Current 1  
IDD1  
one bank; active/read/precharge; Burst Length = 4; see component data sheet.  
Precharge Power-Down Standby Current  
all banks idle; power-down mode; CKE ≤ VIL,MAX  
IDD2P  
IDD2F  
Precharge Floating Standby Current  
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN  
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.  
Precharge Quiet Standby Current  
IDD2Q  
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;  
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX  
.
Active Power-Down Standby Current  
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.  
IDD3P  
IDD3N  
Active Standby Current  
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX  
DQ, DM and DQS inputs changing twice per clock cycle;  
address and control inputs changing once per clock cycle.  
;
Operating Current Read  
IDD4R  
one bank active; Burst Length = 2; reads; continuous burst;  
address and control inputs changing once per clock cycle;  
50% of data outputs changing on every clock edge;  
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA  
Operating Current Write  
IDD4W  
one bank active; Burst Length = 2; writes; continuous burst;  
address and control inputs changing once per clock cycle;  
50% of data outputs changing on every clock edge;  
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B  
Auto-Refresh Current  
IDD5  
IDD6  
IDD7  
t
RC = tRFCMIN, burst refresh  
Self-Refresh Current  
CKE ≤ 0.2 V; external clock on  
Operating Current 7  
four bank interleaving with Burst Length = 4; see component data sheet.  
Data Sheet  
14  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Electrical Characteristics  
Table 9  
IDD Specification and Conditions -8/-7  
Unit  
Note 1)2)  
128MB  
×64  
–8  
–7  
Symbol  
IDD0  
max.  
480  
540  
36  
max.  
540  
620  
40  
3)  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
3)4)  
5)  
IDD1  
IDD2P  
IDD2F  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
5)  
280  
280  
120  
280  
500  
520  
860  
12  
360  
360  
120  
360  
620  
620  
940  
12  
5)  
5)  
5)  
3)4)  
3)  
3)  
5)  
IDD6  
3)4)  
IDD7  
1220  
1300  
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading  
capacity.  
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C  
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:  
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules  
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)  
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]  
Data Sheet  
15  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Electrical Characteristics  
3.3  
AC Characteristics  
Table 10  
AC Timing - Absolute Specifications –8/–7  
Parameter  
Symbol  
–8  
–7  
Unit  
Note/  
Test Condition 1)  
DDR200  
DDR266A  
Min Max.  
.
Min.  
Max.  
+0.75  
+0.75  
0.55  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
DQ output access time from CK/CK  
DQS output access time from CK/CK  
CK high-level width  
tAC  
–
+0.8  
–0.75  
–0.75  
0.45  
ns  
ns  
tCK  
tCK  
0.8  
tDQSCK  
tCH  
–
+0.8  
0.8  
0.4 0.55  
5
CK low-level width  
tCL  
0.4 0.55  
5
0.45  
0.55  
Clock Half Period  
Clock cycle time  
tHP  
min. (tCL, tCH)  
min. (tCL, tCH)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK2.5  
tCK2  
tCK1.5  
tDH  
8
12  
7
12  
CL = 2.5 2)3)4)5)  
CL = 2.0 2)3)4)5)  
CL = 1.5 2)3)4)5)  
10 12  
10 12  
7.5  
—
12  
—
—
—
—
2)3)4)5)  
DQ and DM input hold time  
DQ and DM input setup time  
0.6  
0.6  
2.5  
—
—
—
0.5  
0.5  
2.2  
2)3)4)5)  
tDS  
2)3)4)5)6)  
Control and Addr. input pulse width  
(each input)  
tIPW  
2)3)4)5)6)  
2)3)4)5)7)  
2)3)4)5)7)  
2)3)4)5)  
DQ and DM input pulse width (each  
input)  
tDIPW  
tHZ  
2.0  
—
1.75  
–0.75  
–0.75  
0.75  
—
—
ns  
ns  
ns  
tCK  
ns  
Data-out high-impedance time from  
CK/CK  
–
0.8  
+0.8  
+0.8  
+0.75  
+0.75  
1.25  
+0.5  
Data-out low-impedance time from  
CK/CK  
Write command to 1st DQS latching  
tLZ  
–
0.8  
tDQSS  
tDQSQ  
0.7 1.25  
5
transition  
2)3)4)5)  
DQS-DQ skew (DQS and associated  
DQ signals)  
—
+0.6  
2)3)4)5)  
2)3)4)5)  
Data hold skew factor  
tQHS  
tQH  
—
1.0  
—
—
0.75  
—
ns  
ns  
DQ/DQS output hold time  
tHP  
–
tQHS  
tHP –  
tQHS  
0.35  
0.2  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
DQS input low (high) pulse width (write tDQSL,H 0.3  
cycle)  
—
—
—
—
—
—
tCK  
tCK  
tCK  
5
DQS falling edge to CK setup time (write tDSS  
cycle)  
0.2  
DQS falling edge hold time from CK  
(write cycle)  
tDSH  
0.2  
0.2  
2)3)4)5)  
Mode register set command cycle time tMRD  
2
0
—
—
2
—
tCK  
ns  
2)3)4)5)8)  
2)3)4)5)9)  
Write preamble setup time  
Write postamble  
tWPRES  
tWPST  
0
—
0.4 0.60  
0
0.40  
0.60  
tCK  
Data Sheet  
16  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Electrical Characteristics  
Table 10  
AC Timing - Absolute Specifications –8/–7  
Parameter  
Symbol  
–8  
–7  
Unit  
Note/  
Test Condition 1)  
DDR200  
DDR266A  
Min Max.  
.
Min.  
Max.  
2)3)4)5)  
Write preamble  
tWPRE  
tIS  
0.2  
5
—
—
—
—
—
0.25  
0.9  
1.0  
0.9  
1.0  
—
tCK  
ns  
ns  
ns  
ns  
Address and control input setup time  
1.1  
1.1  
1.1  
1.1  
—
fast slew rate  
3)4)5)6)10)  
—
slow slew rate  
3)4)5)6)10)  
Address and control input hold time  
tIH  
—
fast slew rate  
3)4)5)6)10)  
—
slow slew rate  
3)4)5)6)10)  
Read preamble  
tRPRE  
0.9 1.1  
0.9  
NA  
1.1  
tCK  
tCK  
ns  
CL > 1.5 2)3)4)5)  
CL = 1.5 2)3)4)5)11)  
tRPRE1.5 0.9 1.1  
tRPRES 1.5  
tRPST  
2)3)4)5)12)  
Read preamble setup time  
Read postamble  
—
NA  
2)3)4)5)  
0.4 0.60  
0
0.40  
0.60  
tCK  
2)3)4)5)  
2)3)4)5)  
Active to Precharge command  
tRAS  
50 120E+3 45  
120E+3 ns  
Active to Active/Auto-refresh command tRC  
70  
—
65  
—
ns  
period  
2)3)4)5)  
Auto-refresh to Active/Auto-refresh  
command period  
tRFC  
80  
—
75  
—
ns  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
2)3)4)5)  
Active to Read or Write delay  
Precharge command period  
Active to Autoprecharge delay  
tRCD  
tRP  
tRAP  
tRRD  
20  
20  
20  
15  
—
—
—
—
20  
20  
20  
15  
—
—
—
—
ns  
ns  
ns  
ns  
Active bank A to Active bank B  
command  
2)3)4)5)  
Write recovery time  
tWR  
15  
—
15  
—
ns  
2)3)4)5)13)  
Auto precharge write recovery +  
precharge time  
tDAL  
(twr/tCK) + (trp/tCK)  
tCK  
Internal write to read command delay  
tWTR  
1
—
—
—
1
—
—
—
—
7.8  
tCK  
tCK  
ns  
CL > 1.5 2)3)4)5)  
CL = 1.5 2)3)4)5)  
tWTR1.5  
2
—
75  
200  
—
2)3)4)5)  
Exit self-refresh to non-read command tXSNR  
80  
2)3)4)5)  
Exit self-refresh to read command  
Average Periodic Refresh Interval  
tXSRD  
tREFI  
200 —  
7.8  
tCK  
µs  
2)3)4)5)14)  
—
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V  
2) Input slew rate ≥ 1 V/ns for DDR266, and = 1 V/ns for DDR200  
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference  
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.  
4) Inputs are not recognized as valid until VREF stabilizes.  
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.  
6) These parameters guarantee device timing, but they are not necessarily tested on each device.  
Data Sheet  
17  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
Electrical Characteristics  
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred  
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).  
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.  
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were  
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,  
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS  
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but  
system performance (bus turnaround) degrades accordingly.  
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,  
measured between VOH(ac) and VOL(ac)  
.
11) CAS Latency 1.5 operation is supported on DDR200 devices only  
12) tRPRES is defined for CL = 1.5 operation only  
13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock  
cycle time.  
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.  
Data Sheet  
18  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
SPD Contents  
4
SPD Contents  
Table 11  
Byte#  
SPD Codes for PC2100 & PC1600  
Description  
128MB  
x64  
128MB  
x64  
2ranks  
–7  
2ranks  
–8  
HEX.  
80  
HEX.  
80  
0
1
2
3
4
5
6
7
8
9
10  
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
256  
08  
08  
DDR-SDRAM  
07  
07  
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Ranks  
Module Data Width  
12  
0C  
09  
0C  
09  
9
2
02  
02  
×64  
40  
40  
Module Data Width (cont’d)  
Module Interface Levels  
0
00  
00  
SSTL_2.5  
04  
04  
SDRAM Cycle Time at CL = 2.5 7 ns/8 ns  
70  
80  
Access Time from Clock at  
CL = 2.5  
0.75 ns/0.8 ns  
75  
80  
11  
12  
13  
14  
DIMM config  
non-ECC/ECC  
00  
80  
10  
00  
02  
80  
10  
00  
Refresh Rate/Type  
SDRAM Width, Primary  
Self-Refresh 15.6 ms  
×16  
Error Checking SDRAM Data  
Witdh  
na  
15  
Minimum Clock Delay for Back-  
to-Back Random Column  
Address  
t
CCD = 1 CLK  
01  
01  
16  
17  
18  
19  
20  
21  
22  
Burst Length Supported  
Number of SDRAM Ranks  
Supported CAS Latencies  
CS Latencies  
2, 4 & 8  
0E  
04  
0C  
01  
02  
20  
C1  
0E  
04  
0C  
01  
02  
20  
C1  
4
CAS latency = 2 & 2.5  
CS latency = 0  
Write latency = 1  
WE Latencies  
SDRAM DIMM Module Attributes unbuffered  
SDRAM Device Attributes:  
General  
Concurrent Auto Precharge,  
weak driver  
23  
24  
25  
26  
27  
Min. Clock Cycle Time at CAS  
Latency = 2  
7.5 ns/10 ns  
75  
75  
00  
00  
50  
A0  
80  
00  
00  
50  
Access Time from Clock for  
CL = 2  
0.75 ns/0.8 ns  
not supported  
not supported  
20 ns  
Minimum Clock Cycle Time for  
CL = 1.5  
Access Time from Clock at  
CL = 1.5  
Minimum Row Precharge Time  
Data Sheet  
19  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
SPD Contents  
Table 11  
Byte#  
SPD Codes for PC2100 & PC1600 (cont’d)  
Description  
128MB  
x64  
128MB  
x64  
2ranks  
–7  
2ranks  
–8  
HEX.  
HEX.  
28  
Minimum Row Act. to Row Act.  
15 ns  
3C  
3C  
Delay tRRD  
29  
Minimum RAS to CAS Delay tRCD 20 ns  
50  
2D  
10  
90  
90  
50  
50  
50  
32  
10  
B0  
B0  
60  
60  
30  
Minimum RAS Pulse Width tRAS 45 ns/50 ns  
Module Rank Density (per Rank) 64 MByte  
Addr. and Command Setup Time 0.9 ns/1.1 ns  
Addr. and Command Hold Time 0.9 ns/1.1 ns  
31  
32  
33  
34  
Data Input Setup Time  
Data Input Hold Time  
0.5 ns/0.6 ns  
0.5 ns/0.6 ns  
–
35  
36 to 40  
41  
Superset Information  
Minimum Core Cycle Time tRC  
65 ns/70 ns  
41  
4B  
46  
50  
42  
Min. Auto Refresh Cmd Cycle 75 ns/80 ns  
Time tFRC  
43  
Maximum Clock Cycle Time tCK  
Max. DQS-DQ Skew tDQSQ  
X-Factor tQHS  
12 ns  
30  
30  
44  
0.5 ns/0.6 ns  
32  
3C  
45  
0.75 ns/1.0 ns  
75  
A0  
46 to 61  
62  
Superset Information  
SPD Revision  
–
00  
00  
Revision 0.0  
00  
00  
63  
Checksum for Bytes 0 - 62  
Manufactures JEDEC ID Codes  
Manufactures  
–
–
–
–
–
–
–
–
–
–
88  
7D  
64  
C1  
C1  
65 to 71  
72  
Infineon  
Infineon  
Module Assembly Location  
Module Part Number  
Module Revision Code  
Module Manufacturing Date  
Module Serial Number  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
73 to 90  
91 to 92  
93 to 94  
95 to 98  
99 to 127  
128 to 255 open for Customer use  
Data Sheet  
20  
Rev. 1.02, 2004-01  
11042003-YIV7-VK6M  
HYS64D16020GD(L)-[7/8]-A  
Unbuffered DDR SDRAM SO Modules  
PRELIMINARY  
Package Outlines  
5
Package Outlines  
67.6  
3.8 MAX.  
±0.1  
63.6  
±0.1  
±0.1  
(2.15)  
1
(2.45)  
100  
18.45  
1
0.15  
±0.1  
1.8  
(2.4)  
±0.1  
11.4  
±0.1  
47.4  
(2.7)  
(2.15)  
200  
±0.1  
(2.45)  
1.5  
±0.1  
1
101  
2 MIN.  
Detail of contacts  
±0.03  
0.45  
±0.1  
0.6  
Burnished, no burr allowed  
Figure 3 Package Outlines Raw Card A : DDR-SDRAM SO-DIMM Modules Raw Card A  
Data Sheet  
21  
Rev. 1.01, 2003-11  
11042003-YIV7-VK6M  
w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  
厂商 型号 描述 页数 下载

INFINEON

 		HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

INFINEON

 		HYS64-74V8200GU 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ] 17 页

INFINEON

 		HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

 		HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

 		HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

 		HYS64D128020GBDL-7-A ？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

 		HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

 		HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

 		HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

 		HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

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