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HYS72T1G042ER

型号：

HYS72T1G042ER

描述：

240针双芯片寄存器的DDR2 SDRAM模块[ 240-Pin Dual Die Registered DDR2 SDRAM Modules ]

品牌：

QIMONDA[ QIMONDA AG ]

页数：

31 页

PDF大小：

1654 K

下载PDF手册
April 2007  
HYS72T1G042ER–5–B  
240-Pin Dual Die Registered DDR2 SDRAM Modules  
RDIMM SDRAM  
RoHS Compliant  
Internet Data Sheet  
Rev. 1.0  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
HYS72T1G042ER–5–B  
Revision History: 2007-04, Rev. 1.0  
Page  
Subjects (major changes since last revision)  
All  
All  
Adapted internet edition  
Final document  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc@qimonda.com  
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07  
04242007-NQ2Z-YM3O  
2
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
1
Overview  
This chapter gives an overview of the 240-Pin Dual Die Registered DDR2 SDRAM Modules product family and describes its  
main characteristics.  
1.1  
Features  
•
•
240-Pin PC2–3200 DDR2 SDRAM memory modules.  
1024M ×72 module organization and 2 × 256M × 4 chip  
organization  
Standard Double-Data-Rate-Two Synchronous DRAMs  
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power  
supply  
8 GB built with 1Gbit DDR2 SDRAMs in P-TFBGA-71  
chipsize packages  
All speed grades faster than DDR2–400 comply with  
DDR2–400 timing specifications.  
•
Average Refresh Period 7.8 µs at a TCASE lower than 85°C,  
3.9µs between 85°C and 95°C.  
Programmable self refresh rate via EMRS2 setting  
Programmable partial array refresh via EMRS2 settings  
DCC enabling via EMRS2 setting  
•
•
•
•
•
•
All inputs and outputs SSTL_1.8 compatible  
Off-Chip Driver Impedance Adjustment (OCD) and On-Die  
Termination (ODT)  
•
•
•
•
•
•
Serial Presence Detect with E2PROM  
RDIMM Dimensions (nominal):  
42mm high and 133.35 mm wide  
Programmable CAS Latencies (3, 4 and 5), Burst Length  
(8 & 4) and Burst Type  
Auto Refresh (CBR) and Self Refresh  
•
•
Based on standard reference layouts Raw Card “Z”  
RoHS compliant products1)  
TABLE 1  
Performance Table  
Product Type Speed Code  
Speed Grade  
–5  
Unit  
PC2–3200 3–3–3  
—
Max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
200  
200  
200  
15  
MHz  
MHz  
MHz  
ns  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
15  
ns  
tRAS  
tRC  
40  
ns  
55  
ns  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.0, 2007-04  
3
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
1.2  
Description  
The QIMONDA HYS72T1G042ER–5–B module family are  
Registered DIMM modules “RDIMMs” with 42 mm height  
based on DDR2 technology. DIMMs are available ECC  
modules in 1024M × 72 (8 GB) organization and density,  
intended for mounting into 240-pin connector sockets.  
capacitors are mounted on the PCB board. The DIMMs  
feature serial presence detect based on a serial E2PROM  
device using the 2-pin I2C protocol. The first 128 bytes are  
programmed with configuration data and are write protected;  
the second 128 bytes are available to the customer.  
The memory array is designed with stacked 1-Gbit Double-  
Data-Rate-Two (DDR2) Synchronous DRAMs. All control  
and address signals are re-driven on the DIMM using  
register devices and a PLL for the clock distribution.  
This reduces capacitive loading to the system bus, but  
adds one cycle to the SDRAM timing. Decoupling  
TABLE 2  
Ordering Information for RoHS Compliant Products  
Product Type1)  
Compliance Code2)  
Description  
SDRAM  
Technology  
PC2–3200  
HYS72T1G042ER–5–B  
8 GB 4R×4 PC2–3200R–333–12–ZZ  
4 Ranks, ECC  
2 × 256Mbit( × 4 )  
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T1G042ER–5–B, indicating Rev.  
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data  
sheet.  
2) The Compliance Code is printed on the module label and describes the speed grade, for example “4R×4 PC2–3200R–333–12–ZZ”, where  
3200R means Registered DIMM modules with 3.2 GB/sec Module Bandwidth and “333-12” means Column Address Strobe (CAS) latency  
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced  
on the Raw Card “Z”.  
TABLE 3  
Address Format  
DIMM  
Density  
Module  
Organization  
Memory  
Ranks  
ECC/  
Non-ECC  
# of SDRAMs # of row/bank/column  
bits  
Raw  
Card  
8 GByte  
1024M × 72  
4
ECC  
36  
14/3/11  
Z
TABLE 4  
Components on Modules  
DRAM Organisation Note2)  
2 × 256M × 4  
Product Type1)  
DRAM Components1)  
DRAM Density  
HYS72T1G042ER  
1) Green Product  
HYB18T2G402BF  
1 Gbit  
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.  
Rev. 1.0, 2007-04  
4
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
2
Pin Configuration  
The pin configuration of the Registered DDR2 SDRAM DIMM  
is listed by function in Table 5 (240 pins). The abbreviations  
used in columns Pin and Buffer Type are explained in Table 6  
and Table 7 respectively. The pin numbering is depicted in  
Figure 1.  
TABLE 5  
Pin Configuration of RDIMM  
Ball No.  
Name  
Pin  
Buffer  
Function  
Type Type  
Clock Signals  
185  
186  
52  
CK0  
CK0  
CKE0  
CKE1  
NC  
I
SSTL  
SSTL  
SSTL  
SSTL  
—
Clock Signal CK0, Complementary Clock Signal CK0  
I
I
Clock Enables 1:0  
Note: 2-Ranks module  
171  
I
NC  
Not Connected  
Note: 1-Rank module  
Control Signals  
193  
76  
S0  
S1  
NC  
I
SSTL  
SSTL  
—
Chip Select  
Note: 2-Ranks module  
I
NC  
Not Connected  
Note: 1-Rank module  
220,  
221  
S2  
I
SSTL  
—
Rank 2 is selected by S2  
Not Connected  
NC  
NC  
Note: 1-Rank, 2-Ranks module  
S3  
I
SSTL  
—
Rank 3 is selected by S3  
Not Connected  
NC  
NC  
Note: 1-Rank, 2-Ranks module  
192  
RAS  
I
I
I
I
SSTL  
SSTL  
SSTL  
CMOS  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
74  
CAS  
73  
WE  
18  
RESET  
Register Reset  
Address Signals  
71  
BA0  
BA1  
BA2  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus 1:0  
190  
54  
Bank Address Bus 2  
Greater than 512Mb DDR2 SDRAMS  
NC  
I
SSTL  
Not Connected  
Less than 1Gb DDR2 SDRAMS  
Rev. 1.0, 2007-04  
5
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Ball No.  
Name  
Pin  
Buffer  
Function  
Type Type  
188  
183  
63  
A0  
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
—
Address Bus 12:0, Address Signal 10/AutoPrecharge  
A1  
I
A2  
I
182  
61  
A3  
I
A4  
I
60  
A5  
I
180  
58  
A6  
I
A7  
I
179  
177  
70  
A8  
I
A9  
I
A10  
AP  
A11  
A12  
A13  
NC  
I
I
57  
I
176  
196  
I
I
Address Signal 13  
NC  
Not Connected  
Note: Non CA parity modules based on 256 Mbit component  
Address Signal 14  
174  
173  
A14  
NC  
I
SSTL  
—
Note: CA Parity module  
NC  
I
Not Connected  
Note: Non CA parity module. Less than 1 GBit per DRAM die.  
Address Signal 14  
A15  
NC  
SSTL  
—
Note: CA Parity module  
NC  
Not Connected  
Note: Non CA parity module. Less than 1 GBit per DRAM die.  
Rev. 1.0, 2007-04  
6
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Ball No.  
Name  
Pin  
Buffer  
Function  
Type Type  
Data Signals  
3
DQ0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Data Input/Output pins  
4
DQ1  
9
DQ2  
10  
DQ3  
122  
123  
128  
129  
12  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
13  
DQ9  
21  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
22  
131  
132  
140  
141  
24  
25  
30  
31  
143  
144  
149  
150  
33  
34  
39  
40  
152  
153  
158  
Rev. 1.0, 2007-04  
7
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Ball No.  
Name  
Pin  
Buffer  
Function  
Type Type  
159  
80  
DQ31  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Data Input/Output pins  
81  
86  
87  
199  
200  
205  
206  
89  
90  
95  
96  
208  
209  
214  
215  
98  
99  
107  
108  
217  
218  
226  
227  
110  
111  
116  
117  
229  
230  
235  
236  
Check Bits  
42  
CB0  
CB1  
CB2  
CB3  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bits 7:0  
Check Bit Input / Output pins  
43  
Note: NC on Non-ECC module  
48  
49  
Rev. 1.0, 2007-04  
8
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Ball No.  
Name  
Pin  
Buffer  
Function  
Type Type  
161  
CB4  
CB5  
CB6  
CB7  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bits 7:0  
Check Bit Input / Output pins  
162  
Note: NC on Non-ECC module  
167  
168  
Data Strobe Bus  
7
DQS0  
DQS0  
DQS1  
DQS1  
DQS2  
DQS2  
DQS3  
DQS3  
DQS4  
DQS4  
DQS5  
DQS5  
DQS6  
DQS6  
DQS7  
DQS7  
DQS8  
DQS8  
DQS9  
DQS9  
DQS10  
DQS10  
DQS11  
DQS11  
DQS12  
DQS12  
DQS13  
DQS13  
DQS14  
DQS14  
DQS15  
DQS15  
DQS16  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobes 17:0  
6
16  
15  
28  
27  
37  
36  
84  
83  
93  
92  
105  
104  
114  
113  
46  
45  
125  
126  
134  
135  
146  
147  
155  
156  
202  
203  
211  
212  
223  
224  
232  
Rev. 1.0, 2007-04  
9
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Ball No.  
Name  
Pin  
Buffer  
Function  
Type Type  
233  
DQS16  
DQS17  
DQS17  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
Data Strobes 17:0  
164  
165  
Data Mask  
125  
DM0  
DM1  
DM2  
DM3  
DM4  
DM5  
DM6  
DM7  
DM8  
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Masks 8:0  
Note: ×8 based module  
134  
146  
155  
202  
211  
223  
232  
164  
EEPROM  
120  
SCL  
SDA  
SA0  
SA1  
SA2  
I
CMOS  
OD  
Serial Bus Clock  
119  
I/O  
Serial Bus Data  
239  
I
I
I
CMOS  
CMOS  
CMOS  
Serial Address Select Bus 2:0  
240  
101  
Parity  
55  
ERR_OUT  
PAR_IN  
O
I
CMOS  
CMOS  
Parity bits  
68  
Power Supplies  
1
VREF  
AI  
—
—
—
I/O Reference Voltage  
EEPROM Power Supply  
I/O Driver Power Supply  
238  
VDDSPD  
PWR  
PWR  
51, 56, 62, 72, 75, VDDQ  
78, 170, 175, 181,  
191, 194  
53, 59, 64, 67, 69, VDD  
172, 178, 184, 187,  
189, 197  
PWR  
—
Power Supply  
Rev. 1.0, 2007-04  
10  
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Ball No.  
Name  
Pin  
Buffer  
Function  
Type Type  
2, 5, 8, 11, 14, 17, VSS  
20, 23, 26, 29, 32,  
35, 38, 41, 44, 47,  
50, 65, 66, 79, 82,  
85, 88, 91, 94, 97,  
100, 103, 106, 109,  
112, 115, 118, 121,  
124, 127, 130, 133,  
136, 139, 142, 145,  
148, 151, 154, 157,  
160, 163, 166, 169,  
198, 201, 204, 207,  
210, 213, 216, 219,  
222, 225, 228, 231,  
234, 237  
GND  
—
Ground Plane  
Other Pins  
19, 102, 137, 138, NC  
NC  
—
Not connected  
195  
77  
ODT0  
I
SSTL  
SSTL  
—
On-Die Termination Control 1:0  
Note: 2-Ranks module  
ODT1  
NC  
I
NC  
Note: 1-Rank modules  
TABLE 6  
Abbreviations for Buffer Type  
Abbreviation  
Description  
SSTL  
CMOS  
OD  
Serial Stub Terminated Logic (SSTL_18)  
CMOS Levels  
Open Drain. The corresponding pin has 2 operational states, active low and tristate,  
and allows multiple devices to share as a wire-OR.  
TABLE 7  
Abbreviations for Pin Type  
Abbreviation  
Description  
I
Standard input-only pin. Digital levels.  
Output. Digital levels.  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
O
I/O  
AI  
PWR  
GND  
NU  
NC  
Ground  
Not Usable  
Not Connected  
Rev. 1.0, 2007-04  
11  
04242007-NQ2Z-YM3O  
ꢃ
                                       
                                       
                                        
                                                                                                               
                                                                                                                
                                                                                                                 
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
FIGURE 1  
Pin Configuration for RDIMM (240 pins)  
95()  
'4ꢀ  
966  
'46ꢀ  
'4ꢈ  
966  
'4ꢇ  
'46ꢁ  
966  
1&  
'4ꢁꢀ  
966  
'4ꢁꢂ  
'46ꢈ  
966  
'4ꢁꢇ  
'4ꢈꢉ  
966  
'46ꢅ  
'4ꢈꢊ  
966  
&%ꢁ  
'46ꢋ  
966  
&%ꢅ  
9''4  
9''  
1&ꢌ(35B287  
ꢃ 3LQꢄꢀꢀꢁ  
ꢃ 3LQꢄꢀꢀꢅ  
ꢃ 3LQꢄꢀꢀꢆ  
ꢃ 3LQꢄꢀꢀꢂ  
ꢃ 3LQꢄꢀꢀꢇ  
ꢃ 3LQꢄꢀꢁꢁ  
ꢃ 3LQꢄꢀꢁꢅ  
ꢃ 3LQꢄꢀꢁꢆ  
ꢃ 3LQꢄꢀꢁꢂ  
ꢃ 3LQꢄꢀꢁꢇ  
3LQꢄꢁꢈꢁ ꢃ 966  
3LQꢄꢁꢈꢈ ꢃ '4ꢉ  
966  
'4ꢁ  
'46ꢀ ꢃ 3LQꢄꢀꢀꢊ  
966  
'4ꢅ  
'4ꢋ  
966  
'46ꢁ ꢃ 3LQꢄꢀꢁꢊ  
5(6(7 ꢃ 3LQꢄꢀꢁꢋ  
ꢃ 3LQꢄꢀꢀꢈ  
ꢃ 3LQꢄꢀꢀꢉ  
3LQꢄꢁꢈꢅ ꢃ '4ꢆ  
3LQꢄꢁꢈꢉ ꢃ 966  
3LQꢄꢁꢈꢆ ꢃ '0ꢀꢌ'46ꢇ  
3LQꢄꢁꢈꢊ ꢃ 1&ꢌ'46ꢇ  
3LQꢄꢁꢈꢂ ꢃ 966  
ꢃ 3LQꢄꢀꢀꢋ  
ꢃ 3LQꢄꢀꢁꢀ  
ꢃ 3LQꢄꢀꢁꢈ  
ꢃ 3LQꢄꢀꢁꢉ  
3LQꢄꢁꢈꢋ ꢃ '4ꢊ  
3LQꢄꢁꢈꢇ ꢃ '4ꢂ  
3LQꢄꢁꢅꢀ ꢃ 966  
3LQꢄꢁꢅꢁ ꢃ '4ꢁꢈ  
3LQꢄꢁꢅꢈ ꢃ '4ꢁꢅ  
3LQꢄꢁꢅꢅ ꢃ 966  
3LQꢄꢁꢅꢉ ꢃ '0ꢁꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢆ ꢃ 1&ꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢊ ꢃ 966  
3LQꢄꢁꢅꢂ ꢃ 1&  
3LQꢄꢁꢅꢇ ꢃ 966  
3LQꢄꢁꢉꢁ ꢃ '4ꢁꢆ  
3LQꢄꢁꢉꢅ ꢃ '4ꢈꢀ  
3LQꢄꢁꢉꢆ ꢃ 966  
3ꢄLQꢄꢁꢉꢂ ꢃ 1&ꢌ'46ꢁꢁ  
3LQꢄꢁꢉꢇ ꢃ '4ꢈꢈ  
3LQꢄꢁꢆꢁ ꢃ 966  
3LQꢄꢁꢆꢅ ꢃ '4ꢈꢇ  
3LQꢄꢁꢆꢆ ꢃ '0ꢅꢌ'46ꢁꢈ  
3LQꢄꢁꢆꢂ ꢃ 966  
3LQꢄꢁꢆꢇ ꢃ '4ꢅꢁ  
3LQꢄꢁꢊꢁ ꢃ &%ꢉ  
3LQꢄꢁꢊꢅ ꢃ 966  
3LQꢄꢁꢊꢆ ꢃ 1&ꢌ'46ꢁꢂ  
3LQꢄꢁꢊꢂ ꢃ &%ꢊ  
3LQꢄꢁꢊꢇ ꢃ 966  
3LQꢄꢁꢂꢁ ꢃ 1&ꢌ&.(ꢁ  
3LQꢄꢁꢂꢅ ꢃ 1&ꢄꢌꢄ$ꢁꢆ  
3LQꢄꢁꢂꢆ ꢃ 9''4  
3LQꢄꢁꢂꢂ ꢃ $ꢇ  
3LQꢄꢁꢂꢇ ꢃ $ꢋ  
3LQꢄꢁꢋꢁ ꢃ 9''4  
3LQꢄꢁꢋꢅ ꢃ $ꢁ  
3LQꢄꢁꢅꢋ ꢃ 1&  
3LQꢄꢁꢉꢀ ꢃ '4ꢁꢉ  
ꢃ
3LQꢄꢁꢉꢈ 966  
966  
ꢃ 3LQꢄꢀꢈꢀ  
ꢃ
ꢃ
3LQꢄꢀꢈꢁ  
3LQꢄꢀꢈꢅ  
ꢃ
ꢃ
'4ꢁꢁ  
'4ꢁꢊ  
966  
'46ꢈ  
'4ꢁꢋ  
966  
'4ꢈꢆ  
'46ꢅ  
966  
'4ꢈꢂ  
&%ꢀ  
966  
'46ꢋ  
&%ꢈ  
966  
&.(ꢀ  
3LQꢄꢀꢈꢈ  
3LQꢄꢀꢈꢉ  
ꢃ
3LQꢄꢁꢉꢉ '4ꢈꢁ  
ꢃ 3LQꢄꢀꢈꢆ  
3ꢄLQꢄꢀꢈꢂ  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢉꢊ '0ꢈꢌ'46ꢁꢁ  
3LQꢄꢀꢈꢊ  
3LQꢄꢀꢈꢋ  
3LQꢄꢀꢅꢀ  
3LQꢄꢀꢅꢈ  
3LQꢄꢀꢅꢉ  
3LQꢄꢀꢅꢊ  
3LQꢄꢀꢅꢋ  
3LQꢄꢀꢉꢀ  
3LQꢄꢀꢉꢈ  
3LQꢄꢀꢉꢉ  
3LQꢄꢀꢉꢊ  
3LQꢄꢀꢉꢋ  
3LQꢄꢀꢆꢀ  
3LQꢄꢀꢆꢈ  
ꢃ
3LQꢄꢁꢉꢋ 966  
ꢃ 3LQꢄꢀꢈꢇ  
ꢃ 3LQꢄꢀꢅꢁ  
ꢃ 3LQꢄꢀꢅꢅ  
ꢃ 3LQꢄꢀꢅꢆ  
ꢃ 3LQꢄꢀꢅꢂ  
ꢃ 3LQꢄꢀꢅꢇ  
ꢃ 3LQꢄꢀꢉꢁ  
ꢃ 3LQꢄꢀꢉꢅ  
ꢃ 3LQꢄꢀꢉꢆ  
ꢃ 3LQꢄꢀꢉꢂ  
ꢃ 3LQꢄꢀꢉꢇ  
ꢃ 3LQꢄꢀꢆꢁ  
ꢃ 3LQꢄꢀꢆꢅ  
ꢃ 3LQꢄꢀꢆꢆ  
ꢃ 3LQꢄꢀꢆꢂ  
ꢃ 3LQꢄꢀꢆꢇ  
ꢃ 3LQꢄꢀꢊꢁ  
ꢃ 3LQꢄꢀꢊꢅ  
ꢃ
3LQꢄꢁꢆꢀ '4ꢈꢅ  
ꢃ
3LQꢄꢁꢆꢈ '4ꢈꢋ  
ꢃ
3LQꢄꢁꢆꢉ 966  
ꢃ
3LQꢄꢁꢆꢊ 1&ꢌ'46ꢁꢈ  
ꢃ
3LQꢄꢁꢆꢋ '4ꢅꢀ  
ꢃ
3LQꢄꢁꢊꢀ 966  
ꢃ
3LQꢄꢁꢊꢈ &%ꢆ  
ꢃ
3LQꢄꢁꢊꢉ '0ꢋꢌ'46ꢁꢂ  
ꢃ
3LQꢄꢁꢊꢊ 966  
ꢃ
3LQꢄꢁꢊꢋ &%ꢂ  
ꢃ
3LQꢄꢁꢂꢀ 9''4  
ꢃ
3LQꢄꢁꢂꢈ 9''  
ꢃ
ꢃ
1&ꢌ%$ꢈ 3LQꢄꢀꢆꢉ  
9''4  
$ꢂ  
$ꢆ  
9''4  
9''  
3LQꢄꢁꢂꢉ 1&ꢌ$ꢁꢉ  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢂꢊ $ꢁꢈ  
3LQꢄꢀꢆꢊ  
3LQꢄꢀꢆꢋ  
3LQꢄꢀꢊꢀ  
3LQꢄꢀꢊꢈ  
3LQꢄꢀꢊꢉ  
$ꢁꢁ  
9''  
$ꢉ  
ꢃ
3LQꢄꢁꢂꢋ 9''  
ꢃ
3LQꢄꢁꢋꢀ $ꢊ  
ꢃ
3LQꢄꢁꢋꢈ $ꢅ  
$ꢈ  
ꢃ
3LQꢄꢁꢋꢉ 9''  
966  
9''  
9''  
%$ꢀ  
ꢃ 3LQꢄꢀꢊꢆ  
ꢃ 3LQꢄꢀꢊꢂ  
ꢃ 3LQꢄꢀꢊꢇ  
ꢃ 3LQꢄꢀꢂꢁ  
ꢃ 3LQꢄꢀꢂꢅ  
ꢃ 3LQꢄꢀꢂꢆ  
ꢃ 3LQꢄꢀꢂꢂ  
ꢃ 3LQꢄꢀꢂꢇ  
ꢃ 3LQꢄꢀꢋꢁ  
ꢃ 3LQꢄꢀꢋꢅ  
ꢃ 3LQꢄꢀꢋꢆ  
ꢃ 3LQꢄꢀꢋꢂ  
ꢃ 3LQꢄꢀꢋꢇ  
ꢃ 3LQꢄꢀꢇꢁ  
ꢃ 3LQꢄꢀꢇꢅ  
ꢃ 3LQꢄꢀꢇꢆ  
ꢃ 3LQꢄꢀꢇꢂ  
ꢃ 3LQꢄꢀꢇꢇ  
ꢃ 3LQꢄꢁꢀꢁ  
ꢃ 3LQꢄꢁꢀꢅ  
ꢃ 3LQꢄꢁꢀꢆ  
ꢃ 3LQꢄꢁꢀꢂ  
ꢃ 3LQꢄꢁꢀꢇ  
ꢃ 3LQꢄꢁꢁꢁ  
ꢃ 3LQꢄꢁꢁꢅ  
ꢃ 3LQꢄꢁꢁꢆ  
ꢃ 3LQꢄꢁꢁꢂ  
ꢃ 3LQꢄꢁꢁꢇ  
3LQꢄꢁꢋꢆ ꢃ &.ꢀ  
3LQꢄꢁꢋꢂ ꢃ 9''  
3LQꢄꢁꢋꢇ ꢃ 9''  
3LQꢄꢁꢇꢁ ꢃ 9''4  
3LQꢄꢁꢇꢅ ꢃ 6ꢀ  
3LQꢄꢁꢇꢆ ꢃ 2'7ꢀ  
3LQꢄꢁꢇꢂ ꢃ 9''  
3LQꢄꢁꢇꢇ ꢃ '4ꢅꢊ  
3LQꢄꢈꢀꢁ ꢃ 966  
3LQꢄꢈꢀꢅ ꢃ 1&ꢌ'46ꢁꢅ  
3LQꢄꢈꢀꢆ ꢃ '4ꢅꢋ  
3LQꢄꢈꢀꢂ ꢃ 966  
3LQꢄꢈꢀꢇ ꢃ '4ꢉꢆ  
3LQꢄꢈꢁꢁ ꢃ '0ꢆꢌ'46ꢁꢉ  
3LQꢄꢈꢁꢅ ꢃ 966  
3LQꢄꢈꢁꢆ ꢃ '4ꢉꢂ  
3LQꢄꢈꢁꢂ ꢃ '4ꢆꢈ  
3LQꢄꢈꢁꢇ ꢃ 966  
3LQꢄꢈꢈꢁ ꢃ 1&ꢌ6ꢅ  
3LQꢄꢈꢈꢅ ꢃ '0ꢊꢌ'46ꢁꢆ  
3LQꢄꢈꢈꢆ ꢃ 966  
3LQꢄꢈꢈꢂ ꢃ '4ꢆꢆ  
3LQꢄꢈꢈꢇ ꢃ '4ꢊꢀ  
3LQꢄꢈꢅꢁ ꢃ 966  
3LQꢄꢈꢅꢅ ꢃ 1&ꢌ'46ꢁꢊ  
3LQꢄꢈꢅꢆ ꢃ '4ꢊꢈ  
3LQꢄꢈꢅꢂ 966  
3LQꢄꢈꢅꢇ 6$ꢀ  
0337ꢀꢁꢂꢀ  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢁꢋꢊ &.ꢀ  
966  
3LQꢄꢀꢊꢊ  
3LQꢄꢀꢊꢋ  
3LQꢄꢀꢂꢀ  
3LQꢄꢀꢂꢈ  
3LQꢄꢀꢂꢉ  
3LQꢄꢀꢂꢊ  
3LQꢄꢀꢂꢋ  
3LQꢄꢀꢋꢀ  
3LQꢄꢀꢋꢈ  
3LQꢄꢀꢋꢉ  
3LQꢄꢀꢋꢊ  
3LQꢄꢀꢋꢋ  
3LQꢄꢀꢇꢀ  
3LQꢄꢀꢇꢈ  
3LQꢄꢀꢇꢉ  
3LQꢄꢀꢇꢊ  
3LQꢄꢀꢇꢋ  
3LQꢄꢁꢀꢀ  
3LQꢄꢁꢀꢈ  
3LQꢄꢁꢀꢉ  
3LQꢄꢁꢀꢊ  
3LQꢄꢁꢀꢋ  
3LQꢄꢁꢁꢀ  
3LQꢄꢁꢁꢈ  
3LQꢄꢁꢁꢉ  
3LQꢄꢁꢁꢊ  
3LQꢄꢁꢁꢋ  
3LQꢄꢁꢈꢀ  
1&ꢌ3$5B,1  
ꢃ
3LQꢄꢁꢋꢋ $ꢀ  
$ꢁꢀꢌ$3  
9''4  
&$6  
1&ꢌ6ꢁ  
9''4  
'4ꢅꢈ  
966  
'46ꢉ  
'4ꢅꢉ  
966  
'4ꢉꢁ  
'46ꢆ  
966  
'4ꢉꢅ  
'4ꢉꢋ  
966  
1&  
'46ꢊ  
966  
'4ꢆꢁ  
'4ꢆꢊ  
966  
'46ꢂ  
'4ꢆꢋ  
966  
ꢃ
3LQꢄꢁꢇꢀ %$ꢁ  
ꢃ
3LQꢄꢁꢇꢈ 5$6  
:(  
ꢃ
3LQꢄꢁꢇꢉ 9''4  
9''4  
1&ꢌ2'7ꢁ  
966  
'4ꢅꢅ  
'46ꢉ  
966  
'4ꢅꢆ  
'4ꢉꢀ  
966  
'46ꢆ  
'4ꢉꢈ  
966  
'4ꢉꢇ  
6$ꢈ  
966  
'46ꢊ  
'4ꢆꢀ  
966  
'4ꢆꢂ  
'46ꢂ  
966  
ꢃ
3LQꢄꢁꢇꢊ 1&ꢌ$ꢁꢅ  
ꢃ
3LQꢄꢁꢇꢋ 966  
ꢃ
3LQꢄꢈꢀꢀ '4ꢅꢂ  
ꢃ
3LQꢄꢈꢀꢈ '0ꢉꢌ'46ꢁꢅ  
ꢃ
3LQꢄꢈꢀꢉ 966  
ꢃ
3LQꢄꢈꢀꢊ '4ꢅꢇ  
ꢃ
3LQꢄꢈꢀꢋ '4ꢉꢉ  
ꢃ
3LQꢄꢈꢁꢀ 966  
ꢃ
3LQꢄꢈꢁꢈ 1&ꢌ'46ꢁꢉ  
ꢃ
3LQꢄꢈꢁꢉ '4ꢉꢊ  
ꢃ
3LQꢄꢈꢁꢊ 966  
ꢃ
3LQꢄꢈꢁꢋ '4ꢆꢅ  
ꢃ
3LQꢄꢈꢈꢀ 1&ꢌ6ꢈ  
ꢃ
3LQꢄꢈꢈꢈ 966  
ꢃ
3LQꢄꢈꢈꢉ 1&ꢌ'46ꢁꢆ  
ꢃ
3LQꢄꢈꢈꢊ '4ꢆꢉ  
ꢃ
3LQꢄꢈꢈꢋ 966  
ꢃ
3LQꢄꢈꢅꢀ '4ꢊꢁ  
ꢃ
3LQꢄꢈꢅꢈ '0ꢂꢌ'46ꢁꢊ  
ꢃ
3LQꢄꢈꢅꢉ 966  
ꢃ
3LQꢄꢈꢅꢊ '4ꢊꢅ  
'4ꢆꢇ  
6'$  
3LQꢄꢈꢅꢋ 9''63'  
3LQꢄꢈꢉꢀ 6$ꢁ  
6&/  
Rev. 1.0, 2007-04  
04242007-NQ2Z-YM3O  
12  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
3
Electrical Characteristics  
This chapter lists the electrical characteristics.  
3.1  
Absolute Maximum Ratings  
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.  
TABLE 8  
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
Min.  
Unit  
Note  
Max.  
1)  
VDD  
Voltage on VDD pin relative to VSS  
Voltage on VDDQ pin relative to VSS  
Voltage on VDDL pin relative to VSS  
Voltage on any pin relative to VSS  
Storage Temperature  
–1.0  
–0.5  
–0.5  
–0.5  
–55  
+2.3  
+2.3  
+2.3  
+2.3  
+100  
V
1)2)  
1)2)  
1)  
VDDQ  
VDDL  
V
V
VIN, VOUT  
TSTG  
V
1)2)  
°C  
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.  
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.  
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at these or any other  
conditions above those indicated in the operational sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended periods may affect reliability.  
TABLE 9  
DRAM Component Operating Temperature Range  
Symbol  
Parameter  
Rating  
Unit  
Note  
Min.  
Max.  
1)2)3)4)  
TOPER  
Operating Temperature  
0
95  
°C  
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.  
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case  
temperature must be maintained between 0 - 95 °C under all other specification parameters.  
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs  
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %  
Rev. 1.0, 2007-04  
13  
04242007-NQ2Z-YM3O  
 
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
3.2  
DC Operating Conditions  
This chapter contains the DC operating conditions tables.  
TABLE 10  
Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Max.  
Operating temperature (ambient)  
DRAM Case Temperature  
TOPR  
TCASE  
TSTG  
PBar  
0
+65  
+95  
+100  
+105  
90  
°C  
°C  
°C  
kPa  
%
1)2)3)4)  
5)  
0
Storage Temperature  
– 50  
+69  
10  
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
HOPR  
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported  
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs  
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %.  
5) Up to 3000 m.  
TABLE 11  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Typ.  
Max.  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
VDD  
1.7  
1.8  
1.9  
V
1)  
2)  
VDDQ  
VREF  
1.7  
1.8  
1.9  
V
0.49 × VDDQ  
0.5 × VDDQ  
0.51 × VDDQ  
V
VDDSPD  
VIH(DC)  
VIL (DC  
IL  
1.7  
—
—
—
—
3.6  
V
DC Input Logic High  
V
REF + 0.125  
V
V
5
DDQ + 0.3  
V
DC Input Logic Low  
)
– 0.30  
– 5  
REF – 0.125  
V
3)  
In / Output Leakage Current  
µA  
1) Under all conditions, VDDQ must be less than or equal to VDD  
2) Peak to peak AC noise on VREF may not exceed ± 2 % VREF (DC).VREF is also expected to track noise in VDDQ  
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
Rev. 1.0, 2007-04  
14  
04242007-NQ2Z-YM3O  
 
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
3.3  
Timing Characteristics  
This chapter describes the timing characteristics.  
3.3.1  
Speed Grade Definitions  
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK = 5ns with tRAS = 40ns).  
Speed Grade Definitions: Table 12 for DDR2–400B  
TABLE 12  
Speed Grade Definition Speed Bins for DDR2-400B  
Speed Grade  
DDR2–400B  
Unit  
Note  
QAG Sort Name  
CAS-RCD-RP latencies  
–5  
3–3–3  
tCK  
Parameter  
Symbol  
Min.  
Max.  
—
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
5
8
tCK  
5
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
40  
55  
15  
15  
70000  
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal  
OCD drive strength (EMRS(1) A1 = 0) .  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
4) The output timing reference voltage level is VTT  
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI  
t
.
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Registerd DDR2 SDRAM Module  
3.3.2  
Component AC Timing Parameters  
Timing Parameters: Table 13 for DDR2–400B  
TABLE 13  
DRAM Component Timing Parameter by Speed Grade - DDR2-400  
Parameter  
Symbol  
DDR2–400  
Unit  
Note1)2)3)4)5)  
6)7)  
Min.  
Max.  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–600  
2
+600  
—
ps  
tCCD  
tCH  
tCKE  
tCL  
tCK  
tCK  
tCK  
tCK  
tCK  
0.45  
3
0.55  
—
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
—
8)21)  
9)  
Auto-Precharge write recovery + precharge  
time  
tDAL  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK + tIH  
275  
––  
––  
—
ns  
ps  
ps  
10)  
11)  
DQ and DM input hold time (differential data  
strobe)  
t
t
DH(base)  
DQ and DM input hold time (single ended data  
strobe)  
DH1(base)  
–25  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDIPW  
0.35  
–500  
0.35  
—
—
tCK  
ps  
tCK  
ps  
tDQSCK  
+500  
—
DQS input low (high) pulse width (write cycle) tDQSL,H  
11)  
DQS-DQ skew (for DQS & associated DQ  
signals)  
tDQSQ  
350  
Write command to 1st DQS latching transition tDQSS  
– 0.25  
150  
+ 0.25  
—
tCK  
11)  
11)  
DQ and DM input setup time (differential data  
strobe)  
t
DS(base)  
ps  
DQ and DM input setup time (single ended  
data strobe)  
t
DS1(base)  
–25  
0.2  
—
—
ps  
DQS falling edge hold time from CK (write  
cycle)  
tDSH  
tCK  
DQS falling edge to CK setup time (write cycle) tDSS  
0.2  
—
—
—
tCK  
ns  
ns  
Four Activate Window period  
Four Activate Window period  
Clock half period  
tFAW  
tFAW  
tHP  
37.5  
13)  
12)  
13)  
11)  
50  
MIN. (tCL, tCH  
)
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
—
tAC.MAX  
—
ps  
ps  
tCK  
tIH(base)  
tIPW  
475  
0.6  
Address and control input pulse width  
(each input)  
—
11)  
14)  
14)  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
tIS(base)  
tLZ(DQ)  
350  
—
ps  
ps  
ps  
2 × tAC.MIN  
tAC.MIN  
tAC.MAX  
tAC.MAX  
tLZ(DQS)  
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Registerd DDR2 SDRAM Module  
Parameter  
Symbol  
DDR2–400  
Min.  
Unit  
Note1)2)3)4)5)  
6)7)  
Max.  
Mode register set command cycle time  
OCD drive mode output delay  
Data output hold time from DQS  
Data hold skew factor  
tMRD  
tOIT  
2
0
—
tCK  
12  
ns  
tQH  
t
HP –tQHS  
—
tQHS  
tREFI  
tREFI  
—
450  
7.8  
3.9  
—
ps  
µs  
µs  
ns  
14)15)  
16)18)  
17)  
Average periodic refresh Interval  
Average periodic refresh Interval  
—
—
Auto-Refresh to Active/Auto-Refresh  
command period  
127.5  
Precharge-All (4 banks) command period  
Precharge-All (8 banks) command period  
Read preamble  
tRP  
t
RP + 1tCK  
—
ns  
ns  
tCK  
tCK  
ns  
tRP  
15 + 1tCK  
0.9  
—
14)  
tRPRE  
tRPST  
tRRD  
1.1  
0.60  
—
14)  
Read postamble  
0.40  
14)18)  
Active bank A to Active bank B command  
period  
7.5  
16)22)  
Active bank A to Active bank B command  
period  
tRRD  
10  
—
ns  
Internal Read to Precharge command delay  
Write preamble  
tRTP  
7.5  
—
ns  
tCK  
tCK  
ns  
tWPRE  
tWPST  
tWR  
0.25  
0.40  
15  
—
19)  
Write postamble  
0.60  
—
Write recovery time for write without Auto-  
Precharge  
20)  
21)  
Internal Write to Read command delay  
tWTR  
10  
2
—
—
ns  
Exit power down to any valid command  
(other than NOP or Deselect)  
tXARD  
tCK  
21)  
Exit active power-down mode to Read  
command (slow exit, lower power)  
tXARDS  
tXP  
6 – AL  
2
—
—
tCK  
tCK  
Exit precharge power-down to any valid  
command (other than NOP or Deselect)  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
WR  
t
RFC +10  
200  
WR/tCK  
—
—
—
ns  
tCK  
tCK  
22)  
Write recovery time for write with Auto-  
Precharge  
t
1) For details and notes see the relevant Qimonda component data sheet  
2)  
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)  
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,  
input reference level is the crosspoint when in differential strobe mode.  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
7) The output timing reference voltage level is VTT  
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to  
the WR parameter stored in the MR.  
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9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.  
10) For timing definition, refer to the Component data sheet.  
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate  
mis-match between DQS / DQS and associated DQ in any given cycle.  
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can  
be greater than the minimum specification limits for tCL and tCH).  
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving  
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These  
parameters are verified by design and characterization, but not subject to production test.  
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C  
and 95 °C.  
15) 0 °C≤ TCASE ≤ 85 °C  
16) 85 °C < TCASE ≤ 95 °C  
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.  
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS  
Compliant Products” on Page 4.  
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system  
performance (bus turnaround) degrades accordingly.  
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.  
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-  
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow  
power-down exit timing tXARDS has to be satisfied.  
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded  
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK  
refers to the application clock period. WR refers to the WR parameter stored in the MRS.  
3.3.3  
ODT AC Electrical Characteristics  
TABLE 14  
ODT AC Electrical Characteristics and Operating Conditions for DDR2-400  
Symbol  
Parameter / Condition  
Values  
Unit  
Note  
Min.  
Max.  
tAOND  
tAON  
ODT turn-on delay  
2
2
tCK  
ns  
ns  
tCK  
ns  
ns  
tCK  
tCK  
1)  
2)  
ODT turn-on  
tAC.MIN  
tAC.MAX + 1 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns  
2 tCK + tAC.MAX + 1 ns  
2.5  
2.5  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
ODT to Power Down Mode Entry Latency  
ODT Power Down Exit Latency  
t
AC.MIN + 2 ns  
2.5 tCK + tAC.MAX + 1 ns  
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when  
the ODT resistance is fully on. Both are measure from tAOND  
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.  
.
Both are measured from tAOFD  
.
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3.4  
IDD Specifications and Conditions  
List of tables defining IDD Specifications and Conditions.  
•
•
•
Table 15 “IDD Measurement Conditions” on Page 19  
Table 16 “Definitions for IDD” on Page 20  
Table 17 “IDD Specification for HYS72T1G042ER–5–B” on Page 21  
TABLE 15  
DD Measurement Conditions  
I
Parameter  
Symbol Note  
1)2)3)4)5)  
Operating Current 0  
IDD0  
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between  
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.  
6)  
Operating Current 1  
IDD1  
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN  
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and  
control inputs are SWITCHING, Databus inputs are SWITCHING.  
Precharge Standby Current  
IDD2N  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,  
Databus inputs are SWITCHING.  
Precharge Power-Down Current  
Other control and address inputs are STABLE, Data bus inputs are FLOATING.  
IDD2P  
IDD2Q  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,  
Data bus inputs are FLOATING.  
Active Standby Current  
IDD3N  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);  
IDD3P(0)  
IDD3P(1)  
IDD4R  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);  
6)  
Operating Current - Burst Read  
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX  
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data  
bus inputs are SWITCHING; IOUT = 0mA.  
Operating Current - Burst Write  
IDD4W  
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING;  
Burst Refresh Current  
IDD5B  
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
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Registerd DDR2 SDRAM Module  
Parameter  
Symbol Note  
1)2)3)4)5)  
Distributed Refresh Current  
IDD5D  
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Self-Refresh Current  
IDD6  
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data  
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.  
6)  
All Bank Interleave Read Current  
IDD7  
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control  
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.  
1)  
2)  
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.  
3) Definitions for IDD see Table 16  
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P  
5) For details and notes see the relevant Qimonda component data sheet  
6)  
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output  
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.  
TABLE 16  
Definitions for IDD  
Parameter  
LOW  
Description  
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN  
Inputs are stable at a HIGH or LOW level  
Inputs are VREF = VDDQ /2  
STABLE  
FLOATING  
SWITCHING  
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control  
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ  
signals not including mask or strobes  
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TABLE 17  
DD Specification for HYS72T1G042ER–5–B  
I
Product Type  
Organization  
HYS72T1G042ER–5–B  
Units  
Note1)  
8 GB  
×72  
4 Ranks  
–5  
2)  
IDD0  
3330  
3420  
1840  
4580  
4220  
3500  
2060  
4940  
4050  
4050  
5040  
1910  
720  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
3)  
IDD2P  
3)  
IDD2N  
3)  
IDD2Q  
IDD3P_0 (fast)  
IDD3P_1 (slow)  
IDD3N  
3)  
3)4)  
3)5)  
2)  
IDD4R  
2)  
IDD4W  
IDD5B  
2)  
3)6)  
3)6)  
2)  
IDD5D  
IDD6  
IDD7  
5490  
1) Module IDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are  
defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Current mode  
3) Both ranks are in the same IDDcurrent mode  
4) Fast: MRS(12)=0  
5) Slow: MRS(12)=1  
6)  
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C  
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Registerd DDR2 SDRAM Module  
4
SPD Codes  
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands  
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.  
List of SPD Code Tables  
•
Table 18 “HYS72T1G042ER-5-B” on Page 22  
TABLE 18  
HYS72T1G042ER-5-B  
Product Type  
Organization  
8 GByte  
×72  
4 Ranks (×4)  
PC2–3200R–333  
Rev. 1.2  
HEX  
Label Code  
JEDEC SPD Revision  
Byte#  
Description  
0
Programmed SPD Bytes in EEPROM  
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
80  
08  
08  
0E  
0B  
63  
48  
00  
05  
50  
60  
02  
82  
04  
04  
00  
1
2
3
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
4
5
6
7
Not used  
8
Interface Voltage Level  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
10  
11  
12  
13  
14  
15  
AC SDRAM @ CLMAX (Byte 18) [ns]  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
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Registerd DDR2 SDRAM Module  
Product Type  
Organization  
8 GByte  
×72  
4 Ranks (×4)  
PC2–3200R–333  
Rev. 1.2  
HEX  
Label Code  
JEDEC SPD Revision  
Byte#  
Description  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
0C  
08  
38  
01  
01  
05  
07  
50  
60  
50  
60  
3C  
1E  
3C  
28  
02  
35  
47  
15  
27  
3C  
28  
1E  
00  
06  
37  
7F  
DIMM Attributes  
Component Attributes  
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
Rev. 1.0, 2007-04  
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HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Product Type  
Organization  
8 GByte  
×72  
4 Ranks (×4)  
PC2–3200R–333  
Rev. 1.2  
HEX  
Label Code  
JEDEC SPD Revision  
Byte#  
Description  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
t
t
t
CK.MAX [ns]  
80  
23  
2D  
0F  
50  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
12  
46  
7F  
7F  
7F  
7F  
7F  
51  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
PLL Relock Time  
CASE.MAX Delta / ∆T4R4W Delta  
T
Psi(T-A) DRAM  
∆T0 (DT0)  
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)  
∆T2P (DT2P)  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
Manufacturer’s JEDEC ID Code (1)  
Manufacturer’s JEDEC ID Code (2)  
Manufacturer’s JEDEC ID Code (3)  
Manufacturer’s JEDEC ID Code (4)  
Manufacturer’s JEDEC ID Code (5)  
Manufacturer’s JEDEC ID Code (6)  
Rev. 1.0, 2007-04  
24  
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Product Type  
Organization  
8 GByte  
×72  
4 Ranks (×4)  
PC2–3200R–333  
Rev. 1.2  
HEX  
Label Code  
JEDEC SPD Revision  
Byte#  
Description  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95 - 98  
Manufacturer’s JEDEC ID Code (7)  
Manufacturer’s JEDEC ID Code (8)  
Module Manufacturer Location  
Product Type, Char 1  
00  
00  
xx  
37  
32  
54  
31  
47  
30  
34  
32  
45  
52  
35  
42  
20  
20  
20  
20  
20  
20  
0x  
xx  
xx  
xx  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
Module Serial Number  
Rev. 1.0, 2007-04  
25  
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Product Type  
Organization  
8 GByte  
×72  
4 Ranks (×4)  
PC2–3200R–333  
Rev. 1.2  
HEX  
Label Code  
JEDEC SPD Revision  
Byte#  
Description  
99 - 127  
Not used  
00  
128 - 255  
Blank for customer use  
FF  
Rev. 1.0, 2007-04  
26  
04242007-NQ2Z-YM3O  
                                                                                                                             
                                                                                                                               
                                                                                                                               
                                                                                                                                
                                                                                                                                
                                                                           
                                                                            
                                                                            
                                                                             
                                                                              
                                                                              
                                                                               
                                                                               
ꢁꢄꢄ  
ꢁꢈꢀꢄꢄ  
                                                                                                              
                                                                                                              
                                                                                                               
                                                                                                               
ꢈꢍꢆꢄꢄ  
                                                                            
                                                                             
                                                                                                                                                                      
ꢀꢍꢁꢄꢄ  
                                                                                                                                                                      
                                                                                                                                                                       
                                                                                                                                                                        
                                                                                                                             
                                                                                                                              
                                                                                                                              
                                                                                                                               
ꢊꢅ  
                                                            
                                                            
ꢄꢄ  
ꢆꢆꢄꢄ  
                                                                                                 
                                                                                                 
“ꢀꢍꢁ  
ꢁꢍꢆꢄꢄ  
                                                                                                   
                                                                                                    
                                                                                                     
                                                                                                     
ꢄꢄ  
                                                                           
                                                                           
ꢁꢈꢁ  
                                       
                                       
                                        
                                        
ꢄꢄ  
ꢈꢉꢀꢄꢄ  
                                                                                                              
                                                                                                              
                                                                                                               
                                                                                                               
ꢅꢄ  
                                          
                                            
                                            
1
                                            
0,  
ꢄR  
ꢍꢄꢄ  
'HW  
                                       
                                        
                                        
                                         
DLO  
                                         
                                          
                                          
                                           
I
                                            
ꢄF  
                                             
RQ  
                                              
                                              
                                              
                                               
W
                                               
                                                
DFWVꢄꢄ  
                                                
                                                 
                                                 
                                                  
                                                  
                                                  
“ꢀꢍ  
ꢀꢍꢋꢄꢄ  
                                                                             
                                                                             
                                                                              
ꢀꢆꢄꢄ  
                                                                               
                                                                               
                                                                                
                                                         
                                                          
ꢀꢍꢁꢄ$ꢄꢄ%ꢄꢄ&ꢄꢄ  
                                                                   
                                                                   
                                                                    
%XUU  
                                         
                                         
                                         
                                          
ꢄP  
                                           
                                            
D[ꢍꢄꢀꢍ  
                                             
                                             
                                              
                                               
                                                
ꢉ
                                                 
ꢄDOORZHGꢄꢄ  
                                                  
                                                   
                                                   
                                                   
                                                    
                                                    
                                                     
                                                     
                                                      
                                                      
                                                       
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
5
Package Outlines  
This chapter contains the package outlines of the products.  
FIGURE 2  
Package Outline Raw Card Z L-DIM-240-46  
ꢁꢅ  
                                                                           
                                                                            
ꢅ
                                                                            
                                                                             
ꢍ
ꢍ
                                                                              
ꢅ
                                                                              
ꢆ
ꢆ
                                                                               
                                                                               
ꢄꢄ  
ꢄꢄ  
ꢉꢄ0  
$;ꢍꢄꢄ  
ꢁꢈꢋ  
ꢇ
ꢉꢄꢄ  
%ꢄꢄ &ꢄꢄ  
“
ꢁꢍꢈꢂꢄꢄ  
ꢆꢄꢄ  
$ꢄꢄ  
%ꢄꢄ  
ꢁꢄꢄ  
Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
Rev. 1.0, 2007-04  
27  
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
6
Product Type Nomenclature  
Qimonda´s nomenclature uses simple coding combined with some propriatory coding. Table 19 provides examples for module  
and component product type number as well as the field number. The detailed field description together with possible values  
and coding explanation is listed for modules in Table 20 and for components in Table 21.  
TABLE 19  
Nomenclature Fields and Examples  
Example for  
Field Number  
1
2
3
4
5
6
7
8
9
10  
11  
Micro-DIMM  
DDR2 DRAM  
HYS  
HYB  
64  
18  
T
T
64/128  
0
2
0
0
K
A
M
C
–5  
–5  
–A  
—
512/1G 16  
TABLE 20  
DDR2 DIMM Nomenclature  
Field  
Description  
Values  
Coding  
1
2
Qimonda Module Prefix  
Module Data Width [bit]  
HYS  
64  
Constant  
Non-ECC  
ECC  
72  
3
4
DRAM Technology  
T
DDR2  
Memory Density per I/O [Mbit];  
Module Density1)  
32  
256 MByte  
512 MByte  
1 GByte  
2 GByte  
4 GByte  
64  
128  
256  
512  
0 .. 9  
0, 2, 4  
0 .. 9  
A .. Z  
D
5
6
7
8
9
Raw Card Generation  
Number of Module Ranks  
Product Variations  
Look up table  
1, 2, 4  
Look up table  
Look up table  
SO-DIMM  
Package, Lead-Free Status  
Module Type  
M
Micro-DIMM  
Registered  
Unbuffered  
Fully Buffered  
R
U
F
Rev. 1.0, 2007-04  
28  
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Field  
Description  
Values  
Coding  
10  
Speed Grade  
–2.5F  
–2.5  
–3  
PC2–6400 5–5–5  
PC2–6400 6–6–6  
PC2–5300 4–4–4  
PC2–5300 5–5–5  
PC2–4200 4–4–4  
PC2–3200 3–3–3  
First  
–3S  
–3.7  
–5  
11  
Die Revision  
–A  
–B  
Second  
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall  
module memory density in MBytes as listed in column “Coding”.  
TABLE 21  
DDR2 DRAM Nomenclature  
Field  
Description  
Values  
Coding  
1
2
3
4
Qimonda Component Prefix  
Interface Voltage [V]  
HYB  
18  
Constant  
SSTL_18  
DRAM Technology  
T
DDR2  
Component Density [Mbit]  
256  
512  
1G  
2G  
40  
256 Mbit  
512 Mbit  
1 Gbit  
2 Gbit  
5+6  
Number of I/Os  
×4  
80  
×8  
16  
×16  
7
8
Product Variations  
Die Revision  
0 .. 9  
A
Look up table  
First  
B
Second  
9
Package, Lead-Free Status  
Speed Grade  
C
FBGA, lead-containing  
FBGA, lead-free  
DDR2-800 5-5-5  
DDR2-800 6-6-6  
DDR2-667 4-4-4  
DDR2-667 5-5-5  
DDR2-533 4-4-4  
DDR2-400 3-3-3  
F
10  
–25F  
–2.5  
–3  
–3S  
–3.7  
–5  
Rev. 1.0, 2007-04  
29  
04242007-NQ2Z-YM3O  
Internet Data Sheet  
HYS72T1G042ER–5–B  
Registerd DDR2 SDRAM Module  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
3
3.1  
3.2  
3.3  
3.3.1  
3.3.2  
3.3.3  
3.4  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Rev. 1.0, 2007-04  
30  
04242007-NQ2Z-YM3O  
Internet Data Sheet  
Edition 2007-04  
Published by Qimonda AG  
Gustav-Heinemann-Ring 212  
D-81739 München, Germany  
© Qimonda AG 2007.  
All Rights Reserved.  
Legal Disclaimer  
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics  
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any  
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,  
including without limitation warranties of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in question please  
contact your nearest Qimonda Office.  
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a  
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect  
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human  
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health  
of the user or other persons may be endangered.  
www.qimonda.com  
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