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HYS72V16300GU-75-C2

型号：

HYS72V16300GU-75-C2

描述：

3.3 V 16M ×64 /72- 1位银行128MByte SDRAM模块3.3 V 32M ×64 /72- 2位银行256MByte SDRAM模块168针无缓冲DIMM模块[ 3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules ]

品牌：

INFINEON[ Infineon ]

页数：

20 页

PDF大小：

302 K

下载PDF手册
HYS 64/72V16300/32220GU  
SDRAM-Modules  
3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module  
3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module  
168-Pin Unbuffered DIMM Modules  
•
168-Pin unbuffered 8-Byte Dual-In-Line  
SDRAM Modules for PC main memory  
applications  
•
Programmed Latencies:  
Product Speed  
CL tRCD  
tRP  
2
-7  
PC133-222  
PC133-333  
PC100-222  
2
3
2
2
3
2
•
•
•
•
•
•
PC100-222, PC133-333 and PC133-222  
versions  
-7.5  
-8  
3
2
1 bank 16M × 64, 16M × 72 and 2 bank  
32M × 64, 32M × 72 organzation  
•
•
Single +3.3 V(±0.3 V) Power Supply  
Optimized for byte-write non-parity (x64) or  
ECC (x72) applications  
Programmable CAS Latency, Burst Length,  
and Wrap Sequence  
(Sequential and Interleave)  
JEDEC standard Synchronous DRAMs  
(SDRAM)  
•
•
•
•
•
Auto-Refresh (CBR) and Self-Refresh  
Decoupling capacitors mounted on substrate  
All inputs and outputs are LVTTL compatible  
Serial Presence Detect with E2PROM  
Fully PC board layout compatible to INTEL’s  
Rev. 1.0 Module Specification  
SDRAM Performance:  
-7 /-7.5 -8  
Unit  
Utilizes 16M × 8 SDRAMs in TSOPII-54  
packages with 4096 refresh cycles every  
64 ms  
PC133  
133  
PC100  
fCK Max. Clock  
100  
MHz  
ns  
Frequency  
•
133.35 mm × 31.75 mm × 4,00 mm card size  
with gold-contact pads  
(JEDEC MO-161-BA)  
tAC Clock Access 5.4  
6
Time  
Description  
The HYS 64(72)V16300GU and HYS 64(72)V32220GU are industry-standard 168-pin 8-byte Dual  
In-line Memory Modules (DIMMs) which are organized as 16M × 64, 16M × 72 in 1 bank and  
32M × 64 and 32M × 72 in two banks of high-speed memory arrays designed with 128Mbit  
Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -7 speed  
sorted 16M × 8 SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -7.5  
speed sorted for PC133-333 and use -8 components for the standard PC100-222 applications.  
Decoupling capacitors are mounted on the PC board. The PC board design is in accordance with  
INTEL’s Module Specification. The DIMMs have Serial Presence Detect, implemented with a serial  
E2PROM using the two-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer  
and the second 128 bytes are available to the end user. All INFINEON 168-pin DIMMs provide a  
high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm)  
height.  
INFINEON Technologies  
1
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Ordering Information  
Type  
Code  
Package  
Descriptions  
Module  
Height  
128 MByte DIMMs  
HYS 64V16300GU-7-C2  
PC133-222-520 L-DIM-168-33 133 Mhz 16M × 64  
1.25“  
1.25“  
1.25“  
1.25“  
1.25“  
1.25“  
1 bank SDRAM module  
HYS 64V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M × 64  
1 bank SDRAM module  
HYS 64V16300GU-8-C2  
HYS 72V16300GU-7-C2  
PC100-222-620 L-DIM-168-33 100 MHz 16M × 64  
1 bank SDRAM module  
PC133-222-520 L-DIM-168-33 133 Mhz 16M × 72  
1 bank SDRAM module  
HYS 72V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M × 72  
1 bank SDRAM module  
HYS 72V16300GU-8-C2  
PC100-222-620 L-DIM-168-33 100 MHz 16M × 72  
1 bank SDRAM module  
256 MByte DIMMs  
HYS 64V32220GU-7-C2  
PC133-222-520 L-DIM-168-30 133 MHz 32M × 64  
1.25“  
1.25“  
1.25“  
1.25“  
1.25“  
1.25“  
2 bank SDRAM module  
HYS 64V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 MHz 32M × 64  
2 bank SDRAM module  
HYS 64V32220GU-8-C2  
HYS 72V32220GU-7-C2  
PC100-222-620 L-DIM-168-30 100 MHz 32M × 64  
2 bank SDRAM module  
PC133-222-520 L-DIM-168-30 133 Mhz 32M × 72  
2 bank SDRAM module  
HYS 72V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 Mhz 32M × 72  
2 bank SDRAM module  
HYS 72V32220GU-8-C2  
PC100-222-620 L-DIM-168-30 100 Mhz 32M × 72  
2 bank SDRAM module  
Note: All part numbers end with a place code, designating the die revision. Consult factory for  
current revision. Example: HYS 64V16300GU-8-C2, indicates that Rev.C2 dies are used for  
SDRAM components.  
INFINEON Technologies  
2
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Pin Definitions and Functions  
A0-A11  
Address Inputs  
Bank Selects  
WE  
Read/Write Input VSS Ground  
BA0, BA1  
CKE0, CKE1 *)  
CLK0 - CLK3  
Clock Enable  
Clock Input  
SCL Clock for SPD  
SDA Serial Data Out  
N.C. No Connection  
DQ0 - DQ63 Data Input/Output  
CB0-CB7  
Check Bits  
DQMB0 - DQMB7 Data Mask  
(x72 modules only)  
RAS  
CAS  
Row Address Strobe CS0 - CS3 *)  
Chip Select  
–
–
–
–
Column Address  
Strobe  
VDD  
Power (+3.3 V)  
*) CKE1, CS1 and CS3 on two bank modules only  
Address Format  
Part Number  
Rows  
Columns Bank Select Refresh Period Interval  
16M × 64 HYS 64V16300GU 12  
16M × 72 HYS 72V16300GU 12  
32M × 64 HYS 64V32220GU 12  
32M × 72 HYS 72V32220GU 12  
10  
10  
10  
10  
2
2
2
2
4k  
4k  
4k  
4k  
64 ms 15,6 µs  
64 ms 15,6 µs  
64 ms 15,6 µs  
64 ms 15,6 µs  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
VSS  
2
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
3
CS2  
4
DQMB2  
DQMB3  
DU  
DQMB6  
DQMB7  
N.C.  
5
6
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
VDD  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VDD  
8
N.C.  
N.C.  
9
N.C.  
N.C.  
10  
11  
12  
13  
14  
15  
N.C. (CB2)  
N.C. (CB3)  
VSS  
CB6  
CB7  
VSS  
DQ9  
DQ10  
DQ11  
DQ16  
DQ17  
DQ18  
DQ41  
DQ42  
DQ43  
DQ48  
DQ49  
DQ50  
INFINEON Technologies  
3
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Pin Configuration (cont’d)  
PIN# Symbol PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
16  
DQ12  
DQ13  
VDD  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DQ19  
VDD  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ44  
DQ45  
VDD  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
DQ51  
VDD  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
DQ20  
N.C.  
DQ52  
N.C.  
DQ14  
DQ15  
N.C. (CB0)  
N.C. (CB1)  
VSS  
DQ46  
DQ47  
N.C. (CB4)  
N.C. (CB5)  
VSS  
DU  
DU  
CKE1  
VSS  
N.C.  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
RAS  
VSS  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
A9  
CLK3  
N.C.  
A10  
BA0  
BA1  
WP  
A11  
SA0  
VDD  
SDA  
SCL  
VDD  
SA1  
VDD  
CLK1  
N.C.  
SA2  
CLK0  
VDD  
VDD  
Note: Pin names in parentheses are for the x72 ECC versions; example: Pin 106 = (CB5).  
INFINEON Technologies  
4
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
WE  
CS0  
CS  
WE  
CS  
WE  
DQMB0  
DQ(7:0)  
DQM  
DQMB4  
DQM  
DQ0-DQ7  
D0  
DQ(39:32)  
DQ0-DQ7  
D4  
CS  
WE  
CS  
WE  
DQMB1  
DQM  
DQMB5  
DQM  
DQ(15:8)  
DQ0-DQ7  
DQ(47:40)  
DQ0-DQ7  
D5  
D1  
CS  
WE  
DQM  
CB(7:0)  
CS2  
DQ0-DQ7  
D8  
CS  
WE  
CS  
WE  
DQMB2  
DQM  
DQMB6  
DQM  
DQ(23:16)  
DQ0-DQ7  
DQ(55:48)  
DQ0-DQ7  
D6  
D2  
CS  
WE  
CS  
WE  
DQMB3  
DQM  
DQMB7  
DQM  
DQ(31:24)  
DQ0-DQ7  
DQ(63:56)  
DQ0-DQ7  
D7  
D3  
A0-A11, BA0, BA1  
VCC  
D0-D7, (D8)  
D0-D7, (D8)  
D0-D7, (D8)  
D0-D7, (D8)  
D0-D7, (D8)  
D0-D7, (D8)  
E2PROM (256 word x 8 Bit)  
SA0  
SA0  
SA1  
SA2  
SCL  
SA1  
SA2  
SCL  
SDA  
WP  
C0-C15, (C16, C17)  
VSS  
47 k  
Ω
RAS  
CAS  
CKE0  
Clock Wiring  
16 M x 64  
SDRAM + 3.3 pF  
16 M x 72  
5 SDRAM  
CLK0  
CLK1  
CLK2  
CLK3  
4
Termination  
Termination  
Note: D8 is only used in the x72 ECC version and  
all resistor values are 10 Ohm except  
otherwise noted.  
4 SDRAM + 3.3 pF  
Termination  
4 SDRAM+ 3.3 pF  
Termination  
Block Diagram for 16M x 64/72 SDRAM DIMM Modules (HYS 64/72V16300GU)  
INFINEON Technologies  
5
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
CS1  
CS0  
CS  
DQM  
CS  
DQM  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D12  
DQMB0  
DQ(7:0)  
DQMB4  
DQ0-DQ7  
DQ0-DQ7  
DQ(39:32)  
DQ0-DQ7  
D0  
D8  
D4  
CS  
DQM  
CS  
DQM  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D13  
DQMB1  
DQMB5  
DQ(15:8)  
DQ0-DQ7  
DQ0-DQ7  
DQ(47:40)  
DQ0-DQ7  
D1  
D9  
D5  
CS  
CS  
DQM  
DQM  
DQ0-DQ7  
D17  
CB(7:0)  
DQ0-DQ7  
D16  
CS3  
CS2  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D10  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D14  
DQMB2  
DQMB6  
DQ(23:16)  
DQ0-DQ7  
DQ(55:48)  
DQ0-DQ7  
D2  
D6  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D11  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D15  
DQMB3  
DQMB7  
DQ(31:24)  
DQ0-DQ7  
DQ(63:56)  
DQ0-DQ7  
D3  
D7  
A0-A11, BA0, BA1  
VDD  
D0-D15, (D16, D17)  
D0-D15, (D16, D17)  
D0-D7, (D8)  
E2PROM (256 Word x 8 Bit)  
SA0  
SA0  
SA1  
SA2  
SCL  
SA1  
SA2  
SCL  
SDA  
WP  
C0-C31, (C32...C35)  
VSS  
Ω
47 k  
RAS, CAS, WE  
CKE0  
D0-D15, (D16, D17)  
D0-D7, (D16)  
Clock Wiring  
32 M x 64  
VDD  
32 M x 72  
Ω
10 k  
CLK0 4 SDRAM + 3.3 pF 5 SDRAM  
CLK1 4 SDRAM + 3.3 pF 5 SDRAM  
CLK2 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF  
CKE1  
D9-D15, (D17)  
CLK3 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF  
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10  
Ω
except otherwise noted.  
BL01  
Block Diagram for 32M x 64/72 SDRAM DIMM Modules (HYS 64/72V32220GU)  
INFINEON Technologies  
6
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
– 1.0  
– 1.0  
-55  
–
max.  
4.6  
Input / Output voltage relative to VSS  
Power supply voltage on VDD  
VIN, VOUT  
VDD  
V
4.6  
+150  
1
V
Storage temperature range  
TSTG  
PD  
oC  
W
mA  
Power dissipation per SDRAM component  
Data out current (short circuit)  
IOS  
–
50  
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
2.0  
–0.5  
2.4  
–
max.  
VDD + 0.3  
0.8  
Input High Voltage  
VIH  
VIL  
V
Input Low Voltage  
V
Output High Voltage (IOUT = – 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
–
V
0.4  
V
Input Leakage Current, any input  
–40  
40  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
–40  
40  
µA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ±0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
max. max.  
Unit  
max.  
max.  
16M×64 16M×72 32M×64 32M×72  
Input Capacitance  
CI1  
65  
72  
105  
144  
pF  
(A0 to A11, BA0, BA1, RAS, CAS, WE)  
Input Capacitance (CS0 - CS3)  
Input Capacitance (CLK0 - CLK3)  
Input Capacitance (CKE0, CKE1)  
Input Capacitance (DQMB0 - DQMB7)  
CCS  
CCLK  
CCKE  
CI4  
32  
38  
65  
13  
10  
40  
40  
72  
13  
10  
35  
42  
65  
20  
17  
43  
45  
72  
20  
17  
pF  
pF  
pF  
pF  
pF  
Input/Output Capacitance  
(DQ0 - DQ63, CB0 - CB7)  
CIO  
Input Capacitance (SCL, SA0-2)  
Input/Output Capacitance  
CSC  
CSD  
8
8
8
8
8
8
8
8
pF  
pF  
INFINEON Technologies  
7
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Operating Currents per SDRAM Component  
TA = 0 to 70 oC, VDD = 3.3 V ±0.3 V  
Parameter  
Test  
Condition  
Symbol -7 /7.5 -8  
max.  
Unit Note  
1)  
Operating Current  
–
ICC1  
160  
150  
mA  
tRC = tRCMIN., tCK = tCKMIN.  
Outputs open, Burst Length = 4, CL = 3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
1)  
Precharge Standby Current  
in Power Down Mode  
t
CK = min.  
CK = min.  
ICC2P  
1.5  
40  
1.5  
35  
mA  
CS = VIH (min.), CKE ≤ VIL(MAX)  
1)  
Precharge Stand-by Current  
in Non-Power Down Mode  
t
ICC2N  
mA  
CS = VIH (MIN.), CKE ≥ VIH(MIN)  
1)  
No Operating Current  
CKE ≥ VIH(MIN.) ICC3N  
CKE ≤ VIL(MAX.) ICC3P  
50  
10  
45  
10  
mA  
1)  
mA  
tCK = min., CS = VIH(MIN),  
active state (max. 4 banks)  
1), 2)  
Burst Operating Current  
–
–
–
ICC4  
ICC5  
ICC6  
100  
230  
1.5  
90  
mA  
tCK = min.,  
Read command cycling  
1)  
Auto-Refresh Current  
210  
1.5  
mA  
tCK = min.,  
Auto-Refresh command cycling  
1)  
Self-Refresh Current  
mA  
Self-Refresh Mode, CKE = 0.2 V  
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 and 7.5 modules  
and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except for ICC6 and for standby  
currents when tCK = infinity. All values are shown per memory component.  
2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3  
and BL = 4 assumed and the data-out current is excluded  
INFINEON Technologies  
8
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
3), 4)  
AC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
-7.5  
Unit Note  
-7  
-8  
PC133-222 PC133-333 PC100-222  
min. max. min. max. min. max.  
Clock and Access Time  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
tCK  
fCK  
tAC  
–
7.5  
7.5  
–
–
7.5  
10  
–
–
10  
10  
–
–
ns  
ns  
System Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
MHz  
–
–
133  
133  
–
–
133  
100  
–
–
100  
100  
MHz  
4), 5)  
Clock Access Time  
CAS Latency = 3  
CAS Latency = 2  
–
–
5.4  
5.4  
–
–
5.4  
6
–
–
6
6
ns  
ns  
6)  
Clock High Pulse Width  
Clock Low Pulse Width  
tCH  
tCL  
2.5  
2.5  
–
–
2.5  
2.5  
–
–
3
3
–
–
ns  
6)  
ns  
Setup & Hold Parameters  
Input Setup Time  
7)  
tIS  
1.5  
0.8  
–
–
–
1
1.5  
0.8  
–
–
–
1
2
1
–
–
–
1
ns  
7)  
Input Hold Time  
tIH  
tSB  
ns  
8)  
Power Down Mode Entry  
Time  
CLK  
9)  
Power Down Mode Exit  
Setup Time  
tPDE  
tRSC  
1
–
1
–
1
–
CLK  
Mode Register Setup Time  
2
1
–
–
2
1
–
–
2
1
–
–
CLK  
Transition Time (rise and fall) tT  
ns  
–
Common Parameters  
RAS to CAS Delay  
Precharge Time  
tRCD  
15  
15  
42  
60  
14  
–
–
20  
20  
–
–
20  
20  
–
–
ns  
ns  
–
–
–
–
–
tRP  
Active Command Period  
Cycle Time  
tRAS  
tRC  
100k 45  
100k 50  
100k ns  
–
–
67.5  
15  
–
–
70  
16  
–
–
ns  
ns  
Bank-to-Bank Delay Time  
tRRD  
INFINEON Technologies  
9
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
AC Characteristics (cont’d) 3), 4)  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-7  
-7.5  
-8  
PC133-222 PC133-333 PC100-222  
min. max. min. max. min. max.  
CAS to CAS Delay Time  
(same bank)  
tCCD  
1
–
1
–
1
–
CLK  
–
Refresh Cycle  
Refresh Period (4096 cycles) tREF  
–
64  
–
64  
–
64  
ms  
10)  
4)  
Self-Refresh Exit Time  
tSREX  
1
–
1
–
1
–
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
3
0
3
–
–
–
7
2
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns  
Data Out to Low Impedance tLZ  
Data Out to High Impedance tHZ  
ns  
–
11  
ns  
DQM Data Out Disable  
Latency  
tDQZ  
CLK  
–
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
2
0
–
–
CLK  
CLK  
–
–
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
10  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Notes  
3. All AC characteristics are shown on SDRAM component level.  
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must  
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation  
can begin.  
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
5. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter.  
6. Rated at 1.4 V  
7. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.  
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)  
commands must be given to “wake-up” the device.  
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal  
is assumed latched on the next cycle.  
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
11.This is referenced to the time at which the output achieves the open circuit condition, not to  
output voltage levels.  
tCH  
2.4 V  
0.4 V  
1.4 V  
CLOCK  
tT  
tCL  
tIH  
tIS  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
OUTPUT  
1.4 V  
50 pF  
tHZ  
Measurement conditions for  
AC and tOH  
IO.vsd  
t
A Serial Presence Detect storage device—E2PROM—is assembled onto the module. Information about the  
module configuration, speed, etc. is written into the E2PROM device during module production using a Serial  
Presence Detect protocol (I2C synchronous 2-wire bus).  
INFINEON Technologies  
11  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
SPD-Table for PC133-222 Modules:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
16Mx64 16Mx72 32Mx64 32Mx72  
-7  
-7  
-7  
-7  
0
1
2
3
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
80  
08  
04  
0C  
SDRAM  
12  
Number of Row Addresses  
(without BS bits)  
4
Number of Column Addres-  
ses  
10  
0A  
5
6
7
8
9
Number of DIMM Banks  
Module Data Width  
1 / 2  
64 / 72  
0
01  
02  
40  
48  
40  
48  
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
00  
01  
75  
54  
LVTTL  
7.5 ns  
5.4 ns  
10 SDRAM Access time from  
Clock at CL=3  
11 Dimm Config  
none / ECC  
00  
00  
02  
08  
00  
00  
02  
08  
12 Refresh Rate/Type  
Self-Refresh,  
15.6 µs  
80  
0 8  
1 3 S D R A M w i d t h , P r i m a r y  
x 8  
14 Error Checking SDRAM data  
width  
n/a / x8  
15 Minimum clock delay for  
back-to-back random column  
address  
tccd = 1 CLK  
01  
16 Burst Length supported  
17 Number of SDRAM banks  
18 Supported CAS Latencies  
1, 2, 4 & 8  
4
0F  
04  
06  
CAS latency = 2  
& 3  
19 CS Latencies  
20 WE Latencies  
CS latency = 0  
01  
01  
00  
Write latency = 0  
21 SDRAM DIMM module  
attributes  
non buffered/non  
reg.  
22 SDRAM Device Attributes  
:General  
Vcc tol +/- 10%  
0E  
75  
54  
FF  
FF  
0F  
0E  
23 Min. Clock Cycle Time at  
CAS Latency = 2  
7.5 ns  
24 Max. data access time from  
Clock for CL=2  
5.4 ns  
25 Minimum Clock Cycle Time  
at CL = 1  
not supported  
not supported  
15 ns  
26 Maximum Data Access Time  
from Clock at CL=1  
27 Minimum Row Precharge  
Time  
28 Minimum Row Active to Row  
Active delay tRRD  
14 ns  
INFINEON Technologies  
12  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Byte#  
Description  
SPD Entry  
Value  
Hex  
16Mx64 16Mx72 32Mx64 32Mx72  
-7  
-7  
-7  
-7  
29 Minimum RAS to CAS delay  
tRCD  
15 ns  
42 ns  
0F  
2A  
20  
30 Minimum RAS pulse width  
tRAS  
31 Module Bank Density (per  
bank)  
128 MByte  
32 SDRAM input setup time  
33 SDRAM input hold time  
34 SDRAM data input hold time  
1.5 ns  
0.8 ns  
1.5 ns  
0.8 ns  
15  
08  
15  
08  
35 SDRAM data input setup  
time  
62-61 Superset information (may be  
used in future)  
FF  
12  
62 SPD Revision  
Revision 1.2  
63 Checksum for bytes 0 - 62  
CE  
XX  
E0  
XX  
tbd  
XX  
tbd  
XX  
64- Manufacturers information  
125  
126 Frequency Specification  
127 Support Details  
64  
FF  
AF  
FF  
128+ Unused storage locations  
INFINEON Technologies  
13  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
SPD-Table for PC133-333 Modules:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
16Mx64 16Mx72 32Mx64 32Mx72  
-7.5  
-7.5  
-7.5  
-7.5  
0
1
2
3
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
80  
08  
04  
0C  
SDRAM  
12  
Number of Row Addresses  
(without BS bits)  
4
Number of Column Addres-  
ses  
10  
0A  
5
6
7
8
9
Number of DIMM Banks  
Module Data Width  
1 / 2  
64 / 72  
0
01  
02  
40  
48  
40  
48  
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
00  
01  
75  
54  
LVTTL  
7.5 ns  
5.4 ns  
10 SDRAM Access time from  
Clock at CL=3  
11 Dimm Config  
none / ECC  
00  
00  
02  
08  
00  
00  
02  
08  
12 Refresh Rate/Type  
Self-Refresh,  
15.6 µs  
80  
0 8  
1 3 S D R A M w i d t h , P r i m a r y  
x 8  
14 Error Checking SDRAM data  
width  
n/a / x8  
15 Minimum clock delay for  
back-to-back random column  
address  
tccd = 1 CLK  
01  
16 Burst Length supported  
17 Number of SDRAM banks  
18 Supported CAS Latencies  
1, 2, 4 & 8  
4
0F  
04  
06  
CAS latency = 2  
& 3  
19 CS Latencies  
20 WE Latencies  
CS latency = 0  
01  
01  
00  
Write latency = 0  
21 SDRAM DIMM module  
attributes  
non buffered/non  
reg.  
22 SDRAM Device Attributes  
:General  
Vcc tol +/- 10%  
0E  
A0  
60  
FF  
FF  
14  
0F  
23 Min. Clock Cycle Time at  
CAS Latency = 2  
10.0 ns  
24 Max. data access time from  
Clock for CL=2  
6.0 ns  
25 Minimum Clock Cycle Time  
at CL = 1  
not supported  
not supported  
20 ns  
26 Maximum Data Access Time  
from Clock at CL=1  
27 Minimum Row Precharge  
Time  
28 Minimum Row Active to Row  
Active delay tRRD  
15 ns  
INFINEON Technologies  
14  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Byte#  
Description  
SPD Entry  
Value  
Hex  
16Mx64 16Mx72 32Mx64 32Mx72  
-7.5  
-7.5  
-7.5  
-7.5  
29 Minimum RAS to CAS delay  
tRCD  
20 ns  
45 ns  
14  
2D  
20  
30 Minimum RAS pulse width  
tRAS  
31 Module Bank Density (per  
bank)  
128 MByte  
32 SDRAM input setup time  
33 SDRAM input hold time  
34 SDRAM data input hold time  
1.5 ns  
0.8 ns  
1.5 ns  
0.8 ns  
15  
08  
15  
08  
35 SDRAM data input setup  
time  
62-61 Superset information (may be  
used in future)  
FF  
12  
62 SPD Revision  
Revision 1.2  
63 Checksum for bytes 0 - 62  
13  
25  
14  
26  
64- Manufacturers information  
125  
XX  
XX  
XX  
XX  
126 Frequency Specification  
127 Support Details  
64  
FF  
AF  
FF  
128+ Unused storage locations  
INFINEON Technologies  
15  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
SPD-Table for PC100 Modules:  
Byte#  
Description  
SPD Entry  
Value  
Hex  
16Mx64 16Mx72 32Mx64 32Mx72  
-8  
-8  
-8  
-8  
0
1
2
3
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
80  
08  
04  
0C  
SDRAM  
12  
Number of Row Addresses  
(without BS bits)  
4
Number of Column Addres-  
ses  
10  
0A  
5
6
7
8
9
Number of DIMM Banks  
Module Data Width  
1 / 2  
64 / 72  
0
01  
02  
40  
48  
40  
48  
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
00  
01  
A0  
60  
LVTTL  
10.0 ns  
6.0 ns  
10 SDRAM Access time from  
Clock at CL=3  
11 Dimm Config  
none / ECC  
00  
00  
02  
08  
00  
00  
02  
08  
12 Refresh Rate/Type  
Self-Refresh,  
15.6 µs  
80  
0 8  
1 3 S D R A M w i d t h , P r i m a r y  
x 8  
14 Error Checking SDRAM data  
width  
n/a / x8  
15 Minimum clock delay for  
back-to-back random column  
address  
tccd = 1 CLK  
01  
16 Burst Length supported  
17 Number of SDRAM banks  
18 Supported CAS Latencies  
1, 2, 4 & 8  
4
0F  
04  
06  
CAS latency = 2  
& 3  
19 CS Latencies  
20 WE Latencies  
CS latency = 0  
01  
01  
00  
Write latency = 0  
21 SDRAM DIMM module  
attributes  
non buffered/non  
reg.  
22 SDRAM Device Attributes  
:General  
Vcc tol +/- 10%  
0E  
A0  
60  
FF  
FF  
14  
10  
23 Min. Clock Cycle Time at  
CAS Latency = 2  
10.0 ns  
24 Max. data access time from  
Clock for CL=2  
6.0 ns  
25 Minimum Clock Cycle Time  
at CL = 1  
not supported  
not supported  
20 ns  
26 Maximum Data Access Time  
from Clock at CL=1  
27 Minimum Row Precharge  
Time  
28 Minimum Row Active to Row  
Active delay tRRD  
16 ns  
INFINEON Technologies  
16  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Byte#  
Description  
SPD Entry  
Value  
Hex  
16Mx64 16Mx72 32Mx64 32Mx72  
-8  
-8  
-8  
-8  
29 Minimum RAS to CAS delay  
tRCD  
20 ns  
45 ns  
14  
2D  
20  
30 Minimum RAS pulse width  
tRAS  
31 Module Bank Density (per  
bank)  
128 MByte  
32 SDRAM input setup time  
33 SDRAM input hold time  
34 SDRAM data input hold time  
2 ns  
1 ns  
2 ns  
1 ns  
20  
10  
20  
10  
35 SDRAM data input setup  
time  
62-61 Superset information (may be  
used in future)  
FF  
12  
62 SPD Revision  
Revision 1.2  
100 MHz  
63 Checksum for bytes 0 - 62  
71  
83  
72  
84  
64- Manufacturers information  
125  
XX  
XX  
XX  
XX  
126 Frequency Specification  
127 Support Details  
64  
FF  
AF  
FF  
128+ Unused storage locations  
INFINEON Technologies  
17  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Package Outlines  
L-DIM-168-30 (JEDEC MO-161-BA)  
SDRAM DIMM Module Package  
133.35+- 0.15  
127.35  
4 max.  
*)  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27 +- 0.1  
3
1.27  
42.18  
91 x 1.27 = 115.57  
124 125  
2
85 94  
95  
168  
*)  
3 min.  
3
Detail of Contacts  
*) on ECC modules only  
1
1.27  
L-DIM-168-30  
Note: All tolerances according to JEDEC standard  
INFINEON Technologies  
18  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Package Outlines  
L-DIM-168-33 (JEDEC MO-161-BA)  
SDRAM DIMM Module Package  
HYS 64/72V16300GU  
133.35+- 0.15  
127.35  
3 max.  
*)  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27+ 0.1  
-
3
1.27  
42.18  
91 x 1.27 = 115.57  
124 125  
2
85 94  
95  
168  
3 min.  
3
Detail of Contacts  
*) on ECC modules only  
1
1.27  
L-DIM-168-33  
Note: All tolerances according to JEDEC standard  
INFINEON Technologies  
19  
9.01  
HYS 64/72V16300/32220GU  
SDRAM-Modules  
Update Releases:  
June 1, 1999  
June 17, 1999  
August 3, 1999  
August 5, 1999  
August 23, 1999  
Sept.30, 1999  
Dec. 2, 1999  
Explanation for factory specific code in part numbers added  
Byte 22 for PC100 modules changed from 06 to 0E  
PC133 spec incorpoated  
SPD tables added  
Byte 126 changed to 64h for PC133 modules  
Some errors corrected, checksums added  
Some timing parameters adjusted according to INTELs PC133 specification  
-8A speedsort removed  
Feb. 23, 2000  
ICC currents updated in accordance to 128Mbit component datasheets  
Capacitance values updated according to module C-measurements  
Block Diagrams corrected, R&L template  
10.5.2000  
21.8.2000  
06.09.2001  
Reference to JEDEC MO-161-BA added  
PC133-222 modules “-7 speed sort” added  
SCR : Absolute Maximum Ratings table added  
INFINEON Technologies  
20  
9.01  
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