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HYS72D128320HU-6-C

型号：

HYS72D128320HU-6-C

描述：

184针无缓冲双数据速率SDRAM[ 184-Pin Unbuffered Double Data Rate SDRAM ]

品牌：

QIMONDA[ QIMONDA AG ]

页数：

39 页

PDF大小：

1112 K

下载PDF手册

September 2006

HYS64D32301HU–[5/6]–C

HYS[72/64]D64300HU–[5/6]–C

HYS[64/72]D128320HU–[5/6]–C

184-Pin Unbuffered Double Data Rate SDRAM

UDIMM

DDR SDRAM

RoHS Compliant Products

Internet Data Sheet

Rev. 1.21

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

HYS64D32301HU–[5/6]–C, HYS[72/64]D64300HU–[5/6]–C, HYS[64/72]D128320HU–[5/6]–C

Revision History: 2006-09, Rev. 1.21

Page

Subjects (major changes since last revision)

Adapted internet edition

All

Previous Revision: Rev. 1.20, 2005-12

changed component configuration for 256MB to 32M x16

changed DDR400 t_RFCfrom 70 ns to 65 ns

Previous Revision: Rev. 1.10, 2005-05

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_rev400 / 3.2 QAG / 2006-08-01

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Overview

This chapter gives an overview of the 184-Pin Unbuffered Double Data Rate SDRAM product family and describes its main

characteristics.

1.1

Features

•

184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Workstation main memory applications

One rank 32M ×64, 64M ×64, 64M ×72 ,and two ranks 128M ×64 ,128M ×72 organization

Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) and +2.6V (±0.1V) power supply

for DDR400

•

Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package

Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

RAS-lockout supported t_RAP=t_RCD

All inputs and outputs SSTL_2 compatible

Serial Presence Detect with E²PROM

Standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.

Standard reference layout for raw cards: A, B and C

Gold plated contacts

RoHS Compliant Product¹⁾

TABLE 1

Performance

Part Number Speed Code

–5

–6

Unit

Speed Grade

Component

Module

@CL3

DDR400B

PC3200–3033

200

DDR333B

PC2700–2533

166

—

max. Clock Frequency

f_CK3

MHz

@CL2.5

@CL2

f_CK2.5

f_CK2

166

133

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

1.2

Description

The HYS64D32301HU–[5/6]–C, HYS[72/64]D64300HU–

[5/6]–C, HYS[64/72]D128320HU–[5/6]–C, and are industry

designed with 512Mbit Double Data Rate Synchronous

DRAMs. A variety of decoupling capacitors are mounted on

the printed circuit board. The DIMMs feature serial presence

detect (SPD) based on a serial E²PROM device using the 2-

pin I2C protocol. The first 128 bytes are programmed with

configuration data and the second 128 bytes are available to

the customer

standard

Data Rate SDRAM (UDIMM)

184-Pin Unbuffered Double

organized as

32M × 64 (256 MB), 64M × 64 (512 MB), 128M × 64 (1 GB)

for non-parity and 64M × 72 (512 MB), 128M × 72 (1 GB) for

ECC main memory applications. The memory array is

TABLE 2

Ordering Information for Lead-Free Products (RoHSCompliant Product)

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM Technology

PC3200 (CL=3.0)

HYS64D32301HU–5–C

HYS64D64300HU–5–C

HYS72D64300HU–5–C

HYS64D128320HU–5–C

HYS72D128320HU–5–C

PC2700 (CL=2.5)

PC3200U–30331–C3

PC3200U–30331–A1

PC3200U–30331–B2

one rank 256 MB DIMM

one rank 512 MB DIMM

one rank 512 MB ECC-DIMM

two ranks 1 GB DIMM

512 Mbit (×16)

512 Mbit (×8)

two ranks 1 GB ECC-DIMM

HYS64D32301HU–6–C

HYS64D64300HU–6–C

HYS72D64300HU–6–C

HYS64D128320HU–6–C

HYS72D128320HU–6–C

PC2700U–25331–C3

PC2700U–25331–A1

PC2700U–25331–B2

one rank 256 MB DIMM

one rank 512 MB DIMM

one rank 512 MB ECC-DIMM

two ranks 1 GB DIMM

512 Mbit (×16)

512 Mbit (×8)

two ranks 1 GB ECC-DIMM

1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:

HYS64D128320HU–5–C, indicating Rev.C die are used for SDRAM components.

2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example

“30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC

SPD code definition version 0, and the Raw Card used for this module.

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

The pin configuration of the Unbuffered DDR SDRAM DIMM

is listed by function in Table 3 (184 pins). The abbreviations

used in columns Pin and Buffer Type are explained in Table 4

and Table 5 respectively. The pin numbering is depicted in

Figure 1.

TABLE 3

Pin Configuration of UDIMM

Pin#

Name

Type

Buffer

Type

Function

Clock Signals

137

CK0

SSTL

–

Clock Signals 2:0

CK1

CK2

CK0

SSTL

–

138

Complement Clock Signals 2:0

CK1

CK2

CKE0

CKE1

SSTL

Clock Enable Rank 0

Clock Enable Rank 1

Note: 2-rank module

Note: 1-rank module

111

–

Control Signals

157

158

SSTL

Chip Select Rank 0

Chip Select Rank 1

Note: 2-rank module

Note: 1-rank module

Row Address Strobe

Column Address Strobe

Write Enable

–

154

RAS

CAS

SSTL

Address Signals

BA0

BA1

SSTL

Bank Address Bus 2:0

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin#

Name

Type

Buffer

Type

Function

SSTL

Address Bus 11:0

130

125

122

Address Bus 11:0

141

A10

A11

A12

118

115

Address Signal 12

Note: Module based on 256 Mbit or larger dies

Note: 128 Mbit based module

Address Signal 13

–

167

A13

SSTL

Note: 1 Gbit based module

–

Note: Module based on 512 Mbit or smaller dies

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin#

Name

Type

Buffer

Type

Function

Data Signals

DQ0

I/O

SSTL

Data Bus 63:0

DQ1

DQ2

DQ3

105

106

109

110

114

117

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin#

Name

Type

Buffer

Type

Function

121

123

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

I/O

SSTL

Data Bus 63:0

126

127

131

133

146

147

150

151

153

155

161

162

165

166

170

171

174

175

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin#

Name

Type

Buffer

Type

Function

178

179

DQ62

DQ63

CB0

I/O

SSTL

–

Data Bus 63:0

Check Bit 0

Check Bit 1

Check Bit 2

Check Bit 3

Check Bit 4

Check Bit 5

Check Bit 6

Check Bit 7

Data Strobe Bus 7:0

CB1

SSTL

–

CB2

SSTL

–

CB3

SSTL

–

134

135

142

144

CB4

SSTL

–

CB5

SSTL

–

CB6

SSTL

–

CB7

SSTL

–

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

SSTL

–

Data Strobe 8

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

SSTL

–

Data Mask Bus 7:0

107

119

129

149

159

169

177

140

Data Mask 8

EEPROM

SCL

CMOS

Serial Bus Clock

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin#

Name

Type

Buffer

Type

Function

SDA

SA0

SA1

SA2

I/O

Serial Bus Data

181

182

183

CMOS

Slave Address Select Bus 2:0

Power Supplies

V_REF

–

I/O Reference Voltage

EEPROM Power Supply

I/O Driver Power Supply

184

V_DDSPD

V_DDQ

PWR

15,

22,

30,

54,

62,

77,

96,

104,

112,

128,

136,

143,

156,

164,

172,

180

V_DD

PWR

–

Power Supply

38,

46,

70,

85,

108,

120,

148,

168

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin#

Name

Type

Buffer

Type

Function

V_SS

GND

–

Ground Plane

11,

18,

26,

34,

42,

50,

58,

66,

74,

81,

89,

93,

100,

116,

124,

132,

139,

145,

152,

160,

176

Other Pins

V_DDID

–

V_DDIdentification

Not connected

10,

71,

90,

101,

102,

103,

113,

163,

173

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

TABLE 4

Abbreviations for Pin Type

Abbreviation

Description

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

I/O

PWR

GND

Ground

Not Connected

TABLE 5

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

Serial Stub Terminated Logic (SSTL2)

Low Voltage CMOS

LV-CMOS

CMOS

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tristate,

and allows multiple devices to share as a wire-OR.

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

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Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

FIGURE 1

Pin Configuration 184-Pin, UDIMM

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Notes

2. DQ, DQS, DM resistors are 22 Ω ±5 %

3. BAn, An, RAS, CAS, WE resistors are 3 Ω ±5 %

1. V_DD= V_DDQ, therefore V_DDIDstrap open

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

TABLE 6

Address Format

Density

Organization

Memory

Ranks

SDRAMs

# of

SDRAMs

# of row/bank/

columns bits

Refresh

Period Interval

256 MB

512 MB

1 GB

32M ×64

64M ×64

64M ×72

128M ×64

128M ×72

32M ×16

64M ×8

13/2/10

13/2/11

64 ms

7.8 ms

1 GB

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Electrical Characteristics

3.1

Operating Conditions

TABLE 12

Absolute Maximum Ratings

Parameter

Symbol

Values

Unit Note/ Test

Condition

min.

typ. max.

Voltage on I/O pins relative to V_SS

Voltage on inputs relative to V_SS

Voltage on V_DDsupply relative to V_SS

Voltage on V_DDQsupply relative to V_SS

Operating temperature (ambient)

Storage temperature (plastic)

V_IN, V_OUT

V_IN

–0.5

–1

–

_DDQ+ 0.5

–

+3.6

+70

+150

–

V_DD

–

V_DDQ

T_A

–

°C

T_STG

-55

–

Power dissipation (per SDRAM component)

Short circuit output current

I_OUT

–

Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress

rating only, and functional operation should be restricted to recommended operation conditions. Exposure

to absolute maximum rating conditions for extended periods of time may affect device reliability and

exceeding only one of the values may cause irreversible damage to the integrated circuit.

TABLE 13

Electrical Characteristics and DC Operating Conditions

Parameter

Symbol

Values

Unit Note/Test Condition ¹⁾

Min.

Typ.

Max.

Device Supply Voltage

Output Supply Voltage

EEPROM supply voltage

V_DD

2.3

2.5

2.3

2.5

2.3

2.5

2.6

2.5

2.6

2.5

2.7

3.6

fck ≤ 166 MHz

fck ≤ 166 MHz ²⁾

fck ≤ 166 MHz ³⁾

fck ≤ 166 MHz ²⁾³⁾

—

V_DD

V_DDQ

V_DDSPD

Supply Voltage, I/O Supply

Voltage

V_SS

—

V_SSQ

V_REF

V_TT

Input Reference Voltage

0.49 × V_DDQ0.5 × V_DDQ0.51 × V_DDQ

V_REF– 0.04 V_REF+ 0.04

I/O Termination Voltage

(System)

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Parameter

Symbol

Values

Typ.

Unit Note/Test Condition ¹⁾

Min.

Max.

Input High (Logic1) Voltage

Input Low (Logic0) Voltage

V_IH(DC)

V_IL(DC)

V_IN(DC)

V_REF+ 0.15

–0.3

V_DDQ+ 0.3

V_REF– 0.15

V_DDQ+ 0.3

Input Voltage Level,

CK and CK Inputs

–0.3

6)7)

Input Differential Voltage,

CK and CK Inputs

V_ID(DC)

0.36

0.71

–2

V_DDQ+ 0.6

VI-Matching Pull-up Current VI_Ratio

to Pull-down Current

1.4

—

µA

Input Leakage Current

I_I

Any input 0 V ≤ V_IN≤ V_DD;

All other pins not under test

= 0 V ⁹⁾

Output Leakage Current

I_OZ

–5

µA

DQs are disabled;

0 V ≤ V_OUT≤ V_DDQ

Output High Current, Normal I_OH

Strength Driver

—

–16.2

—

mA V_OUT

1.95 V

Output Low Current, Normal I_OL

Strength Driver

16.2

mA V_OUT= 0.35 V

1) 0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);

2) DDR400 conditions apply for all clock frequencies above 166 MHz

3) Under all conditions, V_DDQmust be less than or equal to V_DD

4) Peak to peak AC noise on V_REFmay not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in V_DDQ

5) _TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to V_REF, and

must track variations in the DC level of V_REF

6) Inputs are not recognized as valid until V_REFstabilizes.

7) V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and

voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between

pull-up and pull-down drivers due to process variation.

9) Values are shown per pin.

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

3.2

I_DDSpecification and Conditions

TABLE 14

I_DDConditions

Parameter

Symbol

Operating Current 0

I_DD0

one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

Operating Current 1

I_DD1

one bank; active/read/precharge; Burst Length = 4; see component data sheet.

Precharge Power-Down Standby Current

all banks idle; power-down mode; CKE ≤ V_IL,MAX

I_DD2P

I_DD2F

Precharge Floating Standby Current

CS ≥ V_IH,,MIN, all banks idle; CKE ≥ V_IH,MIN

;

address and other control inputs changing once per clock cycle; V_IN= V_REFfor DQ, DQS and DM.

Precharge Quiet Standby Current

I_DD2Q

CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IH,MIN; V_IN= V_REFfor DQ, DQS and DM;

address and other control inputs stable at ≥ V_IH,MINor ≤ V_IL,MAX

Active Power-Down Standby Current

one bank active; power-down mode; CKE ≤ V_ILMAX; V_IN= V_REFfor DQ, DQS and DM.

I_DD3P

I_DD3N

Active Standby Current

one bank active; CS ≥ V_IH,MIN; CKE ≥ V_IH,MIN; t_RC= t_RAS,MAX

DQ, DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle.

;

Operating Current Read

I_DD4R

one bank active; Burst Length = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; I_OUT= 0 mA

Operating Current Write

I_DD4W

one bank active; Burst Length = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B

Auto-Refresh Current

I_DD5

I_DD6

I_DD7

_RC= t_RFCMIN, burst refresh

Self-Refresh Current

CKE ≤ 0.2 V; external clock on

Operating Current 7

four bank interleaving with Burst Length = 4; see component data sheet.

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

TABLE 15

_DDSpecification for HYS[64/72]D[32/64/128]3xxHU–5–C

Product Type

Unit Note ¹⁾²⁾

Organization

256MB

×64

512MB

×64

512MB

×72

1GB

×64

1GB

×72

1 Rank

–5

1 Rank

–5

1 Rank

–5

2 Ranks

–5

2 Ranks

–5

Symbol

Typ. Max.

Typ.

Max.

Typ.

Max.

Typ.

Max.

Typ.

Max.

I_DD0

300

360

440

480

560

600

680

540

630

680

770

760

840

940

1020

860

950

1050

1140

3)4)

I_DD1

I_DD2P

I_DD2F

I_DD2Q

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5

100

120

200

140

100

280

640

680

1160

240

180

130

340

720

760

1520

230

150

110

320

720

770

1310

270

210

140

380

810

860

1710

400

270

190

560

920

960

1440

480

370

260

670

1060

1100

1860

450

310

220

630

1040

540

410

290

760

1190

150

440

460

580

180

540

760

3)4)

1080 1230

620

2090

I_DD6

3)4)

I_DD7

840

1000

1560

1840

1760

2070

1840

2180

2070

2450

1) DRAM component currents only

2) Test condition for maximum values: V_DD= 2.7 V, T_A= 10 °C

3) The module I_DDxvalues are calculated from the component I_DDxdata sheet values as:

m × I_DDx[component] + n × I_DD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules

4) DQ I/O (I_DDQ) currents are not included into calculations: module I_DDvalues will be measured differently depending on load conditions

5) The module I_DDxvalues are calculated from the corrponent I_DDxdata sheet values as: (m + n) × I_DDx[component]

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

TABLE 16

_DDSpecification for HYS[64/72]D[32/64/128]3xxHU–6–C

Product Type

Unit Note ¹⁾²⁾

Organization

256MB

×64

512MB

×64

512MB

×72

1GB

×64

1GB

×72

1 Rank

–6

1 Rank

–6

1 Rank

–6

2 Ranks

–6

2 Ranks

–6

Symbol

Typ. Max.

Typ.

Max.

Typ.

Max.

Typ.

Max.

Typ.

Max.

I_DD0

280

320

340

380

480

520

560

640

540

590

630

720

740

780

860

940

830

870

960

1050

3)4)

I_DD1

I_DD2P

I_DD2F

I_DD2Q

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5

100

170

120

200

180

120

300

680

720

1400

190

140

100

290

630

680

1170

14.4

1580

230

200

140

330

770

810

1580

340

240

180

510

820

860

1300

25.6

1660

400

350

240

590

980

1020

1700

380

270

200

580

920

960

1460

28.8

1860

450

400

270

670

1100

1140

1910

130

380

400

520

6.4

760

160

460

480

700

260

560

600

1040

12.8

1400

3)4)

I_DD6

3)4)

I_DD7

920

1640

1850

1940

2180

1) DRAM component currents only

2) Test condition for maximum values: V_DD= 2.6 V, T_A= 10 °C

3) The module I_DDxvalues are calculated from the component I_DDxdata sheet values as:

m × I_DDx[component] + n × I_DD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules

4) DQ I/O (I_DDQ) currents are not included into calculations: module I_DDvalues will be measured differently depending on load conditions

5) The module I_DDxvalues are calculated from the corrponent I_DDxdata sheet values as: (m + n) × I_DDx[component]

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

3.3

AC Characteristics

TABLE 17

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter

Symbol –5

–6

Unit Note/ Test

Condition ¹⁾

DDR400B

DDR333

Min.

Max.

Min.

Max.

2)3)4)5)

DQ output access time from

CK/CK

t_AC

–0.7

+0.5

–0.7

+0.7

2)3)4)5)

CK high-level width

Clock cycle time

t_CH

t_CK

0.45

0.55

0.45

0.55

t_CK

CL = 3.0 ^2)3)4)5)

CL = 2.5 ^2)3)4)5)

CL = 2.0 ^2)3)4)5)

7.5

0.45

2)3)4)5)

CK low-level width

t_CL

0.45

0.55

2)3)4)5)6)

Auto precharge write recovery + t_DAL

precharge time

(t_WR/t_CK) + (t_RP/t_CK)

2)3)4)5)

DQ and DM input hold time

t_DH

0.4

—

0.45

1.75

—

2)3)4)5)6)

DQ and DM input pulse width

(each input)

t_DIPW

1.75

2)3)4)5)

DQS output access time from

CK/CK

t_DQSCK

–0.5

0.35

—

+0.5

—

–0.6

0.35

—

+0.6

—

t_CK

DQS input low (high) pulse width t_DQSL,H

(write cycle)

DQS-DQ skew (DQS and

associated DQ signals)

Write command to 1^stDQS

latching transition

t_DQSQ

t_DQSS

t_DS

+0.40

1.25

+0.45

1.25

TSOPII ^2)3)4)5)

2)3)4)5)

0.72

0.75

2)3)4)5)

DQ and DM input setup time

0.4

0.2

—

0.45

0.2

—

DQS falling edge hold time from t_DSH

CK (write cycle)

t_CK

2)3)4)5)

DQS falling edge to CK setup

time (write cycle)

t_DSS

0.2

—

0.2

—

t_CK

2)3)4)5)

Clock Half Period

t_HP

t_HZ

min. (t_CL, t_CH

)

—

min. (t_CL, t_CH

–0.7

)

—

2)3)4)5)7)

Data-out high-impedance time

from CK/CK

+0.7

Address and control input hold

time

t_IH

0.6

0.7

2.2

—

0.75

0.8

—

fast slew rate

3)4)5)6)8)

slow slew rate

3)4)5)6)8)

2)3)4)5)9)

Control and Addr. input pulse

width (each input)

t_IPW

2.2

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Parameter

Symbol –5

DDR400B

–6

Unit Note/ Test

Condition ¹⁾

DDR333

Min.

Max.

Min.

Max.

Address and control input setup t_IS

time

0.6

—

0.75

—

t_CK

fast slew rate

3)4)5)6)10)

0.7

–0.7

—

0.8

–0.7

—

slow slew rate

3)4)5)6)10)

2)3)4)5)7)

2)3)4)5)

Data-out low-impedance time

from CK/CK

t_LZ

+0.7

—

+0.7

—

Mode register set command

cycle time

t_MRD

DQ/DQS output hold time

Data hold skew factor

t_QH

t_HP– t_QHS

—

t_HP– t_QHS

—

t_QHS

t_RAP

t_RAS

t_RC

+0.50

—

+0.55

—

TSOPII ^2)3)4)5)

2)3)4)5)

Active to Autoprecharge delay

Active to Precharge command

t_RCD

2)3)4)5)

70E+3 42

70E+3 ns

Active to Active/Auto-refresh

command period

—

2)3)4)5)

Active to Read or Write delay

t_RCD

t_REFI

—

2)3)4)5)8)

Average Periodic Refresh

Interval

7.8

µs

2)3)4)5)

Auto-refresh to Active/Auto-

refresh command period

t_RFC

—

2)3)4)5)

Precharge command period

Read preamble

t_RP

—

t_CK

t_RPRE

t_RPST

t_RRD

0.9

0.40

1.1

0.60

—

0.9

0.40

1.1

0.60

—

Read postamble

Active bank A to Active bank B

command

2)3)4)5)

Write preamble

t_WPRE

t_WPRES

t_WPST

t_WR

0.25

—

0.25

—

t_CK

2)3)4)5)11)

2)3)4)5)12)

2)3)4)5)

Write preamble setup time

Write postamble

—

0.40

0.60

—

0.40

0.60

—

Write recovery time

2)3)4)5)

Internal write to read command t_WTR

delay

—

2)3)4)5)

Exit self-refresh to non-read

command

t_XSNR

—

Exit self-refresh to read

command

t_XSRD

200

t_CK

1) 0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V (DDR333); V_DDQ= 2.6 V ± 0.1 V, V_DD= +2.6 V ± 0.1 V (DDR400)

2) Input slew rate ≥ 1 V/ns for DDR400, DDR333

3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals

other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.

4) Inputs are not recognized as valid until V_REFstabilizes.

5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT

6) For each of the terms, if not already an integer, round to the next highest integer. t_CKis equal to the actual system clock cycle time.

7) _HZand t_LZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific

voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

9) These parameters guarantee device timing, but they are not necessarily tested on each device.

10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured

between V_OH(ac)and V_OL(ac)

11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition

is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the

bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from

HIGH to LOW at this time, depending on tDQSS.

12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Codes

This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands

for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.

List of SPD Code Tables

•

Table 18 “SPD Codes for HYS64D32301HU–[5/6]–C” on Page 29

Table 19 “SPD Codes for HYS[72/64]D64300HU–[5/6]–C” on Page 32

Table 20 “SPD Codes for HYS[64/72]D128320HU–[5/6]–C” on Page 36

TABLE 18

SPD Codes for HYS64D32301HU–[5/6]–C

Product Type

Organization

HYS64D32301HU–5–C

HYS64D32301HU–6–C

256MB

×64

1 Rank (×16)

PC3200U–30331

Rev. 1.0

1 Rank (×16)

PC2700U–25331

Rev. 1.0

Label Code

JEDEC SPD Revision

Byte#

Description

HEX

Programmed SPD Bytes in E²PROM

Total number of Bytes in E²PROM

Memory Type (DDR = 07h)

Number of Row Addresses

Number of Column Addresses

Number of DIMM Ranks

Data Width (LSB)

Data Width (MSB)

Interface Voltage Levels

t_CK@ CL_max(Byte 18) [ns]

t_ACSDRAM @ CL_max(Byte 18) [ns]

Error Correction Support

Refresh Rate

Primary SDRAM Width

Error Checking SDRAM Width

t_CCD[cycles]

Burst Length Supported

Number of Banks on SDRAM Device

CAS Latency

CS Latency

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

HYS64D32301HU–5–C

HYS64D32301HU–6–C

256MB

×64

1 Rank (×16)

PC3200U–30331

Rev. 1.0

HEX

1 Rank (×16)

PC2700U–25331

Rev. 1.0

Label Code

JEDEC SPD Revision

Byte#

Description

HEX

Write Latency

DIMM Attributes

Component Attributes

t_CK@ CL_max-0.5 (Byte 18) [ns]

t_ACSDRAM @ CL_max-0.5 [ns]

_CK@ CL_max-1 (Byte 18) [ns]

_ACSDRAM @ CL_max-1 [ns]

t_RPmin[ns]

_RRDmin[ns]

_RCDmin[ns]

t_RASmin[ns]

Module Density per Rank

t_AS,t_CS[ns]

t_AH,t_CH[ns]

_DS[ns]

_DH[ns]

36 - 40 Not used

t_RCmin[ns]

_RFCmin[ns]

t_CKmax[ns]

_DQSQmax[ns]

_QHSmax[ns]

not used

DIMM PCB Height

48 - 61 Not used

SPD Revision

Checksum of Byte 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

HYS64D32301HU–5–C

HYS64D32301HU–6–C

256MB

×64

1 Rank (×16)

PC3200U–30331

Rev. 1.0

HEX

1 Rank (×16)

PC2700U–25331

Rev. 1.0

Label Code

JEDEC SPD Revision

Byte#

Description

HEX

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Part Number, Char 1

Part Number, Char 2

Part Number, Char 3

Part Number, Char 4

Part Number, Char 5

Part Number, Char 6

Part Number, Char 7

Part Number, Char 8

Part Number, Char 9

Part Number, Char 10

Part Number, Char 11

Part Number, Char 12

Part Number, Char 13

Part Number, Char 14

Part Number, Char 15

Part Number, Char 16

Part Number, Char 17

Part Number, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

TABLE 19

SPD Codes for HYS[72/64]D64300HU–[5/6]–C

Product Type

Organization

512MB

×64

×72

1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

Programmed SPD Bytes in E²PROM

Total number of Bytes in E²PROM

Memory Type (DDR = 07h)

Number of Row Addresses

Number of Column Addresses

Number of DIMM Ranks

Data Width (LSB)

Data Width (MSB)

Interface Voltage Levels

t_CK@ CL_max(Byte 18) [ns]

t_ACSDRAM @ CL_max(Byte 18) [ns]

Error Correction Support

Refresh Rate

Primary SDRAM Width

Error Checking SDRAM Width

t_CCD[cycles]

Burst Length Supported

Number of Banks on SDRAM Device

CAS Latency

CS Latency

Write Latency

DIMM Attributes

Component Attributes

t_CK@ CL_max-0.5 (Byte 18) [ns]

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

512MB

×64

×72

1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

t_ACSDRAM @ CL_max-0.5 [ns]

t_CK@ CL_max-1 (Byte 18) [ns]

t_ACSDRAM @ CL_max-1 [ns]

t_RPmin[ns]

t_RRDmin[ns]

t_RCDmin[ns]

_RASmin[ns]

Module Density per Rank

t_AS,t_CS[ns]

_AH,t_CH[ns]

_DS[ns]

t_DH[ns]

36 - 40 Not used

t_RCmin[ns]

t_RFCmin[ns]

t_CKmax[ns]

t_DQSQmax[ns]

t_QHSmax[ns]

not used

DIMM PCB Height

48 - 61 Not used

SPD Revision

Checksum of Byte 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

512MB

×64

×72

1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Part Number, Char 1

Part Number, Char 2

Part Number, Char 3

Part Number, Char 4

Part Number, Char 5

Part Number, Char 6

Part Number, Char 7

Part Number, Char 8

Part Number, Char 9

Part Number, Char 10

Part Number, Char 11

Part Number, Char 12

Part Number, Char 13

Part Number, Char 14

Part Number, Char 15

Part Number, Char 16

Part Number, Char 17

Part Number, Char 18

Module Revision Code

Test Program Revision Code

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

512MB

×64

×72

1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

TABLE 20

SPD Codes for HYS[64/72]D128320HU–[5/6]–C

Product Type

Organization

1 GByte

×64

×72

2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

Programmed SPD Bytes in E²PROM

Total number of Bytes in E²PROM

Memory Type (DDR = 07h)

Number of Row Addresses

Number of Column Addresses

Number of DIMM Ranks

Data Width (LSB)

Data Width (MSB)

Interface Voltage Levels

t_CK@ CL_max(Byte 18) [ns]

t_ACSDRAM @ CL_max(Byte 18) [ns]

Error Correction Support

Refresh Rate

Primary SDRAM Width

Error Checking SDRAM Width

t_CCD[cycles]

Burst Length Supported

Number of Banks on SDRAM Device

CAS Latency

CS Latency

Write Latency

DIMM Attributes

Component Attributes

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

1 GByte

×64

×72

2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

t_CK@ CL_max-0.5 (Byte 18) [ns]

_ACSDRAM @ CL_max-0.5 [ns]

_CK@ CL_max-1 (Byte 18) [ns]

t_ACSDRAM @ CL_max-1 [ns]

t_RPmin[ns]

t_RRDmin[ns]

t_RCDmin[ns]

_RASmin[ns]

Module Density per Rank

t_AS,t_CS[ns]

_AH,t_CH[ns]

_DS[ns]

t_DH[ns]

36 - 40 Not used

t_RCmin[ns]

t_RFCmin[ns]

t_CKmax[ns]

t_DQSQmax[ns]

t_QHSmax[ns]

not used

DIMM PCB Height

48 - 61 Not used

SPD Revision

Checksum of Byte 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

1 GByte

×64

×72

2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Part Number, Char 1

Part Number, Char 2

Part Number, Char 3

Part Number, Char 4

Part Number, Char 5

Part Number, Char 6

Part Number, Char 7

Part Number, Char 8

Part Number, Char 9

Part Number, Char 10

Part Number, Char 11

Part Number, Char 12

Part Number, Char 13

Part Number, Char 14

Part Number, Char 15

Part Number, Char 16

Part Number, Char 17

Part Number, Char 18

Module Revision Code

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Product Type

Organization

1 GByte

×64

×72

2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code

PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Rev. 1.0

HEX

Byte#

Description

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outlines

Package Outline for HYS64D32301HU–[5/6]–C

FIGURE 8

Package Outline UDIMM Raw Card C (L-DIM-184-18)

133.35

128.95

0.15 A B C

2.7 MAX.

2.36

6.62

2.175

±0.1

ø0.1 A B C

64.77

0.4

6.35

±0.1

1.27

49.53

95 x 1.27 = 120.65

±0.1

1.8

0.1 A B C

184

3 MIN.

Detail of contacts

1.27

±0.05

0.1 A B C

1) On ECC modules only

Burr max. 0.4 allowed

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outline for HYS64D64300HU–[5/6]–C

FIGURE 9

Package Outline UDIMM Raw Card A (L-DIM-184-32)

133.35

128.95

0.15

A B C

2.7 MAX.

2.36

6.62

2.175

±0.1

ø0.1

A B C

64.77

0.4

6.35

±0.1

1.27

49.53

95 x 1.27 = 120.65

±0.1

1.8

0.1

A B C

184

3 MIN.

Detail of contacts

1.27

±0.05

0.1 A B C

Burr max. 0.4 allowed

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outline for HYS72D64300HU–[5/6]–C

FIGURE 10

Package Outline UDIMM Raw Card A (L-DIM-184-30)

133.35

128.95

0.15

A B C

2.7 MAX.

2.36

6.62

2.175

±0.1

ø0.1

A B C

64.77

0.4

6.35

±0.1

1.27

49.53

95 x 1.27 = 120.65

±0.1

1.8

0.1

A B C

184

3 MIN.

Detail of contacts

1.27

±0.05

0.1

A B C

1) On ECC modules only

Burr max. 0.4 allowed

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outline for HYS[64/72]D128320HU–[5/6]–C

FIGURE 11

Package Outline UDIMM Raw Card B (L-DIM-184-31)

133.35

128.95

0.15

A B C

4 MAX.

2.36

6.62

2.175

±0.1

ø0.1

A B C

64.77

0.4

6.35

±0.1

1.27

49.53

95 x 1.27 = 120.65

±0.1

1.8

0.1

A B C

184

3 MIN.

Detail of contacts

1.27

±0.05

0.1

A B C

1) On ECC modules only

Burr max. 0.4 allowed

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Table of Contents

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

I_DDSpecification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

3.2

3.3

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Rev. 1.21, 2006-09

03292006-RA8T-MSZL

Internet Data Sheet

Edition 2006-09

Published by Qimonda AG

Gustav-Heinemann-Ring 212

D-81739 München, Germany

Legal Disclaimer

The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics

(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,

including without limitation warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please

contact your nearest Qimonda Office.

Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a

failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect

the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human

body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health

of the user or other persons may be endangered.

www.qimonda.com

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