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HYS64V64220GU-7-D

型号：

HYS64V64220GU-7-D

描述：

3.3 V 64M ×64 /72- BIT， 512MByte SDRAM模块168针无缓冲DIMM模块[ 3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules 168-pin Unbuffered DIMM Modules ]

品牌：

INFINEON[ Infineon ]

页数：

15 页

PDF大小：

258 K

下载PDF手册
HYS 64/72V64220GU  
SDRAM-Modules  
3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules  
168-pin Unbuffered DIMM Modules  
•
168-pin unbuffered 8 Byte Dual-In-Line  
SDRAM Modules for PC main memory  
applications using 256Mbit technology.  
•
•
Single + 3.3 V (± 0.3 V) power supply  
Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
•
•
•
•
•
PC100-222, PC133-333 & PC133-222  
versions  
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh  
Decoupling capacitors mounted on substrate  
All inputs and outputs are LVTTL compatible  
Serial Presence Detect with E2PROM  
Two bank 64M × 64 and 64M × 72  
organization  
Optimized for byte-write non-parity and ECC  
applications  
JEDEC standard Synchronous DRAMs  
(SDRAM)  
Uses Infineon 256 Mbit SDRAM components  
in 32M × 8 organization and TSOPII-54  
packages  
Programmed Latencies:  
•
•
Fully PC board layout compatible to INTEL’s  
Rev. 1.0 module specification  
Product Speed  
CL tRCD  
tRP  
2
-7  
PC133  
2
3
2
2
3
2
Gold contact pad, card size:  
133.35 mm × 31.75 mm × 4.00 mm  
(JEDEC MO-161-BA)  
-7.5  
-8  
PC133  
PC100  
3
2
•
SDRAM Performance:  
-7  
-7.5  
-8  
Unit  
PC133  
133  
PC133  
133  
PC100  
100  
6
fCK  
tAC  
Clock Frequency (max.)  
Clock Access time  
MHz  
ns  
5.4  
5.4  
Description  
The HYS 64V64220GU and HYS 72V64220GU are industry standard 168-pin 8-byte Dual in-line  
Memory Modules (DIMMs) which are organized as 64M × 64 and 64M × 72 in two banks high speed  
memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC  
applications. The DIMMs use “-7” speed sorted 256 Mbit Synchronous DRAMs (SDRAMs) to meet  
the PC133-222 requirements, “-7.5” for PC133-333 and “-8” components for PC100-222  
applications. Decoupling capacitors are mounted on the PC board. The PC board design is  
according to INTEL’s module specification. The DIMMs have a serial presence detect, implemented  
with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM  
manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs  
provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“  
(31.75 mm) height.  
INFINEON Technologies  
1
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Ordering Information  
Type  
Code  
Package  
Descriptions  
Module  
Height  
HYS 64V64220GU-7-D  
PC133-222-520 L-DIM-168-30 PC133 64M × 64 2 bank 1.25“  
SDRAM module  
HYS 72V64220GU-7-D  
PC133-222-520 L-DIM-168-30 PC133 64M × 72 2 bank 1.25“  
SDRAM module  
HYS 64V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M × 64 2 bank 1.25“  
HYS 64V64220GU-7.5-D SDRAM module  
HYS 72V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M × 72 2 bank 1.25“  
HYS 72V64220GU-7.5-D  
SDRAM module  
HYS 64V64220GU-8-C2  
PC100-222-620 L-DIM-168-30 PC100 64M × 64 2 bank 1.25“  
SDRAM module  
HYS 72V64220GU-8-C2  
PC100-222-620 L-DIM-168-30 PC100 64M × 72 2 bank 1.25“  
SDRAM module  
Note: All part numbers end with a place code, designating the die revision. Consult factory for  
current revision. Example: HYS 64V64220GU-8-C2, indicating Rev.C2 dies are used for  
SDRAM components.  
ames in paranthese are for the x72 ECC versions; example: Pin 106  
= (CB5)  
Pin Definitions and Functions  
A0 - A12  
Address Inputs  
Bank Selects  
CLK0 - CLK3  
Clock Input  
BA0, BA1  
DQMB0 - DQMB7 Data Mask  
DQ0 - DQ63 Data Input/Output  
CS0 - CS3  
Chip Select  
CB0 - CB7  
RAS  
Check Bits (x72 organization only) VDD  
Power (+ 3.3 V)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
VSS  
CAS  
SCL  
SDA  
Clock for Presence Detect  
WE  
Serial Data Out for  
Presence Detect  
CKE0, CKE1 Clock Enable  
N.C./DU  
No Connection  
Address Format  
Part Number  
Rows Columns Bank Select Refresh Period Interval  
64M × 64/72 HYS64/72V64220GU 13  
10  
2
8k  
64 ms 7.8 µs  
INFINEON Technologies  
2
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
VSS  
85  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
VSS  
2
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
86  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
3
CS2  
87  
4
DQMB2  
DQMB3  
DU  
88  
DQMB6  
DQMB7  
N.C.  
5
89  
6
90  
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
VDD  
91  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VDD  
8
N.C.  
92  
N.C.  
9
N.C.  
93  
N.C.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
N.C. (CB2)  
N.C. (CB3)  
VSS  
94  
CB6  
95  
CB7  
96  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
DQ16  
DQ17  
DQ18  
DQ19  
VDD  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
DQ48  
DQ49  
DQ50  
DQ51  
VDD  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
N.C.  
DQ52  
N.C.  
DQ14  
DQ15  
N.C. (CB0)  
N.C. (CB1)  
VSS  
DQ46  
DQ47  
N.C. (CB4)  
N.C. (CB5)  
VSS  
DU  
DU  
CKE1  
VSS  
N.C.  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
RAS  
VSS  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
A9  
CLK3  
N.C.  
A10  
BA0  
BA1  
WP  
A11  
SA0  
VDD  
SDA  
VDD  
SA1  
VDD  
SCL  
CLK1  
A12  
SA2  
CLK0  
VDD  
VDD  
Note: Pin names in parenthses are for the x72 ECC versions  
INFINEON Technologies  
3
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
CS1  
CS0  
CS  
DQM  
DQ0-DQ7  
D0  
CS  
DQM  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D12  
DQMB0  
DQ(7:0)  
DQMB4  
DQ0-DQ7  
DQ(39:32)  
DQ0-DQ7  
D8  
D4  
CS  
DQM  
CS  
DQM  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D13  
DQMB1  
DQMB5  
DQ(15:8)  
DQ0-DQ7  
DQ0-DQ7  
DQ(47:40)  
DQ0-DQ7  
D1  
D9  
D5  
CS  
CS  
DQM  
DQM  
DQ0-DQ7  
D17  
CB(7:0)  
DQ0-DQ7  
D16  
CS3  
CS2  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D10  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D14  
DQMB2  
DQMB6  
DQ(23:16)  
DQ0-DQ7  
DQ(55:48)  
DQ0-DQ7  
D2  
D6  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D11  
CS  
DQM  
CS  
DQM  
DQ0-DQ7  
D15  
DQMB3  
DQMB7  
DQ(31:24)  
DQ0-DQ7  
DQ(63:56)  
DQ0-DQ7  
D3  
D7  
A0-A12, BA0, BA1  
D0-D15, (D16, D17)  
D0-D15, (D16, D17)  
D0-D15, (D16, D17)  
D0-D15, (D16, D17)  
D0-D7, (D16)  
E2PROM (256 Word x 8 Bit)  
SA0  
SA0  
SA1  
SA2  
SCL  
VDD  
SA1  
SA2  
SCL  
SDA  
WP  
C
VSS  
Ω
47 k  
RAS, CAS, WE  
CKE0  
Clock Wiring  
32 M x 64  
VDD  
32 M x 72  
Ω
10 k  
CLK0 4 SDRAM + 3.3 pF 5 SDRAM  
CLK1 4 SDRAM + 3.3 pF 5 SDRAM  
CLK2 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF  
CKE1  
D9-D15, (D17)  
CLK3 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF  
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10  
Ω
except otherwise noted.  
BL012  
Block Diagram: 64M x 64/72 Two Bank SDRAM DIMM Modules  
INFINEON Technologies  
4
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
– 1.0  
– 1.0  
-55  
–
max.  
4.6  
Input / Output voltage relative to VSS  
Power supply voltage on VDD  
VIN, VOUT  
VDD  
V
4.6  
+150  
1
V
Storage temperature range  
TSTG  
PD  
oC  
W
mA  
Power dissipation per SDRAM component  
Data out current (short circuit)  
IOS  
–
50  
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
V
DD + 0.3  
V
Input Low Voltage  
– 0.5  
2.4  
0.8  
–
V
Output High Voltage (IOUT = – 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
–
0.4  
40  
V
Input Leakage Current, any input  
– 40  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
– 40  
40  
µA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
max.  
64M × 64  
64M × 72  
Input Capacitance  
CI1  
105  
144  
pF  
(A0 to A11, BA0, BA1, RAS, CAS, WE)  
Input Capacitance (CS0 - CS3)  
CI2  
32  
40  
65  
20  
17  
8
40  
43  
72  
25  
17  
8
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance (CLK0 - CLK3)  
Input Capacitance (CKE0, CKE1)  
Input Capacitance (DQMB0 - DQMB7)  
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0-2)  
Input/Output Capacitance  
CICL  
CI3  
CI4  
CIO  
CSC  
CSD  
8
8
INFINEON Technologies  
5
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Operating Currents per SDRAM Component  
TA = 0 to 70 oC, VDD = 3.3 V ± 0.3 V  
Parameter  
Test  
Condition  
Symbol -7/ -7.5 -8  
max.  
170  
Unit Note  
1, 2  
Operating current  
–
ICC1  
230  
mA  
tRC = tRC(MIN.), tCK = tCK(MIN.)  
Outputs open, Burst Length = 4, CL = 3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
1, 2  
Precharge stand-by current  
in Power Down Mode  
t
CK = min.  
CK = min.  
ICC2P  
2
2
mA  
CS = VIH(MIN.), CKE ≤ VIL(MAX.)  
1, 2  
Precharge Stand-by Current  
in Non-Power Down Mode  
t
ICC2N  
40  
30  
mA  
CS = VIH (MIN.), CKE ≥ VIH(MIN.)  
1, 2  
No operating current  
CKE ≥ VIH(MIN.) ICC3N  
CKE ≤ VIL(MAX.) ICC3P  
50  
10  
45  
10  
mA  
1, 2  
mA  
tCK = min., CS = VIH(MIN.),  
active state (max. 4 banks)  
1,2,3  
Burst operating current  
–
–
ICC4  
ICC5  
ICC6  
150  
240  
3
100  
220  
3
mA  
tCK = min.,  
Read command cycling  
1, 2  
Auto refresh current  
mA  
tCK = min.,  
Auto Refresh command cycling  
1
Self refresh current  
mA  
Self Refresh Mode, CKE = 0.2 V  
Notes  
1. All values are shown per one SDRAM component.  
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation  
frequency for -7 & -7.5 and at 100 MHz for -8 modules.  
Input signals are changed once during tCK, excepts for ICC6 and for stand-by currents when  
tCK = infinity.  
3. These parameters are measured with continuous data stream during read access and all DQ  
toggling. CL = 3 and BL = 4 are assumed and the data out current is excluded.  
INFINEON Technologies  
6
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
1), 2)  
AC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Symbol  
Parameter  
Limit Values  
-7.5  
Unit Note  
-7  
-8  
PC133-222 PC133-333 PC100-222  
min. max min. max. min. max.  
Clock  
Clock Cycle Time  
tCK  
fCK  
tAC  
–
ns  
ns  
CAS Latency = 3  
CAS Latency = 2  
System Frequency  
7.5  
7.5  
–
–
7.5  
10  
–
–
10  
10  
–
–
–
CAS Latency = 3  
CAS Latency = 2  
–
–
133  
133  
–
–
133  
100  
–
–
100 MHz  
100 MHz  
3), 4)  
Clock Access Time  
CAS Latency = 3  
CAS Latency = 2  
–
–
5.4  
5.4  
–
–
5.4  
6
–
–
6
6
ns  
ns  
4)  
4)  
Clock High Pulse Width  
Clock Low Pulse Width  
tCH  
tCL  
2.5  
2.5  
–
–
2.5  
2.5  
–
–
3
3
–
–
ns  
ns  
Setup and Hold Times  
Input Setup Time  
5)  
5)  
6)  
7)  
tCS  
tCH  
tSB  
1.5  
0.8  
–
–
–
1
–
–
–
1.5  
0.8  
–
–
–
1
–
–
–
2
1
–
1
2
1
–
–
1
–
–
–
ns  
Input Hold Time  
ns  
Power Down Mode Entry Time  
CLK  
CLK  
CLK  
ns  
Power Down Mode Exit Setup Time tPDE  
1
1
Mode Register Setup Time  
Transition Time (rise and fall)  
tRSC  
tT  
2
2
1
1
–
Common Parameters  
RAS to CAS Delay  
Precharge Time  
tRCD  
tRP  
tRAS  
tRC  
15  
15  
42  
60  
14  
1
–
–
–
–
–
–
20  
20  
45  
67.5  
15  
1
–
–
20  
20  
–
–
ns  
ns  
–
–
–
–
–
–
Active Command Period  
Cycle Time  
100k 50  
100k ns  
–
–
–
70  
16  
1
–
–
–
ns  
Bank to Bank Delay Time  
tRRD  
ns  
CAS to CAS Delay Time (same bank) tCCD  
CLK  
INFINEON Technologies  
7
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
AC Characteristics (cont’d) 1), 2)  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Symbol  
Parameter  
Limit Values  
-7.5  
Unit Note  
-7  
-8  
PC133-222 PC133-333 PC100-222  
min. max min. max. min. max.  
Refresh Cycle  
6)  
Refresh Period (8192 cycles)  
Self Refresh Exit Time  
tREF  
64  
–
–
64  
–
64  
ms  
8)  
tSREX  
–
1
1
–
1
–
CLK  
Read Cycle  
2)  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
7
2
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns  
Data Out to Low Impedance  
Data Out to High Impedance  
DQM Data Out Disable Latency  
ns  
–
9)  
tHZ  
ns  
tDQZ  
CLK  
–
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
2
0
–
–
CLK  
CLK  
–
–
DQM Write Mask Latency  
tDQW  
Notes  
4. All AC characteristics are shown on SDRAM component level.  
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must  
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation  
can begin.  
5. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
6. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter.  
7. Rated at 1.4 V  
8. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.  
9. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)  
commands must be given to “wake-up” the device.  
10.Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal  
is assumed latched on the next cycle.  
INFINEON Technologies  
8
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
11.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
12.This is referenced to the time at which the output achieves the open circuit condition, not to  
output voltage levels.  
tCH  
2.4 V  
0.4 V  
1.4 V  
CLOCK  
tT  
tCL  
tIH  
tIS  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
OUTPUT  
1.4 V  
50 pF  
tHZ  
Measurement conditions for  
AC and tOH  
t
IO.vsd  
Serial Presence Detect  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information  
about the module configuration, speed, etc. is written into the E2PROM device during module  
production using a serial presence detect protocol (I2C synchronous 2-wire bus).  
INFINEON Technologies  
9
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for 64M x 64 (512 MByte non-ECC) Modules HYS64V64220GU  
Byte Description  
#
SPD Entry Value  
Hex  
64M x 64  
-7.5  
80  
-7  
-8  
0
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
256  
SDRAM  
13  
1
2
08  
04  
3
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
0D  
4
10  
0A  
5
2
02  
6
64  
40  
7
8
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL = 3  
Access Time from Clock at CL = 3  
DIMM Config  
0
00  
01  
LVTTL  
7.5 / 10 ns  
5.4 / 6 ns  
non-ECC  
9
75  
54  
75  
A0  
60  
10  
11  
12  
54  
00  
Refresh Rate/Type  
Self-Refresh,  
82  
7.8 µs  
13  
14  
15  
SDRAM Width, Primary  
x8  
na  
08  
00  
01  
Error Checking SDRAM Data Width  
Minimum Clock Delay for Back-to-  
Back Random Column Address  
Burst Length Supported  
t
CCD = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
1, 2, 4 & 8  
4
0F  
04  
06  
01  
01  
00  
0E  
A0  
60  
FF  
FF  
Number of SDRAM Banks  
Supported CAS Latencies  
CS Latencies  
CL = 2 & 3  
CS latency = 0  
Write latency = 0  
unbuffered  
DD tol +/– 10%  
7.5 / 10.0 ns  
5.4 / 6.0 ns  
WE Latencies  
SDRAM DIMM Module Attributes  
SDRAM Device Attributes: General  
SDRAM Cycle Time at CL = 2  
Access Time from Clock for CL = 2  
Minimum Clock Cycle Time at CL = 1  
V
75  
54  
00  
00  
A0  
60  
FF  
FF  
not supported  
not supported  
Maximum Data Access Time from  
Clock at CL = 1  
27  
28  
Minimum Row Precharge Time  
Minimum Row Active to Row Active  
Delay tRRD  
15 / 20 ns  
0F  
0E  
14  
0F  
14  
10  
14 / 15 / 16 ns  
29  
30  
31  
32  
33  
Minimum RAS to CAS Delay tRCD  
Minimum RAS Pulse Width tRAS  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
15 / 20 ns  
42 / 45 / 50 ns  
256 MByte  
0F  
2A  
14  
2D  
40  
15  
08  
14  
32  
1.5 / 2.0 ns  
0.8 / 1.0 ns  
15  
08  
20  
10  
INFINEON Technologies  
10  
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for 64M x 64 (512 MByte non-ECC) Modules HYS64V64220GU  
Byte Description  
#
SPD Entry Value  
Hex  
64M x 64  
-7  
15  
08  
FF  
12  
F4  
-7.5  
-8  
20  
10  
FF  
12  
9A  
34  
35  
SDRAM Data Input Hold Time  
SDRAM Data Input Setup Time  
1.5 / 2.0 ns  
15  
0.8 / 1.0 ns  
08  
FF  
36-61 Superset Information  
–
62  
63  
64  
SPD Revision  
Revision 1.2  
12  
37  
Checksum for Bytes 0 - 62  
Manufacturers JEDEC ID Code  
–
–
C1  
65-71 Manufacturer  
INFINEO(N)  
72  
Module Assembly Locaction  
73-90 Module Part Number  
91-92 Module Revision Code  
93-94 Module Manufacturing Code  
95-98 Module Serial Number  
99-  
Superset Information  
125  
126  
127  
Frequency Specification  
100 MHz Support Details  
64  
FF  
FF  
64  
FF  
FF  
64  
FF  
FF  
–
–
128+ Unused Storage Locations  
INFINEON Technologies  
11  
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for 64M x 72 (512 MByte ECC) Modules HYS72V64220GU  
Byte# Description  
SPD Entry Value  
Hex  
64M x 72  
-7.5  
80  
-7  
-8  
0
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
256  
SDRAM  
13  
1
2
08  
04  
3
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
0D  
4
10  
0A  
5
2
02  
6
72  
48  
7
8
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL = 3  
Access Time from Clock at CL = 3  
DIMM Config  
0
00  
01  
LVTTL  
7.5 / 10 ns  
5.4 / 6 ns  
ECC  
9
75  
54  
75  
A0  
60  
10  
11  
12  
54  
02  
Refresh Rate/Type  
Self-Refresh,  
82  
7.8 µs  
13  
14  
15  
SDRAM Width, Primary  
x8  
x8  
08  
08  
01  
Error Checking SDRAM Data Width  
Minimum Clock Delay for Back-to-  
Back Random Column Address  
Burst Length Supported  
t
CCD = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
1, 2, 4 & 8  
4
0F  
04  
06  
01  
01  
00  
0E  
A0  
60  
FF  
FF  
Number of SDRAM Banks  
Supported CAS Latencies  
CS Latencies  
CL = 2 & 3  
CS latency = 0  
Write latency = 0  
unbuffered  
VDD tol +/– 10%  
7.5 / 10.0 ns  
WE Latencies  
SDRAM DIMM Module Attributes  
SDRAM Device Attributes: General  
SDRAM Cycle Time at CL = 2  
Access Time from Clock for CL = 2  
Minimum Clock Cycle Time at CL = 1  
75  
54  
00  
00  
A0  
60  
FF  
FF  
5.4 / 6.0 ns  
not supported  
not supported  
Maximum Data Access Time from  
Clock at CL = 1  
27  
28  
Minimum Row Precharge Time  
Minimum Row Active to Row Active  
Delay tRRD  
15 / 20 ns  
0F  
0E  
14  
0F  
14  
10  
14 / 15 / 16 ns  
29  
30  
31  
32  
33  
Minimum RAS to CAS Delay tRCD  
Minimum RAS Pulse Width tRAS  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
15 / 20 ns  
42 / 45 / 50 ns  
256 MByte  
0F  
2A  
14  
2D  
40  
15  
08  
14  
32  
1.5 / 2.0 ns  
0.8 / 1.0 ns  
15  
08  
20  
10  
INFINEON Technologies  
12  
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
SPD-Table for 64M x 72 (512 MByte ECC) Modules HYS72V64220GU  
Byte# Description  
SPD Entry Value  
Hex  
64M x 72  
-7  
15  
08  
FF  
12  
06  
-7.5  
-8  
20  
10  
FF  
12  
AC  
34  
35  
SDRAM Data Input Hold Time  
SDRAM Data Input Setup Time  
1.5 / 2.0 ns  
15  
0.8 / 1.0 ns  
08  
FF  
36-61 Superset Information  
–
62  
63  
64  
SPD Revision  
Revision 1.2  
12  
49  
Checksum for Bytes 0 - 62  
Manufacturers JEDEC ID Code  
–
–
C1  
65-71 Manufacturer  
INFINEO(N)  
72  
Module Assembly Locaction  
73-90 Module Part Number  
91-92 Module Revision Code  
93-94 Module Manufacturing Code  
95-98 Module Serial Number  
99-125 Superset Information  
126  
127  
Frequency Specification  
100 MHz Support Details  
Unused Storage Locations  
64  
FF  
FF  
64  
FF  
FF  
64  
FF  
FF  
–
–
128+  
INFINEON Technologies  
13  
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Package Outlines  
L-DIM-168-30 (JEDEC MO-161-BA)  
SDRAM DIMM Module Package  
HYS 64/72V64220GU  
133.35+- 0.15  
127.35  
4 max.  
*)  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27 +- 0.1  
3
1.27  
42.18  
91 x 1.27 = 115.57  
124 125  
2
85 94  
95  
168  
*)  
3 min.  
3
Detail of Contacts  
*) on ECC modules only  
1
1.27  
L-DIM-168-30  
Note: All tolerances according to JEDEC standard  
INFINEON Technologies  
14  
9.01  
HYS 64/72V64220GU  
SDRAM-Modules  
Change List:  
14.1.1999  
Input capacitances adjusted  
18.4.1999  
-8A speed sort added  
Infineon logo added  
SPD codes updated according to new 256M speedsorts  
Some ICC current values changed due to new inputs  
PC133 merged into this datasheet  
12.5.99  
3.8.99  
23.8.99  
6.9.99  
Byte 126 changed to 64h for PC133 modules  
Template from R&L  
20.10.99  
2.12.99  
20.1.2000  
10.3.2000  
CL=2 max. frequency changed to 83 Mhz for -7.5 modules  
Some timing parameters adjusted according to INTELs PC133 specification  
Capacitance values for x72 adjusted (new measurements)  
Implemented differences between 256Mbit S20 and S17 PC133 modules  
256Mbit S20 based PC133 modules are backward compatible to PC100 3-2-2  
256Mbit S17 based modules are backwards compatible to PC100-2-2-2  
leading to changes in SPD code of bytes 23, 63 (checksum) and 126  
TPCR issued  
10.5.2000  
5.03.2001  
Reference to JEDEC MO-161-BA added  
-8A and -8B speed sorts removed  
PC133 timing parameters only for 256M S17 and later versions  
References to 256M S20 removed  
ICC currents according to 256M S17 datasheet  
24.07.2001  
06.09.2001  
256M S14 based modules addded  
-7 speed sort added for 256M S14 modules  
SCR : Absolute Maximum Ratings table added  
INFINEON Technologies  
15  
9.01  
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