Internet Data Sheet
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
3.2
Current Specification and Conditions
TABLE 10
IDD Conditions
Parameter
Symbol
Operating Current 0
IDD0
One bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
One bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
All banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
Address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
One bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
One bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
One bank active; Burst Length = 2; reads; continuous burst;
Address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
One bank active; Burst Length = 2; writes; continuous burst;
Address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
t
RC = tRFCMIN, burst refresh
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
Four bank interleaving with Burst Length = 4; see component data sheet.
Rev. 1.21, 2007-01
03292006-F1IB-1I3E
16
