CYS25G0101DX
the frequency of the clock that drives the REFCLK signal of the
remote transmitter to ensure a lock to the incoming data stream.
Serializer
The parallel data from the phase align buffer is passed to the
Serializer that converts the parallel data to serial data. It uses the
bit rate clock generated by the Transmit PLL clock multiplier.
TXD[15] is the most significant bit of the output word and is trans-
mitted first on the serial interface.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When an
LFI indication is detected, external logic toggles selection of the
input device. When such a port switch takes place, it is
necessary for the PLL to reacquire lock to the new serial stream.
Serial Output Driver
External Filter
The Serial Interface Output Driver makes use of high perfor-
mance differential Current Mode Logic (CML) to provide a source
matched driver for the transmission lines. This driver receives its
data from the Transmit Shifters or the receive loopback data. The
outputs have signal swings equivalent to that of standard
LVPECL drivers and are capable of driving AC coupled optical
modules or transmission lines.
The CDR circuit uses external capacitors for the PLL filter. A 0.1
F capacitor needs to be connected between RXCN1 and
µ
RXCP1. Similarly a 0.1 F capacitor needs to be connected
µ
between RXCN2 and RXCP2. The recommended packages and
dielectric material for these capacitors are 0805 X7R or 0603
X7R.
Deserializer
CYS25G0101DX Receive Data Path
The CDR circuit extracts bits from the serial data stream and
clocks these bits into the Deserializer at the bit clock rate. The
Deserializer converts serial data into parallel data. RXD[15] is the
most significant bit of the output word and is received first on the
serial interface.
Serial Line Receivers
A differential line receiver, IN , is available for accepting the input
serial data stream. The serial line receiver inputs accommodate
high wire interconnect and filtering losses or transmission line
attenuation (VSE > 25 mV, or 50 mV peak-to-peak differential). It
can be AC coupled to +3.3V or +5V powered fiber optic interface
modules. The common mode tolerance of these line receivers
accommodates a wide range of signal termination voltages.
Loopback Timing Modes
CYS25G0101DX supports various loopback modes, as
described in the following sections.
Facility Loopback (Line Loopback with Retiming)
Lock to Data Control
When the LINELOOP signal is set HIGH, the Facility Loopback
mode is activated and the high speed serial receive data (IN ) is
presented to the high speed transmit output (OUT ) after
retiming. In Facility Loopback mode, the high speed receive data
(IN ) is also converted to parallel data and presented to the low
speed receive data output pins (RXD[15:0]). The receive
recovered clock is also divided down and presented to the
low-speed clock output (RXCLK).
Line Receiver routed to the clock and data recovery PLL is
monitored for:
I
status of signal detect (SD) pin
status of LOCKREF pin.
I
This status is presented on the Line Fault Indicator (LFI) output,
that changes asynchronously in the cases in which SD or
LOCKREF go from HIGH to LOW. Otherwise, it changes
synchronously to the REFCLK.
Equipment Loopback (Diagnostic Loopback with Retiming)
Clock Data Recovery
When the DIAGLOOP signal is set HIGH, transmit data is looped
back to the RX PLL, replacing IN . Data is looped back from the
parallel TX inputs to the parallel RX outputs. The data is looped
back at the internal serial interface and goes through transmit
shifter and the receive CDR. SD is ignored in this mode.
The extraction of a bit rate clock and recovery of data bits from
received serial stream is performed by a Clock Data Recovery
(CDR) block. The clock extraction function is performed by high
performance embedded phase-locked loop (PLL) that tracks the
frequency of the incoming bit stream and aligns the phase of the
internal bit rate clock to the transitions in the selected serial data
stream.
Line Loopback Mode (Non-retimed Data)
When the LOOPA signal is set HIGH, the RX serial data is
directly buffered out to the transmit serial data. The data at the
serial output is not retimed.
CDR accepts a character rate (bit rate * 16) reference clock on
the REFCLK input. This REFCLK input is used to ensure that the
VCO (within the CDR) is operating at the correct frequency
(rather than some harmonic of the bit rate), to improve PLL
acquisition time and to limit unlocked frequency excursions of the
CDR VCO when no data is present at the serial inputs.
Loop Timing Mode
When the LOOPTIME signal is set HIGH, the TX PLL is
bypassed and the receive bit rate clock is used for the transmit
side shifter.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the frequency of the recovered
data stream is outside the limits set by the range controls, the
CDR PLL tracks REFCLK instead of the data stream. When the
frequency of the selected data stream returns to a valid
frequency, the CDR PLL is allowed to track the received data
stream. The frequency of REFCLK must be within 100 ppm of
Reset Modes
ALL logic circuits in the device are reset using RESET and
FIFO_RST signals. When RESET is set LOW, all logic circuits
except FIFO are internally reset. When FIFO_RST is set LOW,
the FIFO logic is reset.
Document Number: 38-02009 Rev. *K
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