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HYS64V2100GCU-10

型号：

HYS64V2100GCU-10

描述：

3.3V 2M ×64位的SDRAM模块3.3V 2米x 72位的SDRAM模块[ 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module ]

品牌：

INFINEON[ Infineon ]

页数：

12 页

PDF大小：

78 K

下载PDF手册
3.3V 2M x 64-Bit SDRAM Module  
3.3V 2M x 72-Bit SDRAM Module  
HYS64V2100G(C)U-10  
HYS72V2100G(C)U-10  
168 pin unbuffered DIMM Modules  
• 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module  
for PC main memory applications  
• 1 bank 2M x 64, 2M x 72 organisation  
• Optimized for byte-write non-parity or ECC applications  
• Fully PC66 layout compatible  
• JEDEC standard Synchronous DRAMs (SDRAM)  
• Performance:  
-10  
fCK  
tAC  
Max. Clock frequency  
66 MHz @ CL=2  
100 MHz @ CL=3  
Max. access time from clock  
9 ns @ CL=2  
8 ns @ CL=3  
• Single +3.3V(± 0.3V ) power supply  
• Programmable CAS Latency, Burst Length and Wrap Sequence  
(Sequential & Interleave)  
• Auto Refresh (CBR) and Self Refresh  
• Decoupling capacitors mounted on substrate  
• All inputs, outputs are LVTTL compatible  
2
• Serial Presence Detect with E PROM  
• Utilizes eight / nine 2M x 8 SDRAMs in TSOPII-44 packages  
• 4096 refresh cycles every 64 ms  
• Gold contact pad  
• Card Size: 133,35mm x 29,21mm x 3,00mm for HYS64/72V2100GU  
• HYS64/72V2100GCU in chip-on-board technique  
• Card Size : 133,35mm x 25,40mm x 3,00mm for HYS64/72V2100GCU  
•
Semiconductor Group  
1
12.97  
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
The HYS64(72)V21)00G(C)U-10 are industry standard 168-pin 8-byte Dual in-line Memory  
Modules (DIMMs) which are organised as 2M x 64 and 2M x 72 high speed memory arrays  
designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs  
use eight 2M x 8 SDRAMs for the 2M x 64 organisation and an additional SDRAM for the 2M x 72  
organisation. Decoupling capacitors are mounted on the PC board.  
2
2
The DIMMs have a serial presence detect, implemented with a serial E PROM using the two pin I C  
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are  
available to the end user.  
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm  
long footprint.  
Ordering Information  
Type  
Ordering Code  
Package  
Descriptions  
HYS 64V2100GU-10  
HYS 72V2100GU-10  
HYS 64V2100GCU-10  
HYS 72V2100GCU-10  
L-DIM-168-27  
L-DIM-168-27  
L-DIM-168-C1  
L-DIM-168-C1  
PC66 2M x 64 SDRAM module  
PC66 2M x 72 SDRAM module  
PC66 2M x 64 SDRAM COB module  
PC66 2M x 72 SDRAM COB module  
Pin Names  
A0-A10  
Address Inputs( RA0 ~ RA10 / CA0 ~ CA8) CLK0, CLK1 Clock Input  
A11 (BS)  
Bank Select  
DQMB0 -  
DQMB7  
Data Mask  
DQ0 - DQ63 Data Input/Output  
CS0 - CS3  
Vcc  
Chip Select  
CB0-CB7  
RAS  
Check Bits (x72 organisation only)  
Power (+3.3 Volt)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read / Write Input  
Vss  
CAS  
SCL  
Clock for Presence Detect  
WE  
SDA  
Serial Data Out for Presence  
Detect  
CKE0  
Clock Enable  
N.C.  
No Connection  
Address Format:  
Part Number  
Rows  
11  
Columns Bank Select  
Refresh  
4k  
Period  
64 ms  
64 ms  
Interval  
15,6 µs  
15,6 µs  
2M x 64 HYS64V2100G(C)U  
2M x 72 HYS72V2100G(C)U  
9
9
1
11  
1
4k  
Semiconductor Group  
2
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
Pin Configuration  
PIN #  
Symbol  
PIN #  
Symbol  
PIN #  
Symbol  
PIN #  
Symbol  
1
VSS  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VCC  
DQ14  
DQ15  
NC (CB0)  
NC (CB1)  
VSS  
NC  
43  
VSS  
85  
VSS  
127  
VSS  
2
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DU  
86  
DQ32  
DQ33  
DQ34  
DQ35  
VCC  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
CKE0  
NC  
3
CS2  
87  
4
DQMB2  
DQMB3  
DU  
88  
DQMB6  
DQMB7  
NC  
5
89  
6
90  
7
VCC  
91  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VCC  
NC  
8
NC  
92  
9
NC  
93  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
NC (CB2)  
NC (CB3)  
VSS  
94  
CB6  
95  
CB7  
96  
VSS  
DQ16  
DQ17  
DQ18  
DQ19  
VCC  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VCC  
DQ48  
DQ49  
DQ50  
DQ51  
VCC  
DQ52  
NC  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ20  
NC  
DQ46  
DQ47  
NC (CB4)  
NC (CB5)  
VSS  
DU  
DU  
NC  
NC  
VSS  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
NC  
NC  
NC  
VCC  
WE  
VCC  
DQ24  
DQ25  
DQ26  
DQ27  
VCC  
CAS  
DQ56  
DQ57  
DQ58  
DQ59  
VCC  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
DQMB0  
DQMB1  
CS0  
DQMB4  
DQMB5  
NC  
DU  
RAS  
VSS  
A0  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
VSS  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
NC  
A9  
CLK3  
NC  
A10  
A11=BS  
NC  
NC  
NC  
SA0  
VCC  
VCC  
CLK0  
SDA  
VCC  
SA1  
SCL  
CLK1  
NC  
SA2  
VCC  
VCC  
Note : Pinnames in brackets are for the x72 ECC versions  
Semiconductor Group  
3
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
WE  
CS0  
CS WE  
DQM  
CS WE  
DQMB0  
DQ0-DQ7  
DQMB4  
DQM  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
D4  
D0  
CS WE  
CS WE  
DQM  
DQ0-DQ7  
DQM  
DQMB1  
DQMB5  
DQ0-DQ7  
DQ8-DQ15  
DQ40-DQ47  
D1  
CS WE  
D5  
DQM  
CB0-CB7  
DQ0-DQ7  
D8  
CS2  
CS WE  
CS WE  
DQMB2  
DQM  
DQM  
DQMB6  
DQ0-DQ7  
DQ0-DQ7  
DQ48-DQ55  
DQ16-DQ23  
D6  
CS WE  
D2  
CS WE  
DQMB7  
DQM  
DQM  
DQMB3  
DQ56-DQ63  
DQ0-DQ7  
DQ0-DQ7  
DQ24-DQ31  
D3  
D0 - D7,(D8)  
D0 - D7,(D8)  
D0 - D7,(D8)  
D7  
E2PROM (256wordx8bit)  
A0-A10,BS  
VCC  
VSS  
SA0  
SA1  
SA2  
SA0  
SA1  
SA2  
C1-C8,(C9)  
SCL  
SDA  
RAS  
CAS  
CKE0  
D0 - D7,(D8)  
D0 - D7,(D8)  
2 SDRAMs  
2 (3) SDRAMs  
CLK0  
CLK1  
D0 - D7,(D8)  
2 SDRAMs  
2 SDRAMs  
Note: D8 is only used in the x72 ECC version  
CLK2,CLK3  
10 pF  
Block Diagram for 2M x 64/72 SDRAM DIMM modules  
Semiconductor Group  
4
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
max.  
Vcc+0.3  
0.8  
Input high voltage  
VIH  
VIL  
2.0  
– 0.5  
2.4  
V
Input low voltage  
V
Output high voltage (IOUT = – 2.0 mA)  
Output low voltage (IOUT = 2.0 mA)  
VOH  
VOL  
II(L)  
–
V
–
0.4  
V
Input leakage current, any input  
– 40  
40  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output leakage current  
IO(L)  
– 40  
40  
µA  
(DQ is disabled, 0 V < VOUT < VCC)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
max.  
(x72)  
(x64)  
45  
20  
22  
13  
12  
8
Input capacitance (A0 to A10, BS, RAS, CAS, WE)  
Input capacitance ( CS0 - CS3)  
CI1  
CI2  
CI3  
CI4  
CIO  
55  
25  
38  
13  
12  
8
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input capacitance (CLK0 - CLK3)  
Input capacitance (DQMB0 - DQMB7)  
Input / Output capacitance (DQ0-DQ63,CB0-CB7)  
Input Capacitance (SCL,SA0-2)  
C
C
sc  
sd  
Input/Output Capacitance  
10  
10  
Semiconductor Group  
5
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
o
Standby and Refresh Currents (T = 0 to 70 C, VCC = 3.3V ± 0.3V)  
a
Note  
Parameter  
Symbol  
Test Condition  
X64  
X72  
Burst length = 4, CL=3  
trc>=trc(min.),  
tck>=tck(min.), Io=0 mA  
2 bank interleave operation  
Operating Current  
Icc1  
800  
900 mA 1,2  
mA  
CKE<=VIL(max), tck>=tck(min.)  
CKE<=VIL(max), tck=infinite  
Precharged Standby  
Current in Power  
Down Mode  
Icc2P  
24  
16  
27  
18  
mA  
mA  
Icc2PS  
CKE>=VIH(min), tck>=tck (min.),  
input changed once in 3 cycles  
Precharged Standby  
Current in Non-  
power  
Icc2N  
160  
80  
180 mA CS=  
High  
CKE>=VIH(min), tck=infinite,  
no input change  
Icc2NS  
90  
mA  
Down Mode  
CKE<=VIL(max), tck>=tck(min.)  
CKE<=VIL(max), tck=infinite  
Active Standby  
Current in Power  
Down Mode  
Icc3P  
24  
16  
27  
18  
mA  
mA  
Icc3PS  
CKE>=VIH(min), tck>=tck (min.)  
input changed one time  
Active Standby  
Current in Non-  
power Down Mode  
Icc3N  
Icc3NS  
Icc4  
200  
120  
760  
225 mA CS=  
High  
CKE=>VIH(min),tck=infinite,  
no input change  
135 mA  
Burst Operating  
Current  
Burst length = full page,  
trc = infinite, CL = 3,  
tck>=tck (min.), Io = 0 mA  
2 banks activated  
855 mA 1,2  
mA  
1,2  
Auto (CBR) Refresh  
Current  
Icc5  
Icc6  
trc>=trc(min)  
720  
16  
810 mA  
mA  
Self Refresh Current  
CKE=<0,2V  
18  
mA 1,2  
Semiconductor Group  
6
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
AC Characteristics 3)4)  
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns  
Symbol  
Note  
Parameter  
Limit Values  
Unit  
-10  
min  
max  
Clock and Clock Enable  
Clock Cycle Time  
tCK  
fCK  
tAC  
CAS Latency = 3  
CAS Latency = 2  
CAS Latency = 1  
10  
15  
30  
ns  
ns  
ns  
System Frequency  
Clock Access Time  
CAS Latency = 3  
CAS Latency = 2  
CAS Latency = 1  
–
–
–
100  
66  
33  
MHz  
MHz  
MHz  
5
CAS Latency = 3  
CAS Latency = 2  
CAS Latency = 1  
–
–
–
8
9
27  
ns  
ns  
ns  
Clock High Pulse Width  
Clock Low Pulse Width  
CKE Setup Time  
tCH  
3.5  
3.5  
3
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCL  
6
6
6
8
tCKS  
tCKH  
–
CKE Hold Time  
1
–
CKE Setup Time (Power down mode) tCKSP  
3
–
CKE Setup Time (Self Refresh Exit)  
Transition time (rise and fall)  
tCKSR  
tT  
8
–
1
30  
Common Parameters  
Command Setup time  
Command Hold Time  
Address Setup Time  
Address Hold Time  
RAS to CAS delay  
Cycle Time  
6
6
6
6
tCS  
3
1
–
–
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCH  
tAS  
3
–
tAH  
1
–
tRCD  
tRC  
tRAS  
tRP  
30  
75  
45  
30  
–
120k  
Active Command Period  
Precharge Time  
120k  
–
Semiconductor Group  
7
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
Symbol  
Note  
Parameter  
Limit Values  
Unit  
-10  
min  
20  
max  
Bank to Bank Delay Time  
tRRD  
tCCD  
–
–
ns  
CAS to CAS delay time (same bank)  
1
CLK  
Refresh Cycle  
2Clk  
+tRC  
8
7
Self Refresh Exit Time  
tSREX  
tREF  
–
ns  
Refresh Period (4096 cycles)  
–
64  
ms  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
tHZ  
3
0
–
–
ns  
ns  
Data Out to Low Impedance Time  
9
Data Out to High Impedance Time  
CAS Latency = 3  
–
–
–
6
8
25  
ns  
ns  
ns  
CAS Latency = 2  
CAS Latency = 1  
DQM Data Out Disable Latency  
tDQZ  
2
–
CLK  
Write Cycle  
Data In Setup Time  
Data In Hold Time  
tDS  
3
1
2
5
–
–
–
–
–
ns  
tDH  
ns  
Data input to Precharge  
Data In to Active/refresh  
DQM Write Mask Latency  
tDPL  
tDAL  
tDQW  
CLK  
CLK  
CLK  
10  
0
Semiconductor Group  
8
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
Notes:  
1. The specified values are valid when addresses are changed no more than once during tck(min.)  
and when No Operation commands are registered on every rising clock edge during tRC(min).  
2. The specified values are valid when data inputs (DQs’) are stable during tRC(min.).  
3. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must  
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can  
begin.  
4. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover  
il  
ih  
point. The transition time is measured between V and V . All AC measurements assume t =1ns  
ih  
il  
T
with the AC output load circuit shown.  
tCH  
2.4 V  
0.4 V  
CLOCK  
tCL  
t
T
+ 1.4 V  
tSETUP tHOLD  
50 Ohm  
1.4V  
INPUT  
Z=50 Ohm  
I/O  
tAC  
tAC  
50 pF  
tLZ  
tOH  
1.4V  
OUTPUT  
fig.1  
tHZ  
5. If clock rising time is longer than 1ns, a time (t /2 -0.5) ns has to be added to this parameter.  
T
6. If t is longer than 1 ns, a time (t -1) ns has to be added to this parameter.  
T
T
7. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh  
commands must be given to “wake-up“the device.  
8. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
once the Self Refresh Exit command is registered.  
9. Referenced to the time which the output achieves the open circuit condition, not to output voltage  
levels.  
10.t  
is equivalent to t  
+ t  
.
RP  
DAL  
DPL  
Semiconductor Group  
9
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
2
A serial presence detect storage device - E PROM - is assembled onto the module. Information  
2
about the module configuration, speed, etc. is written into the E PROM device during module  
2
production using a serial presence detect protocol ( I C synchronous 2-wire bus)  
SPD-Table:  
Byte#  
Description  
Number of SPD bytes  
SPD Entry Value  
Hex  
x64  
80  
08  
04  
0B  
09  
x72  
80  
08  
04  
0B  
09  
0
1
2
3
4
128  
256  
Total bytes in Serial PD  
Memory Type  
SDRAM  
11  
Number of Row Addresses (without BS bits)  
Number of Column Addresses (for x 8  
SDRAM)  
9
5
6
7
8
9
Number of DIMM Banks  
Module Data Width  
1
64 / 72  
01  
40  
00  
01  
A0  
80  
00  
80  
01  
48  
00  
01  
A0  
80  
02  
80  
Module Data Width (contd’ )  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
0
LVTTL  
8.0 / 10.0 / 12.0 ns  
8.0 ns  
10 SDRAM Access time from Clock at CL=3  
11 Dimm Config (Error Det/Corr.)  
12 Refresh Rate/Type  
none / ECC  
Self-Refresh,  
15.6µs  
13 SDRAM width, Primary  
x8  
08  
00  
01  
08  
08  
01  
14 Error Checking SDRAM data width  
n/a / x8  
15 Minimum clock delay for back-to-back ran-  
dom column address  
tccd = 1 CLK  
16 Burst Length supported  
17 Number of SDRAM banks  
18 Supported CAS Latencies  
1, 2, 4, 8 & full page  
2
8F  
02  
07  
8F  
02  
07  
CAS latency = 1, 2  
& 3  
19 CS Latencies  
CS latency = 0  
01  
01  
00  
01  
01  
00  
20 WE Latencies  
Write latency = 0  
21 SDRAM DIMM module attributes  
non buffered/non  
reg.  
22 SDRAM Device Attributes :General  
23 SDRAM Cycle Time at CL = 2  
Vcc tol +/- 10%  
15.0 ns  
9.0 ns  
06  
F0  
90  
78  
6C  
1E  
06  
F0  
90  
78  
6C  
1E  
24 SDRAM Access time from Clock at CL = 2  
25 SDRAM Cycle Time at CL = 1  
30 ns  
26 SDRAM Access time from Clock at CL=1  
27 Minimum Row Precharge Time  
27 ns  
30 ns  
Semiconductor Group  
10  
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
SPD-Table (contd’ )  
Byte#  
Description  
SPD Entry Value  
Hex  
x64 x72  
28 Minimum Row Active to Row Active delay  
tRRD  
20 ns  
14  
14  
29 Minimum RAS to CAS delay tRCD  
30 Minimum RAS pulse width tRAS  
31 Module Bank Density (per bank)  
30 ns  
45 ns  
1E  
2D  
04  
FF  
1E  
2D  
04  
FF  
16 MByte  
32-61 Superset information (may be used in  
future)  
62 SPD Revision  
Revision 1  
01  
F3  
FF  
01  
05  
FF  
63 Checksum for bytes 0 - 62  
64- Manufacturess’ information (optional)  
127 (FFh if not used)  
128+ Unused storage locations  
FF  
FF  
L-DIM-168-27  
SDRAM DIMM Module package  
133,35  
127,35  
3,0  
84  
1
10 11  
40 41  
42,18  
66,68  
AC  
A
B
85  
94 95  
124 125  
168  
6,35  
6,35  
1,27  
1,0 + 0.5  
-
+
0,2 0,15  
-
2,0  
2,0  
Detail C  
Detail A  
Detail B  
DM168-27.WMF(EWK)  
Semiconductor Group  
11  
HYS64(72)V2100G(C)U-10  
2M x 64/72 SDRAM-Module  
L-DIM-168-C1  
SDRAM DIMM COB-Module package  
133,35  
127,35  
3,0  
84  
1
10 11  
40 41  
42,18  
66,68  
AC  
A
B
85  
94 95  
124 125  
168  
6,35  
6,35  
1,27  
1,0 + 0.5  
-
+
0,2 0,15  
-
2,0  
2,0  
Detail C  
Detail A  
Detail B  
DM168-C1.WMF  
Semiconductor Group  
12  
厂商 型号 描述 页数 下载

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