D E L I V E R A B L E S
P I N S D E S C R I P T I O N
♦
♦
♦
Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
Synthesis scripts
PIN
ACTIVE TYPE
DESCRIPTION
clk
-
input Global system clock
input Global reset input
input Interrupt request
input Non-Maskable Interrupt Request
input WAIT input
rst
Low
Low
Low
Low
Low
-
int
nmi
wait
busreq
input Bus Request
datai[7:0]
datao[7:0]
addr[15:0]
wr
input Memory bus input
output Data memory & UFR bus output
output Data memory address bus
output Write enable
-
-
♦
♦
♦
Low
Low
Low
Low
Low
Low
Low
Low
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
rd
output Read enable
busack
m1
output Bus Acknowledge
output Machine Cycle One
output Memory Request
output Input/Output Request
output Refresh
●
Delivery the IP Core updates, minor and
major versions changes
mreq
iorq
●
Delivery the documentation updates
rfsh
○ Phone & email support
halt
output Halt State
L I C E N S I N G
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
S Y M B O L
clk
rst
halt
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
datai(7:0)
datao(7:0)
Unlimited Designs, One Year licenses allow use
IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
addr(15:0)
wr
rd
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
m1
mreq
iorq
rfsh
busack
int
nmi
busrq
wait
● Single Design license for
○ VHDL, Verilog source code called HDL Source
○ Encrypted, or plain text EDIF called Netlist
● Unlimited Designs license for
○ HDL Source
B L O C K D I A G R A M
Control Unit - Performs the core synchroniza-
tion and data flow control. This module man-
ages execution of all instructions. The Control
Unit also manages execution of HALT state and
waking-up the processor from the HALT mode.
○ Netlist
● Upgrade from
Opcode Decoder - Performs an instruction
opcode decoding and the control functions for
all other blocks.
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
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are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
