CYP15G0101DXA-BBI,PDF,CYP15G0101DXA-BBI PDF资料,Datasheet,下载CYP15G0101DXA-BBI技术资料

PRELIMINARY

CYP15G0101DXA

Single Channel HOTLink II™ Transceiver

• Compatible with

—Fiber-optic modules

—Copper cables

Features

• 2^ndgeneration HOTLink^®technology

• Fibre Channel and Gigabit Ethernet compliant 8B/10B-

coded or 10-bit unencoded

—Circuit board traces

• ESCON, DVB-ASI Compliant

• JTAG boundary scan

• SMPTE-292M, SMPTE-259M Compliant

• 8-bit encoded data transport

• Built-In Self-Test (BIST) for at-speed link testing

• Link Quality Indicator

— Aggregate throughput of 2.4 GBits/second

• 10-bit unencoded data transport

— Aggregate throughput of 3 GBits/second

• Selectable parity check/generate

• Selectable input clocking options

• Selectable output clocking options

• MultiFrame™ receive Framer provides alignment to

— Bit and byte boundaries

—Analog signal detect

—Digital signal detect

—Frequency range detect

• Low Power (0.85W typical)

—Single +3.3V V_CCsupply

• 100-ball BGA

• 0.25µ BiCMOS technology

Functional Description

— Comma or Full K28.5 detect

— Single or Multi-byte Framer for byte alignment

The CYP15G0101DXA Single Channel HOTLink II™ Trans-

ceiver is a point-to-point communications building block allow-

ing the transfer of data over a high-speed serial link (optical

fiber, balanced, and unbalanced copper transmission lines) at

signaling speeds ranging from 200-to-1500 MBaud.

— Low-latency option

• Synchronous LVTTL parallel input interface

• Synchronous LVTTL parallel output interface

• 200-to-1500 MBaud serial signaling rate

• Internal PLLs with no external PLL components

• Dual differential LVPECL-compatible serial inputs

— Internal DC-restoration

The transmit channel accepts parallel characters in an Input

Register, encodes each character for transport, and converts

it to serial data. The receive channel accepts serial data and

converts it to parallel data, decodes the data into characters,

and presents these characters to an Output Register. Figure 1

illustrates typical connections between independent host sys-

tems and corresponding CYP15G0101DXA parts. As a sec-

ond-generation HOTLink device, the CYP15G0101DXA ex-

tends the HOTLink II family with enhanced levels of integration

and faster data rates, while maintaining serial-link compatibility

(data, command, and BIST) with other HOTLink devices.

• Dual differential LVPECL-compatible serial outputs

— Source matched for 50Ω transmission lines

— No external bias resistors required

— Signaling-rate controlled edge-rates

The transmit (TX) section of the CYP15G0101DXA Single

Channel HOTLink II consists of a byte-wide channel. The

channel can accept either 8-bit data characters or pre-encod-

10

Serial Link

10

Backplane or

Cabled

Connections

Figure 1. HOTLink II™ System Connections

Cypress Semiconductor Corporation

Document #: 38-02061 Rev. **

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised April 25, 2002

PRELIMINARY

CYP15G0101DXA

ed 10-bit transmission characters. Data characters are passed

from the Transmit Input Register to an embedded 8B/10B En-

coder to improve their serial transmission characteristics.

These encoded characters are then serialized and output from

dual Positive ECL (PECL) compatible differential transmis-

sion-line drivers at a bit-rate of either 10- or 20-times the input

reference clock.

systems that present externally encoded or scrambled data at

the parallel interface.

The parallel I/O interface may be configured for numerous

forms of clocking to provide the highest flexibility in system

architecture. In addition to clocking the transmit path interfaces

from one or multiple sources, the receive interface may be

configured to present data relative to a recovered clock (out-

put) or to a local reference clock (input).

The receive (RX) section of the CYP15G0101DXA Single

Channel HOTLink II consists of a byte-wide channel. The

channel accepts a serial bit-stream from one of two PECL-

compatible differential Line Receivers and, using a completely

integrated PLL Clock Synchronizer, recovers the timing infor-

mation necessary for data reconstruction. The recovered bit-

stream is deserialized and framed into characters, 8B/10B de-

coded, and checked for transmission errors. Recovered de-

coded characters are then written to an internal Elasticity Buff-

er, and presented to the destination host system. The

integrated 8B/10B Encoder/Decoder may be bypassed for

Both the transmit and the receive channels contain indepen-

dent Built-In Self-Test (BIST) pattern generators and checkers.

This BIST hardware allows at-speed testing of the high-speed

serial data paths in both transmit and receive sections, as well

as across the interconnecting links.

HOTLink II devices are ideal for a variety of applications where

parallel interfaces can be replaced with high-speed, point-to-

point serial links. Some applications include interconnecting

backplanes on basestations, switches, routers, servers and

video transmission equipment.

CYP15G0101DXA Transceiver Logic Block Diagram

x10

x11

Phase

Align

Buffer

Elasticity

Buffer

Decoder

8B/10B

Encoder

8B/10B

Framer

Serializer

Deserializer

RX

TX

Document #: 38-02061 Rev. **

Page 2 of 40

PRELIMINARY

CYP15G0101DXA

= Internal Signal

TRSTZ

Logic Block Diagram

REFCLK+

REFCLK–

TXRATE

Character-Rate Clock

Transmit PLL

Clock Multiplier

Bit-Rate Clock

SPDSEL

Character-Rate Clock

TXCLKO+

TXCLKO–

2

Transmit

Mode

TXMODE[1:0]

TXPER

SCSEL

12

10

12

OUT1+

OUT1–

TXD[7:0]

8

TXOP

OUT2+

OUT2–

2

TXCT[1:0]

TXLB

TXCKSEL

H M L

2

TXCLK

TXRST

4

Output

Enable

Latch

PARCTL

BOE[1:0]

OELE

BIST Enable

Latch

RX PLL Enable

Latch

BISTLE

RXLE

Character-Rate Clock

SDASEL

LPEN

INSEL

Receive

Signal

LFI

Monitor

IN1+

IN1–

8

RXD[7:0]

IN2+

Clock &

Data

Recovery

PLL

RXOP

IN2–

3

RXST[2:0]

TXLB

FRAMCHAR

RFEN

RXCLK+

RXCLK–

Clock

Select

÷2

RFMODE

Delay

DECMODE

RXCKSEL

RXMODE

RXRATE

RXCLKC+

TMS

TCLK

TDI

JTAG

Boundary

Scan

Controller

TDO

Document #: 38-02061 Rev. **

Page 3 of 40

PRELIMINARY

CYP15G0101DXA

Pin Configuration

Top View

1

2

3

4

5

6

7

8

9

10

IN2+

OUT2–

RX

TX

MODE

[1]

IN1+

OUT1–

A

B

V_CC

TDO

V_CC

N/C

V_CC

MODE

IN2–

OUT2+

TX

RATE

TX

MODE

[0]

IN1–

OUT1+

V_CC

RFEN

V_CC

INSEL

TDI

LPEN

RXLE

RX

CLKC+

RX

RATE

SDA

SEL

SPD

SEL

PAR

CTL

RF

MODE

C

D

E

F

BOE[0]

BISTLE

BOE[1]

FRAM

CHAR

TMS

TRSTZ

GND GND GND GND

DEC

MODE

OELE

TCLK

RX

CKSEL

TX

CKSEL

RX

ST[2]

RX

ST[1]

RX

ST[0]

TX

PER

REF

CLK–

REF

CLK+

RXOP

RX

D[1]

RX

D[5]

TXOP

TX

CLKO+

TX

CLKO–

G

H

J

RX

D[0]

RX

D[2]

RX

D[6]

LFI

TX

CT[1]

TX

D[6]

TX

D[3]

TX

CLK

TXRST

#NC

TX

D[0]

RX

D[3]

RX

D[7]

RX

CLK–

TX

CT[0]

TX

D[5]

TX

D[2]

V_CC

RX

D[4]

RX

CLK+

TX

D[7]

TX

D[4]

TX

D[1]

SCSEL

K

V_CC

Bottom View

10

9

8

7

6

5

4

3

2

1

OUT1–

IN1+

TX

MODE

[1]

RX

OUT2–

IN2+

V_CC

#NC

V_CC

TDO

V_CC

A

B

MODE

OUT1+

IN1–

TX

MODE

[0]

TX

RATE

OUT2+

IN2–

V_CC

INSEL

TDI

V_CC

RFEN

RF

MODE

PAR

CTL

SPD

SEL

SDA

SEL

RX

RATE

RX

CLKC+

RXLE

LPEN

C

D

E

F

TRSTZ

TMS

FRAM

CHAR

BOE[1]

BOE[0]

BISTLE

GND GND GND GND

TX

CKSEL

RX

CKSEL

TCLK

OELE

DEC

MODE

REF

CLK+

REF

CLK–

TX

PER

RX

ST[0]

RX

ST[1]

RX

ST[2]

TX

CLKO–

TX

CLKO+

TXOP

RX

D[5]

RX

D[1]

RXOP

G

H

J

#NC

TXRST

#NC

TX

CLK

TX

D[3]

TX

D[6]

TX

CT[1]

LFI

RX

D[6]

RX

D[2]

RX

D[0]

TX

D[0]

TX

D[2]

TX

D[5]

TX

CT[0]

RX

CLK–

RX

D[7]

RX

D[3]

V_CC

SCSEL

TX

D[1]

TX

D[4]

TX

D[7]

RX

CLK+

RX

D[4]

V_CC

K

NOTE: #NC = DO NOT CONNECT

Document #: 38-02061 Rev. **

Page 4 of 40

PRELIMINARY

CYP15G0101DXA

Pin Descriptions

CYP15G0101DXA Single Channel HOTLink II™ Transceiver

Name I/O Characteristics

Transmit Path Data Signals

Signal Description

TXPER

LVTTL Output,

Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled

changes relative to (PARCTL ≠ LOW) and a parity error is detected at the Encoder. This output is HIGH for

[1]

REFCLK↑

one transmit character-clock period to indicate detection of a parity error in the character

presented to the Encoder.

If a parity error is detected, the character in error is replaced with a C0.7 character to

force a corresponding bad-character detection at the remote end of the link. This re-

placement takes place regardless of the encoded/non-encoded state of the interface.

This output provides an indication of a Phase-Align Buffer underflow/overflow condition.

When the Phase-Align Buffer is enabled (TXCKSEL ≠ LOW, or TXCKSEL = LOW and

TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted

and remains asserted until either an atomic Word Sync Sequence is transmitted or

TXRST is sampled LOW to re-center the Phase-Align Buffer.

When BIST is enabled (BISTLE = HIGH) for the transmit channel, BIST progress is

presented on this output. Once every 511 character times (plus a 16-character Word

Sync Sequence when the receive interface is clocked by REFCLK), the TXPER signal

will pulse HIGH for one transmit-character clock period to indicate a complete pass

through the BIST sequence.

TXCT[1:0]

LVTTL Input,

synchronous,

Transmit Control. These inputs are captured on the rising edge of the transmit interface

clock as selected by TXCKSEL, and are passed to the Encoder or Transmit Shifter. They

sampledbyTXCLK↑ identify how the TXD[7:0] characters are interpreted. When the Encoder is bypassed,

[1]

or REFCLK↑

these inputs are interpreted as data bits. When the Encoder is enabled, these inputs

determine if the TXD[7:0] character is encoded as Data, a Special Character code, or

replaced with other Special Character codes. See Table 1 for details.

TXD[7:0]

TXOP

LVTTL Input,

synchronous,

sampledbyTXCLK↑

or REFCLK↑

Transmit Data Inputs. These inputs are captured on the rising edge of the transmit

interface clock as selected by TXCKSEL, and passed to the Encoder or Transmit Shifter.

When the Encoder is enabled (TXMODE[1:0] ≠ LL), TXD[7:0] specify the specific data

or command character to be sent.

[1]

LVTTL Input,

synchronous,

internal pull-up,

sampled by

Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the

parity captured at this input is XORed with the data on the TXD bus to verify the integrity

of the captured character.

TXCLK↑ or

[1]

REFCLK↑

TXRST

LVTTL Input, asyn- Transmit Clock Phase Reset. Active LOW. When sampled LOW, the transmit Phase-

chronous,

Align Buffer is allowed to adjust its data-transfer timing (relative to TXCLK↑) to allow

clean transfer of data from the Input Register to the Encoder or Transmit Shift Register.

When TXRST is deasserted (HIGH), the internal phase relationship between TXCLK↑

and the internal character-rate clock is fixed and the device operates normally.

internal pull-up,

sampled by

TXCLK↑ or

[1]

REFCLK↑

When configured for half-rate REFCLK sampling of the transmit character stream

(TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear

Phase-Align Buffer faults caused by highly asymmetric REFCLK periods or REFCLK

inputs with excessive cycle-to-cycle jitter.

During this alignment period, one or more characters may be added to or lost from the

transmit path as the Phase-Align Buffer is cleared or reset.

TXRST must be sampled LOW by a minimum of two consecutive rising edges of TXCLK

(or one REFCLK↑) to ensure the reset operation is initiated correctly on the channel.

This input is not interpreted when both TXCKSEL and TXRATE are LOW.

Note:

1. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling

edges of REFCLK.

Document #: 38-02061 Rev. **

Page 5 of 40

PRELIMINARY

CYP15G0101DXA

Pin Descriptions (continued)

CYP15G0101DXA Single Channel HOTLink II™ Transceiver

Name

SCSEL

I/O Characteristics

Signal Description

LVTTL Input,

synchronous,

internal pull-down,

sampled by

Special Character Select. Used in some transmit modes along with TXCT[1:0] to en-

code special characters or to initiate a Word Sync Sequence.

TXCLK↑

or REFCLK↑

[1]

Transmit Path Clock and Clock Control

TXCKSEL

3-Level Select ^[2]

static control input

Transmit Clock Select. Selects the clock source, used to write data into the Transmit

Input Register, of the transmit channel.

[1]

When LOW, the Input Register is clocked by REFCLK↑

.

When HIGH or MID, TXCLK↑ is the Input Register clock for TXD[7:0] and TXCT[1:0].

TXCLKO±

LVTTL Output

Transmit Clock Output. This true and complement output clock is synthesized by the

transmit PLL and operates synchronous to the internal transmit character clock. It op-

erates at either the same frequency as REFCLK, or at twice the frequency of REFCLK

(as selected by TXRATE). TXCLKO± is always equal to the transmit VCO bit-clock

frequency ÷10. This output clock has no direct phase relationship to REFCLK or the

recovered character clock.

TXRATE

LVTTL Input,

Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies

Static Control input, REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit

internal pull-down

PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See Table 9 for a list

of operating serial rates.

When REFCLK is selected to clock the receive parallel interface (RXCKSEL = LOW),

the TXRATE input also determines if the clocks on the RXCLK± and RXCLKC+ outputs

are full or half-rate. When TXRATE = HIGH, these output clocks are half-rate clocks and

follow the frequency and duty cycle of the REFCLK input. When TXRATE = LOW, these

output clocks are full-rate clocks and follow the frequency and duty cycle of the REFCLK

input.

TXCLK

LVTTL Clock Input, Transmit Path Input Clock. This clock must be frequency-coherent to TXCLKO±, but

internal pull-down

may be offset in phase. The internal operating phase of the input clock (relative to

REFLCK or TXCLKO+) is adjusted when TXRST = LOW and locked when

TXRST = HIGH.

Transmit Path Mode Control

TXMODE[1:0]

3-Level Select ^[2]

Transmit Operating Mode. These inputs are interpreted to select one of nine operating

static control inputs modes of the transmit path. See Table 3 for a list of operating modes.

Receive Path Data Signals

RXD[7:0]

LVTTL Output,

synchronous to the receive interface clock.

Parallel Data Output. These outputs change following the rising edge of the selected

RXCLK↑ output or

REFCLK↑ ^[1]input

RXST[2:0]

LVTTL Output,

synchronous to the receive interface clock.

Parallel Status Output. These outputs change following the rising edge of the selected

RXCLK↑ output or

When the Decoder is bypassed (DECMODE = LOW), RXST[1:0] become the two low-

order bits of the 10-bit received character, while RXST[2] = HIGH indicates the pres-

ence of a Comma character in the Output Register.

REFCLK↑ ^[1]input

When the Decoder is enabled (DECMODE = HIGH), RXST[1:0] provide status of the

received signal. See Table 17 for a list of Receive Character status.

Note:

2. 3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.

The LOW level is usually implemented by direct connection to V_SS(ground). The HIGH level is usually implemented by direct connection to V_CC(power). When

not connected or allowed to float, a 3-Level select input will self-bias to the MID level.

Document #: 38-02061 Rev. **

Page 6 of 40

PRELIMINARY

CYP15G0101DXA

Pin Descriptions (continued)

CYP15G0101DXA Single Channel HOTLink II™ Transceiver

Name

RXOP

I/O Characteristics

Signal Description

Receive Path Odd Parity. When parity generation is enabled (PARCTL ≠ LOW), the

3-state, LVTTL

Output,synchronous parity output is valid for the data on the RXD bus bits. When parity generation is disabled

to the

(PARCTL = LOW) this output driver is disabled (High-Z).

RXCLK↑ output or

REFCLK↑ ^[1]input

Receive Path Clock and Clock Control

RXRATE

LVTTL Input

Static Control Input,

internal pull-down

Receive Clock Rate Select.

When LOW, the RXCLK± recovered clock outputs are complementary clocks operating

at the recovered character rate. Data for the receive channel should be latched on either

the rising edge of RXCLK+ or falling edge of RXCLK–.

When HIGH, the RXCLK± recovered clock outputs are complementary clocks operating

at half the character rate. Data for the receive channel should be latched alternately on

the rising edge of RXCLK+ and RXCLK–.

When operated with REFCLK clocking of the received parallel data outputs

(RXCKSEL = LOW), RXRATE must be LOW.

RXCLK±

3-state, LVTTL

Output clock

Receive Character Clock Output or Clock Select Input. When the receive Elasticity

Buffer is disabled (RXCKSEL = MID), this true and complement clock is the Receive

Interface Clock. This is used to control timing of data output transfers. This clock is

output continuously at either the dual-character rate (1/20^ththe serial bit-rate) or char-

acter rate (1/10^ththe serial bit-rate) of the data being received, as selected by RXRATE.

When configured such that all output data path is clocked by REFCLK instead of a

recovered clock (RXCKSEL = LOW), the RXCLK± and RXCLKC+ output drivers

present a buffered form of REFCLK. RXCLK± and RXCLKC+ are buffered forms of

REFCLK that are slightly different in phase. This phase difference allows the user to

select the optimal setup/hold timing for their specific interface.

RXCLKC+

3-state, LVTTL

Output clock

Received Character Clock Output Delayed.

When configured such that the output data path is clocked by REFCLK instead of a

recovered clock (RXCKSEL = LOW), the RXCLKC+ output driver presents a buffered

form of REFCLK that is slightly different in phase from RXCLK±. This phase difference

allows the user to select the optimal setup/hold timing for their specific interface.

RFEN

LVTTL input,

Reframe Enable. Active HIGH. When HIGH, the Framer in the receive channel is en-

asynchronous,

abled to frame per the presently enabled framing mode and selected framing character.

internal pull-down

RXMODE

RXCKSEL

3-Level Select ^[2]

static control input

Receive Operating Mode. This input selects one of two RXST channel status reporting

modes and is only interpreted when the Decoder is enabled (DECMODE ≠ LOW). See

Table 13 for details.

3-Level Select ^[2]

static control input

Receive Clock Mode. Selects the receive clock source used to transfer data to the

Output Registers and configures the Elasticity Buffer in the receive path.

When LOW, the Output Register is clocked by REFCLK. RXCLK± and RXCLKC+

present buffered and delayed forms of REFCLK.

When MID, the RXCLK± output follows the recovered clock as selected by RXRATE

and the Elasticity Buffer is bypassed.

HIGH is an invalid state for this input.

FRAMCHAR

3-Level Select ^[2]

static control input

Framing Character Select. Used to select the character or portion of a character used

for character framing of the received data streams.

When MID, the Framer looks for both positive and negative disparity versions of the 8-

bit Comma character.

When HIGH, the Framer looks for both positive and negative disparity versions of the

K28.5 character.

The LOW selection is reserved for component test.

Document #: 38-02061 Rev. **

Page 7 of 40

PRELIMINARY

CYP15G0101DXA

Pin Descriptions (continued)

CYP15G0101DXA Single Channel HOTLink II™ Transceiver

Name

RFMODE

I/O Characteristics

3-Level Select ^[2]

static control input

Signal Description

Reframe Mode Select. Used to select the type of character framing used to adjust the

character boundaries (based on detection of one or more framing characters in the data

stream. This signal operates in conjunction with the type of framing character selected.

When LOW, the Low-Latency Framer is selected. This will frame on each occurrence

of the selected framing character(s) in the received data stream. This mode of framing

stretches the recovered clock for one or multiple cycles to align that clock with the

recovered data.

When MID, the Cypress-mode multi-byte parallel Framer is selected. This requires a

pair of the selected framing character(s), on identical 10-bit boundaries, within a span

of 50 bits, before the character boundaries are adjusted. The recovered character clock

remains in the same phasing regardless of character offset.

When HIGH, the Alternate-mode multi-byte parallel Framer is selected. This requires

detection of the selected framing character(s) of the allowed disparities in the received

data stream, on identical 10-bit boundaries, on four directly adjacent characters. The

recovered character clock remains in the same phasing regardless of character offset.

DECMODE

3-Level Select ^[2]

static control input

Decoder Mode Select.

When LOW, the Decoder is bypassed and raw 10-bit characters are passed to the

Output Register.

When MID, the Cypress Decoder table for Special Code Characters is used.

When HIGH, the alternate Decoder table for Special Code Characters is used. See

Table 22 for a list of the Special Codes supported in both encoded modes.

Device Control Signals

PARCTL

3-Level Select ^[2]

static control input

Parity Check/Generate Control. Used to control the parity check and generate func-

tions.

When LOW, parity checking is disabled, and the RXOP output is disabled (High-Z).

When MID, and the 8B/10B Encoder and Decoder are enabled (TXMODE[1] ≠ LOW,

DECMODE ≠ LOW), TXD[7:0] inputs are checked (along with TXOP) for valid ODD

parity, and ODD parity is generated for the RXD[7:0] outputs and presented on RXOP.

When the 8B/10B Encoder and Decoder are disabled (TXMODE[1] = LOW,

DECMODE = LOW), the TXD[7:0] and TXCT[1:0] inputs are checked (along with TXOP)

for valid ODD parity, and ODD parity is generated for the RXD[7:0] and RXST[1:0]

outputs and presented on RXOP.

When HIGH, parity generation and checking are enabled. The TXD[7:0] and TXCT[1:0]

inputs are checked (along with TXOP) for valid ODD parity, and ODD parity is generated

for the RXD[7:0] and RXST[2:0] outputs and presented on RXOP.

SPDSEL

3-Level Select ^[2]

static control input

,

Serial Rate Select. This input specifies the operating bit-rate range of both transmit and

receive PLLs. LOW = 200–400 MBd, MID = 400–800 MBd, HIGH = 800–1500 MBd.

REFCLK±

Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and

or single-ended

receive PLLs. This input clock may also be selected to clock the transmit and receive

parallel interfaces. When driven by a single-ended LVCMOS or LVTTL clock source,

connect the clock source to either the true or complement REFCLK input, and leave the

alternate REFCLK input open (floating). When driven by an LVPECL clock source, the

clock must be a differential clock, using both inputs.

LVTTL input clock

When TXCKSEL = LOW, REFCLK is also used as the clock for the parallel transmit data

(input) interface.

When RXCKSEL = LOW, REFCLK is also used as the clock source for the parallel

receive data (output) interface.

Document #: 38-02061 Rev. **

Page 8 of 40

PRELIMINARY

CYP15G0101DXA

Pin Descriptions (continued)

CYP15G0101DXA Single Channel HOTLink II™ Transceiver

Name

TRSTZ

I/O Characteristics

Signal Description

LVTTL Input,

Device Reset. Active LOW. Initializes all state machines and counters in the device.

internal pull-up

When sampled LOW by the rising edge of REFLCK, this input resets the internal state

machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is

removed (TRSTZ sampled HIGH by REFCLK↑), the status and data outputs will be-

come deterministic in less than 16 REFCLK cycles.

The BISTLE, OELE, and RXLE latches are reset by TRSTZ.

If the Elasticity Buffer or the Phase-Align Buffer are used, TRSTZ should be applied

after power up to initialize the internal pointers into these memory arrays.

Analog I/O and Control

OUT1±

CML Differential

Output

Primary Differential Serial Data Outputs. These PECL-compatible CML outputs

(+3.3V referenced) are capable of driving terminated transmission lines or standard

fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compat-

ible connections.

OUT2±

CML Differential

Output

Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs

(+3.3V referenced) are capable of driving terminated transmission lines or standard

fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compat-

ible connections.

IN1±

LVPECL Differential Primary Differential Serial Data Inputs. These inputs accept the serial data stream for

Input

deserialization and decoding. The IN1± serial stream is passed to the receiver Clock

and Data Recovery (CDR) circuit to extract the data content when INSEL = HIGH.

IN2±

LVPECL Differential Secondary Differential Serial Data Inputs. These inputs accept the serial data stream

Input

for deserialization and decoding. The IN2± serial stream is passed to the receiver Clock

and Data Recovery (CDR) circuit to extract the data content when INSEL = LOW.

INSEL

LVTTL Input,

asynchronous

Receive Input Selector. Determines which external serial bit stream is passed to the

receiver Clock and Data Recovery circuit. When HIGH, the IN1± input is selected. When

LOW, the IN2± input is selected.

SDASEL

LPEN

3-Level Select ^[2]

static control input

,

Signal Detect Amplitude Level Select. Allows selection of one of three predefined

amplitude trip points for a valid signal indication, as listed in Table 10.

LVTTL Input,

asynchronous,

internal pull-down

Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial data is

internally routed to the receiver Clock and Data Recovery (CDR) circuit. All enabled

serial drivers are forced to differential logic “1”. All serial data inputs are ignored.

OELE

LVTTL Input,

asynchronous,

internal pull-up

Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the

signals on the BOE[1:0] inputs directly control the OUTxy± differential drivers. When the

BOE[x] input is HIGH, the associated OUTx± differential driver is enabled. When the

BOE[x] input is LOW, the associated OUTx± differential driver is powered down. When

OELE returns LOW, the last values present on BOE[1:0] are captured in the internal

Output Enable Latch. The specific mapping of BOE[1:0] signals to transmit output en-

ables is listed in Table 8.

If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable both outputs.

BISTLE

LVTTL Input,

asynchronous,

internal pull-up

Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the

signals on the BOE[1:0] inputs directly control the transmit and receive BIST enables.

When the BOE[x] input is LOW, the associated transmit or receive channel is configured

to generate or compare the BIST sequence. When the BOE[x] input is HIGH, the asso-

ciated transmit or receive channel is configured for normal data transmission or recep-

tion. When BISTLE returns LOW, the last values present on BOE[1:0] are captured in

the internal BIST Enable latch. The specific mapping of BOE[1:0] signals to transmit and

receive BIST enables is listed in Table 8.

When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is

reset to disable BIST on both the transmit and receive channels.

Document #: 38-02061 Rev. **

Page 9 of 40

PRELIMINARY

CYP15G0101DXA

Pin Descriptions (continued)

CYP15G0101DXA Single Channel HOTLink II™ Transceiver

Name

RXLE

I/O Characteristics

Signal Description

LVTTL Input,

asynchronous,

internal pull-up

Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE = HIGH,

the signal on the BOE[0] input directly controls the power enable for the receive PLL

and analog logic. When the BOE[0] input is HIGH, the receive channel PLL and analog

logic are active. When the BOE[0] input is LOW, the receive channel PLL and analog

logic are placed in a non-functional power saving mode. When RXLE returns LOW, the

last value present on BOE[0] is captured in the internal RX PLL Enable latch. The

specific mapping of BOE[1:0] signals to the receive channel enable is listed in Table 8.

When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is

reset to disable the receive channel.

BOE[1:0]

LVTTL Input,

asynchronous,

internal pull-up

BIST, Serial Output, and Receive Channel Enables.

These inputs are passed to and through the output enable latch when OELE = HIGH,

and captured in this latch when OELE returns LOW.

These inputs are passed to and through the BIST enable latch when BISTLE = HIGH,

and captured in this latch when BISTLE returns LOW.

These inputs are passed to and through the Receive Channel enable latch when

RXLE = HIGH, and captured in this latch when RXLE returns LOW.

LFI

LVTTL Output,

Link Fault Indication Output. Active LOW. LFI is the logical OR of four internal condi-

synchronous to the tions:

selected RXCLK↑

1. Received serial data frequency outside expected range

output or

REFCLK↑ ^[1]input,

asynchronous to

receive channel

enable/disable

2. Analog amplitude below expected levels

3. Transition density lower than expected

4. Receive Channel disabled

Interface

TMS

LVTTL Input,

internal pull-up

Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high

for >5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset

automatically upon application of power to the device.

TCLK

TDO

LVTTL Input,

internal pull-down

JTAG Test Clock

Three-State

LVTTL Output

Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not

selected.

TDI

LVTTL Input,

internal pull-up

Test Data In. JTAG data input port.

TSTCLK

LVTTLInput,internal Test Clock Input. For internal use. Tie HIGH for normal operation

pull-up

Power

V_CC

+3.3V Power

GND

Signal and Power Ground for all internal circuits

Document #: 38-02061 Rev. **

Page 10 of 40

PRELIMINARY

CYP15G0101DXA

When an Input-Register clock with an uncontrolled phase re-

lationship to REFCLK is selected (TXCKSEL ≠ LOW) or if data

is captured on both edges of REFCLK (TXRATE = HIGH), the

Phase-Align Buffer is enabled. This buffer is used to absorb

clock phase differences between the presently selected input

clock and the internal character clock.

CYP15G0101DXA HOTLink II Operation

The CYP15G0101DXA is a highly configurable device de-

signed to support reliable transfer of large quantities of data,

using a high-speed serial links, from a single source to one or

more destinations.

Initialization of the Phase-Align Buffer takes place when the

TXRST input is sampled LOW by TXCLK↑. When TXRST is

returned HIGH, the present input clock phase relative to

REFCLK↑ is set. TXRST is an asynchronous input, but is sam-

pled internally to synchronize it to the internal transmit path

state machine. TXRST must be sampled LOW by a minimum

of two consecutive TXCLK↑ clocks to ensure the reset opera-

tion is initiated correctly.

CYP15G0101DXA Transmit Data Path

Operating Modes

The transmit path of the CYP15G0101DXA supports a single-

character-wide data path. This data path is used in multiple

operating modes as controlled by the TXMODE[1:0] inputs.

Input Register

Once set, the input clock is allowed to skew in time up to half

a character period in either direction relative to REFCLK↑; i.e.,

±180°. This time shift allows the delay path of the character

clock (relative to REFLCK↑) to change due to operating volt-

age and temperature, while not affecting the design operation.

Within these operating modes, the bits in the Input Register

support different bit assignments, based on if the character is

unencoded, encoded with two control bits, or encoded with

three control bits. These assignments are shown in Table 1.

Table 1. Input Register Bit Assignments^[3]

If the phase offset, between the initialized location of the input

clock and REFCLK↑, exceeds the skew handling capabilities

of the Phase-Align Buffer, an error is reported on the TXPER

output. This output indicates a continuous error until the

Phase-Align Buffer is reset. While the error remains active, the

transmitter will output a continuous C0.7 character to indicate

to the remote receiver that an error condition is present in the

link.

Encoded

(Encoder Enabled)

Unencoded

(Encoder

2-bit

3-bit

Signal Name

TXD[0] (LSB)

TXD[1]

Bypassed)

Control

DIN[0]

DIN[1]

DIN[2]

DIN[3]

DIN[4]

DIN[5]

DIN[6]

DIN[7]

DIN[8]

DIN[9]

N/A

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

N/A

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

SCSEL

In specific transmit modes it is also possible to reset the

Phase-Align Buffer and with minimal disruption of the serial

data stream. When the transmit interface is configured for gen-

eration of atomic Word Sync Sequences (TXMODE[1] = MID)

and a Phase-Align Buffer error is present, the transmission of

a Word Sync Sequence will re-center the Phase-Align Buffer

and clear the error condition.

TXD[2]

TXD[3]

TXD[4]

TXD5]

TXD[6]

TXD[7]

NOTE: One or more K28.5 characters may be added or lost

from the data stream during this reset operation. When

used with non-Cypress devices that require a complete 16-

character Word Sync Sequence for proper receive Elastic-

ity Buffer alignment, it is recommend that the sequence be

followed by a second Word Sync Sequence to ensure prop-

er operation.

TXCT[0]

TXCT[1] (MSB)

SCSEL

Note:

3. The TXOP input is also captured in the Input Register, but its interpreta-

tion is under the separate control of PARCTL.

Parity Support

The Input Register captures a minimum of eight data bits and

two control bits on each input clock cycle. When the Encoder

is bypassed, the control bits are part of the pre-encoded 10-bit

data character.

In addition to the ten data and control bits that are captured at

the transmit Input Register, a TXOP input is also available.

This allows the CYP15G0101DXA to support ODD parity

checking. Parity checking is available for all operating modes

(including Encoder Bypass). The specific mode of parity

checking is controlled by the PARCTL input, and operates per

Table 2.

When the Encoder is enabled (TXMODE[1] ≠ LOW), the

TXCT[1:0] bits are interpreted along with the TXD[7:0] charac-

ter to generate the specific 10-bit transmission character.

When TXMODE[0] ≠ HIGH, an additional special character

select (SCSEL) input is also captured and interpreted. This

SCSEL input is used to modify the encoding of the characters.

When PARCTL = MID (open) and the Encoder is enabled

(TXMODE[1] ≠ LOW), only the TXD[7:0] data bits are checked

for ODD parity along with the TXOP bit. When

PARCTL = HIGH with the Encoder enabled (or MID with the

Encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are

checked for ODD parity along with the TXOP bit. When

PARCTL = LOW, parity checking is disabled.

Phase-Align Buffer

Data from the Input Register is passed either to the Encoder

or to the Phase-Align buffer. When the transmit path is operat-

ed synchronous to REFCLK↑ (TXCKSEL = LOW and

TXRATE = LOW), the Phase-Align Buffer is bypassed and

data is passed directly to the Parity Check and Encoder block

to reduce latency.

When parity checking and the Encoder are both enabled

(TXMODE[1] ≠ LOW), the detection of a parity error causes a

C0.7 character of proper disparity to be passed to the Transmit

Shifter. When the Encoder is bypassed (TXMODE[1] = LOW),

Document #: 38-02061 Rev. **

Page 11 of 40

PRELIMINARY

CYP15G0101DXA

Table 2. Input Register Bits Checked for Parity^[4]

Transmit Parity Check Mode (PARCTL)

• run-length limits in the serial data (to limit the bandwidth of

the link)

• the remote receiver a way of determining the correct char-

acter boundaries (framing).

LOW

MID

HIGH

When the Encoder is enabled (TXMODE[1] ≠ LOW), the char-

acters to be transmitted are converted from Data or Special

Character codes to 10-bit transmission characters (as select-

ed by the TXCT[1:0] and SCSEL inputs), using an integrated

8B/10B Encoder. When directed to encode the character as a

Special Character code, it is encoded using the Special Char-

acter encoding rules listed in Table 22. When directed to en-

code the character as a Data character, it is encoded using the

Data Character encoding rules in Table 21.

Signal

Name

TXMODE[1] TXMODE[1]

= LOW

≠ LOW

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXCT[0]

TXCT[1]

TXOP

X^[5]

X

The 8B/10B Encoder is standards compliant with ANSI/NCITS

ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit

Ethernet), the IBM ESCON and FICON™ channels, Digital

Video Broadcast (DVB-ASI) and ATM Forum standards for

data transport.

X

Many of the Special Character codes listed in Table 22 may be

generated by more than one input character. The

CYP15G0101DXA is designed to support two independent

(but non-overlapping) Special Character code tables. This al-

lows the CYP15G0101DXA to operate in mixed environments

with other Cypress HOTLink devices using the enhanced Cy-

press command code set, and the reduced command sets of

other non-Cypress devices. Even when used in an environ-

ment that normally uses non-Cypress Special Character

codes, the selective use of Cypress command codes can per-

mit operation where running disparity and error handling must

be managed.

X

Note:

4. Transmit path parity errors are reported on the TXPER output.

5. Bits marked as X are XORed together. Result must be a logic-1 for parity

to be valid.

detection of a parity error causes a positive disparity version

of a C0.7 transmission character to be passed to the Transmit

Shifter.

Encoder

The character, received from the Input Register or Phase-

Align Buffer and Parity Check Logic, is then passed to the

Encoder logic. This block interprets each character and any

control bits, and outputs a 10-bit transmission character.

Following conversion of each input character from 8 bits to a

10-bit transmission character, it is passed to the Transmit

Shifter and is shifted out LSB first, as required by ANSI and

IEEE standards for 8B/10B coded serial data streams.

Depending on the configured operating mode, the generated

transmission character may be

Transmit Modes

The operating mode of the transmit path is set through the

TXMODE[1:0] inputs. These 3-level select inputs allow one of

nine transmit modes to be selected. Within each of these op-

erating modes, the actual characters generated by the Encod-

er logic block are also controlled both by these and other static

and dynamic control signals. The transmit modes are listed in

Table 3.

• the 10-bit pre-encoded character accepted inthe Input Reg-

ister

• the 10-bit equivalent of the 8-bit Data character accepted in

the Input Register

• the 10-bit equivalent of the 8-bit Special Character code

accepted in the Input Register

• the 10-bit equivalent of the C0.7 SVS character if parity

checking was enabled and a parity error was detected

• the 10-bit equivalent of the C0.7 SVS character if a Phase-

Align Buffer overflow or underflow error is present

The encoded modes (TX Modes 3 through 8) support multiple

encoding tables. These encoding tables vary by the specific

combinations of SCSEL, TXCT[1], and TXCT[0] that are used

to control the generation of data and control characters. These

multiple encoding forms allow maximum flexibility in interfac-

ing to legacy applications, while also supporting numerous ex-

tensions in capabilities.

• a character that is part of the 511-character BIST sequence

• a K28.5 character generated as an individual character or

as part of the 16-character Word Sync Sequence.

The selection of the specific characters generated are con-

trolled by the TXMODE[1:0], SCSEL, TXCT[1:0], and TXD[7:0]

inputs for each character.

TX Mode 0—Encoder Bypass

When the Encoder is bypassed, the character captured from

the TXD[7:0] and TXCT[1:0] inputs is passed directly to the

Transmit Shifter without modification. If parity checking is en-

abled (PARCTL ≠ LOW) and a parity error is detected, the 10-

bit character is replaced with the 1001111000 pattern (+C0.7

character) regardless of the running disparity of the previous

character.

Data Encoding

Raw data, as received directly from the Transmit Input Regis-

ter, is seldom in a form suitable for transmission across a serial

link. The characters must usually be processed or transformed

to guarantee

• aminimum transitiondensity(toallowtheserialreceivePLL

With the Encoder bypassed, the TXCT[1:0] inputs are consid-

ered part of the data character and do not perform a control

function that would otherwise modify the interpretation of the

to extract a clock from the data stream)

• a DC-balance in the signaling (to prevent baseline wander)

Document #: 38-02061 Rev. **

Page 12 of 40

PRELIMINARY

CYP15G0101DXA

Table 3. Transmit Operating Modes

TX Mode Operating Mode

Table 5. TX Modes 3 and 6 Encoding

Word Sync

Characters Generated

Encoded data character

Sequence

Support

SCSEL

Control

X

0

1

X

0

1

0

1

TXCT Function

Encoder Bypass

Reserved for test

Encoder Control

K28.5 fill character

0

1

2

3

LL None

None

Special character code

LM None

LH None

ML Atomic

16-character Word Sync Sequence

Special

Character

Word Sync Sequence

When TXCT[1:0] = 11, a 16-character sequence of K28.5

characters, known as a Word Sync Sequence, is generated on

the transmit channel. This sequence of K28.5 characters may

start with either a positive or negative disparity K28.5 (as de-

termined by the current running disparity and the 8B/10B cod-

ing rules). The disparity of the second and third K28.5 charac-

ters in this sequence are reversed from what normal 8B/10B

coding rules would generate. The remaining K28.5 characters

in the sequence follow all 8B/10B coding rules. The disparity

of the generated K28.5 characters in this sequence follow a

4

5

6

MM Atomic

MH Atomic

Word Sync Encoder Control

None

Encoder Control

HL Interruptible Special

Character

7

8

HM Interruptible Word Sync Encoder Control

HH Interruptible None Encoder Control

TXD[7:0] bits. The bit usage and mapping of these control bits

when the Encoder is bypassed is shown in Table 4.

pattern

of

either

++––+–+–+–+–+–+–

or

––++–+–+–+–+–+–+.

In Encoder Bypass mode the SCSEL input is ignored. All

clocking modes interpret the data in the same way.

When TXMODE[1] = MID (open, TX modes 3, 4, and 5), the

generation of this character sequence is an atomic (non-inter-

ruptible) operation. Once it has been successfully started, it

cannot be stopped until all 16 characters have been generat-

ed. The content of the Input Register is ignored for the duration

of this 16-character sequence. At the end of this sequence, if

the TXCT[1:0] = 11 condition is sampled again, the sequence

restarts and remains uninterruptible for the following 15 char-

acter clocks.

Table 4. Encoder Bypass Mode (TXMODE[1:0] = LL)

Signal Name

TXD[0] (LSB)

TXD[1]

Bus Weight

10B Name

2⁰

2¹

2²

2³

2⁴

2⁵

2⁶

2⁷

2⁸

2⁹

a^[6]

b

c

d

e

i

TXD[2]

TXD[3]

If parity checking is enabled, the character used to start the

Word Sync Sequence must also have correct ODD parity. This

is true even though the contents of the TXD[7:0] bits do not

directly control the generation of characters during the Word

Sync Sequence. Once the sequence is started, parity is not

checked on the following 15 characters in the Word Sync Se-

quence.

TXD[4]

TXD[5]

TXD[6]

f

TXD[7]

g

h

j

TXCT[0]

TXCT[1] (MSB)

When TXMODE[1] = HIGH (TX modes 6, 7, and 8), the gen-

eration of the Word Sync Sequence becomes an interruptible

operation. In TX Mode 6, this sequence is started as soon as

the TXCT[1:0] = 11 condition is detected on the channel. In

order for the sequence to continue, the TXCT[1:0] inputs must

be sampled as 00 for the remaining 15 characters of the se-

quence.

Note:

6. LSB is shifted out first.

TX Modes 1 and 2—Factory Test Modes

These modes enable specific factory test configurations. They

are not considered normal operating modes of the device. En-

try or configuration into these test modes will not damage the

device.

If at any time a sample period exists where TXCT[1:0] ≠ 00,

the Word Sync Sequence is terminated, and a character rep-

resenting the data and control bits is generated by the Encod-

er. This resets the Word Sync Sequence state machine such

that it will start at the beginning of the sequence at the next

occurrence of TXCT[1:0] = 11.

TX Mode 3—Atomic Word Sync andSCSEL Control of Special

Codes

When configured in TX Mode 3, the SCSEL input is captured

along with the TXCT[1:0] data control inputs. These bits com-

bine to control the interpretation of the TXD[7:0] bits and the

characters generated by them. These bits are interpreted as

listed in Table 5.

When parity checking is enabled and TXMODE[1] = HIGH, all

characters (including those in the middle of a Word Sync Se-

quence) must have correct parity. The detection of a character

with incorrect parity during a Word Sync Sequence (regardless

of the state of TXCT[1:0]) will interrupt that sequence and force

generation of a C0.7 SVS character. Any interruption of the

Word Sync Sequence causes the sequence to terminate.

When TXCKSEL = MID, the transmit channel captures data

into its Input Register using the TXCLK clock.

Document #: 38-02061 Rev. **

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PRELIMINARY

CYP15G0101DXA

When TXCKSEL = LOW, the Input Register for the transmit

channel is clocked by REFCLK ^[1]. When TXCKSEL = HIGH,

the Input Register for the transmit channel is clocked with

TXCLK↑.

back Shift Register (LFSR). This LFSR generates a 511-char-

acter sequence that includes all Data and Special Character

codes, including the explicit violation symbols. This provides a

predictable yet pseudo-random sequence that can be

matched to an identical LFSR in the attached Receiver.

TX Mode 4—Atomic Word Sync and SCSEL Control of

When the BISTLE signal is HIGH, if the BOE[1] input is LOW

the BIST generator in the transmit channel is enabled (and if

BOE[0] = LOW the BIST checker in the receive channel is en-

abled). When BISTLE returns LOW, the values of the BOE[1:0]

signals are captured in the BIST Enable Latch. These values

remain in the BIST Enable Latch until BISTLE is returned high

to open the latch again. A device reset (TRSTZ sampled

LOW), also presets the BIST Enable Latch to disable BIST on

both the transmit and receive channels.

Word Sync Sequence Generation

When configured in TX Mode 4, the SCSEL input is captured

along with the TXCT[1:0] data control inputs. These bits com-

bine to control the interpretation of the TXD[7:0] bits and the

characters generated by them. These bits are interpreted as

listed in Table 6.

Table 6. TX Modes 4 and 7 Encoding

All data and data-control information present at the TXD[7:0]

and TXCT[1:0] inputs are ignored when BIST is active on the

transmit channel. If the receive channel is configured for com-

mon clock operation (RXCKSEL = LOW) each pass is preced-

ed by a 16-character Word Sync Sequence to allow Elasticity

Buffer alignment and management of clock-frequency varia-

tions.

Characters Generated

X

0

1

X

0

1

X

0

1

Encoded data character

K28.5 fill character

Special character code

16-character Word Sync Sequence

Serial Output Drivers

The serial interface Output Drivers use high-performance dif-

ferential CML (Current Mode Logic) to provide source-

matched drivers for the transmission lines. These Serial Driv-

ers accept data from the Transmit Shifter. These outputs have

signal swings equivalent to that of standard PECL drivers, and

are capable of driving AC-coupled optical modules or AC-cou-

pled transmission lines.

TX Mode 4 also supports an Atomic Word Sync Sequence.

Unlike TX Mode 3, this sequence is started when both SCSEL

and TXCT[0] are sampled HIGH. With the exception of the

combination of control bits used to initiate the sequence, the

generation and operation of this Word Sync Sequence is the

same as that documented for TX Mode 3.

When configured for local loopback (LPEN = HIGH), the en-

abled Serial Drivers are configured to drive a static differential

logic-1.

TX Mode 5—Atomic Word Sync, No SCSEL

When configured in TX Mode 5, the SCSEL signal is not used.

The TXCT[1:0] inputs control the characters generated by the

channel. The specific characters generated by these bits are

listed in Table 7.

Each Serial Driver can be enabled or disabled through the

BOE[1:0] inputs, as controlled by the OELE latch-enable sig-

nal. When OELE = HIGH, the signals present on the BOE[1:0]

inputs are passed through the Serial Output Enable latch to

control the Serial Driver. The BOE[1:0] input with OUT1± and

OUT2± driver is listed in Table 8.

Table 7. TX Modes 5 and 8 Encoding

Table 8. Output Enable, BIST, and Receive Channel

Enable Signal Map

Characters Generated

X

0

1

0

1

0

1

Encoded data character

K28.5 fill character

BIST

ReceivePLL

Channel

Enable

Output

Controlled

(OELE)

Channel

Enable

BOE

Special character code

16-character Word Sync Sequence

Input

(BISTLE)

(RXLE)

BOE[1]

BOE[0]

OUT2±

OUT1±

Transmit

Receive

X

Receive

TX Mode 5 also has the capability of generating an Atomic

Word Sync Sequence. For the sequence to be started, the

TXCT[1:0] inputs must both be sampled HIGH. The generation

and operation of this Word Sync Sequence is the same as that

documented for TX Mode 3.

When OELE = HIGH and BOE[x] = HIGH, the associated Se-

rial Driver is enabled to drive any attached transmission line.

When OELE = HIGH and BOE[x] = LOW, the associated driv-

er is disabled and internally configured for minimum power

dissipation. If both Serial Drivers for the channel are disabled,

the internal logic for the channel is also configured for lowest

power operation. When OELE returns LOW, the values

present on the BOE[1:0] inputs are latched in the Output En-

able Latch, and remain there until OELE returns HIGH to open

the latch again. A device reset (TRSTZ sampled LOW) clears

this latch and disables both Serial Drivers.

Transmit BIST

The transmit channel contains an internal pattern generator

that can be used to validate both device and link operation.

This generator is enabled by the BOE[1] signal, as listed in

Table 8 (when the BISTLE latch enable input is HIGH). When

enabled, a register in the transmit channel becomes a signa-

ture pattern generator by logically converting to a Linear Feed-

Document #: 38-02061 Rev. **

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PRELIMINARY

CYP15G0101DXA

Transmit PLL Clock Multiplier

The local loopback input (LPEN) allows the serial transmit data

to be routed internally back to the Clock and Data Recovery

circuit. When configured for local loopback, the transmit Serial

Driver outputs are forced to output a differential logic-1. This

prevents local diagnostic patterns from being broadcast to at-

tached remote receivers.

The Transmit PLL Clock Multiplier accepts a character-rate or

half-character-rate external clock at the REFCLK input, and

multiples that clock by 10 or 20 (as selected by TXRATE) to

generate a bit-rate clock for use by the Transmit Shifter. It also

provides a character-rate clock used by the transmit path.

This clock multiplier PLL can accept a REFCLK input between

20 MHz and 150 MHz, however, this clock range is limited by

the operating mode of the CYP15G0101DXA clock multiplier

(controlled by TXRATE) and by the level on the SPDSEL input.

SPDSEL is a 3-level select^[2](ternary) input that selects one

of three operating ranges for the serial data outputs and inputs.

The operating serial signaling-rate and allowable range of

REFCLK frequencies are listed in Table 9.

Signal Detect / Link Fault

Each selected Line Receiver (i.e., that routed to the Clock and

Data Recovery PLL) is simultaneously monitored for

• analog amplitude

• transition density

• Range Control logic report the received data stream inside

normal frequency range (±200 ppm)

• receive channel enabled.

Table 9. Operating Speed Settings

All of these conditions must be valid for the Signal Detect block

to indicate a valid signal is present. This status is presented on

the LFI (Link Fault Indicator) output which changes synchro-

nous to the selected receive interface clock.

REFCLK

Frequency

(MHz)

Signaling

Rate

(MBaud)

SPDSEL

TXRATE

LOW

1

0

1

0

1

0

reserved

20–40

200–400

400–800

800–1500

Table 10. Analog Amplitude Detect Valid Signal Levels

SDASEL

Typical signal with peak amplitudes above

MID (Open)

HIGH

20–40

LOW

140 mV p-p differential

40–80

MID (Open) 280 mV p-p differential

HIGH 420 mV p-p differential

40–75

80–150

Analog Amplitude

The REFCLK± input is a differential input with each input inter-

nally biased to 1.4V. If the REFCLK+ input is connected to a

TTL, LVTTL, or LVCMOS clock source, the input signal is rec-

ognized when it passes through the internally biased reference

point.

While most signal monitors are based on fixed constants, the

analog amplitude level detection is adjustable to allow opera-

tion with highly attenuated signals, or in high-noise environ-

ments. This adjustment is made through the SDASEL signal,

a 3-level select^[2](ternary) input, which sets the trip point for

the detection of a valid signal at one of three levels, as listed

in Table 10.

When both the REFCLK+ and REFCLK− inputs are connect-

ed, the clock source must be a differential clock. This can be

either a differential LVPECL clock that is DC-or AC-coupled,

or a differential LVTTL or LVCMOS clock.

The Analog Signal Detect monitor is active for the present Line

Receiver, as selected by the INSEL input. When configured for

local loopback (LPEN = HIGH), no Line Receiver is selected,

and the LFI output reports only the receive VCO frequency out-

of-range and transition density status. When local loopback is

active, the Analog Signal Detect monitor is disabled.

By connecting the REFCLK− input to an external voltage

source or resistive voltage divider, it is possible to adjust the

reference point of the REFCLK+ input for alternate logic levels.

When doing so it is necessary to ensure that the 0V-differential

crossing point remains within the parametric range supported

by the input.

Transition Density

The Transition Detection logic checks for the absence of any

transitions spanning greater than six transmission characters

(60 bits). If no transitions are present in the data received (with-

in the referenced period), the Transition Detection logic as-

serts LFI. The LFI output remains asserted until at least one

transition is detected in each of three adjacent received char-

acters.

CYP15G0101DXA Receive Data Path

Serial Line Receivers

Two differential Line Receivers, IN1± and IN2±, are available

for accepting serial data streams. The active Serial Line Re-

ceiver is selected using the INSEL input. Both Serial Line Re-

ceivers have differential inputs, and can accommodate wire

interconnect and filtering losses or transmission line attenua-

tion greater than 16 dB. For normal operation, these inputs

should receive a signal of at least VI_DIFF> 100 mV, or 200 mV

peak-to-peak differential. Each Line Receiver can be DC- or

AC-coupled to +3.3V powered fiber-optic interface modules

(any ECL/PECL logic family, not limited to 100K PECL) or AC-

coupled to +5V powered optical modules. The common-mode

tolerance of accommodates a wide range of signal termination

voltages. Each receiver provides internal DC-restoration, to

the center of the receiver’s common mode range, for AC-cou-

pled signals.

Range Control

The receive-VCO Range-Control Monitor tracks the frequency

of the received signal relative to REFCLK. It also determines

if the receive Clock/Data Recovery circuit (CDR) should align

the receive-VCO clock to the data stream or to the local

REFCLK input. This prevents the receive VCO from tracking

an out-of-specification received signal.

When the Range-Control Monitor indicates that the signaling

rate is within specification, the phase detector in the receive

PLL is configured to track the transitions in the received data

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PRELIMINARY

CYP15G0101DXA

stream. In this mode the LFI output is HIGH (unless one of the

other status monitors indicates that the received signal is out

of specification). If the Range-Control Monitor indicates that

the received data stream signaling-rate is out of specification,

the phase detector is configured to track the local REFCLK

input, and the LFI output is asserted LOW.

• to reduce PLL acquisition time

• andto limitunlockedfrequency excursions oftheCDR VCO

when there is no input data is present at the selected Serial

Line Receiver.

Regardless of the type of signal present, the CDR will attempt

to recover a data bit stream from it. If the frequency of the

recovered data stream is outside the limits set by the Range

Control Monitor, the CDR PLL will track REFCLK instead of the

data stream. When the frequency of the data stream returns

to a valid frequency, the CDR PLL is allowed to track the re-

ceived data stream. The frequency of REFCLK is required to

be within ±200 ppm of the frequency of the clock that drives

the REFCLK input of the remote transmitter to ensure a lock

to the incoming data stream.

The specific trip points for this compare function are listed in

Table 11. Because the compare function operates with two

asynchronous clocks, there is a small uncertainty in the mea-

surement. The switch points are asymmetric to provide hyster-

esis to the operation.

Table 11. Receive Signaling Rate Range Control criteria

Frequency

Difference

For systems using multiple or redundant connections, the LFI

output can be used to select an alternate data stream. When

an LFI indication is detected, external logic can toggle selec-

tion of the IN1± and IN2± inputs through the INSEL input.

When a port switch takes place, it is necessary for the receive

PLL to reacquire the new serial stream and frame to the incom-

ing character boundaries.

Between

Next RX PLL

Tracking

Source

Current RX PLL TransmitCharacter

Tracking Source

Clock & RX VCO

Selected data

stream

<1708 ppm

Data Stream

Indeterminate

REFCLK

1708-1953 ppm

>1953 ppm

(LFI = HIGH)

REFCLK

Deserializer/Framer

<488 ppm

488-732 ppm

>732 ppm

Data Stream

Indeterminate

REFCLK

Each CDR circuit extracts bits from the serial data stream and

clocks these bits into the Shifter/Framer at the bit-clock rate.

When enabled, the Framer examines the data stream looking

for one or more Comma or K28.5 characters at all possible bit

positions. The location of these characters in the data stream

are used to determine the character boundaries of all following

characters.

(LFI = LOW)

Receive Channel Enabled

The CYP15G0101DXA receive channel can be enabled and

disabled through the BOE[0] input, as controlled by the RXLE

latch-enable signal. When RXLE = HIGH, the signal present

on the BOE[0] inputs is passed through the Receive Channel

Enable Latch to control the PLL and logic of the receive chan-

nel. The BOE[1:0] input functions are listed in Table 8.

Framing Character

The CYP15G0101DXA allows selection of either of two com-

binations of framing characters to support requirements of dif-

ferent interfaces. The selection of the framing character is

made through the FRAMCHAR input.

When RXLE = HIGH and BOE[0] = HIGH, the receive channel

is enabled to receive and decode a serial stream from the Line

Receiver. When RXLE = HIGH and BOE[0] = LOW, the re-

ceive channel is disabled and internally configured for mini-

mum power dissipation. When disabled, the channel indicates

a constant LFI output. When RXLE returns LOW, the values

present on the BOE[1:0] inputs are latched in the Receive

Channel Enable Latch, and remain there until RXLE returns

HIGH to opened the latch again.

The specific bit combinations of these framing characters are

listed in Table 12. When the specific bit combination of the

selected framing character is detected by the Framer, the

boundaries of the characters present in the received data

stream are known.

Table 12. Framing Character Selector

Bits detected in Framer

Note: When a disabled receive channel is re-enabled, the

status of the LFI output and data on the parallel outputs may

be indeterminate for up to 10ms.

FRAMCHAR

Character Name

Bits Detected

00111110XX^[7]

or 11000001XX

MID (Open)

Comma+

Comma−

Clock/Data Recovery

HIGH

−K28.5

+K28.5

0011111010 or

1100000101

The extraction of a bit-rate clock and recovery of bits from a

received serial stream is performed by a Clock/Data Recovery

(CDR) block within the receive channel. The clock extraction

function is performed by a high-performance embedded

phase-locked loop (PLL) that tracks the frequency of the tran-

sitions in the incoming bit stream and aligns the phase of the

internal bit-rate clock to the transitions in the serial data

stream.

Note:

7. The standard definition of a Comma contains only seven bits. However,

since all valid Comma characters within the 8B/10B character set also

have the 8th bit as an inversion of the 7th bit, the compare pattern is

extended to a full eight bits to reduce the possibility of a framing error.

Framer

The Framer operates in one of three different modes, as se-

lected by the RFMODE input. In addition, the Framer itself may

be enabled or disabled through the RFEN input. When

RFEN = LOW, the Framer is disabled, and no combination of

bits in a received data stream will alter the character bound-

The CDR accepts a character-rate (bit-rate ÷ 10) or half-char-

acter-rate (bit-rate ÷ 20) reference clock from the REFCLK in-

put. This REFCLK input is used to ensure that the VCO (within

the CDR) is operating at the correct frequency (rather than

some harmonic of the bit-rate)

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PRELIMINARY

CYP15G0101DXA

aries. When RFEN = HIGH, the Framer-mode selected by RF-

MODE is enabled.

codes. This block uses the 10B/8B Decoder patterns in

Table 21 and Table 22 of this data sheet. Valid data characters

are indicated by a 000b bit-combination on the RXST[2:0] sta-

tus bits, and Special Character codes are indicated by a 001b bit-

combination on these same status outputs. Framingcharacters,

invalid patterns, disparity errors, and synchronization status are pre-

sented as alternate combinations of these status bits.

When RFMODE = LOW, the Low-Latency Framer is selected.

This Framer operates by stretching the recovered character

clock until it aligns with the received character boundaries. In

this mode the Framer starts its alignment process on the first

detection of the selected framing character. To reduce the im-

pact on external circuits that make use of a recovered clock,

the clock period is not stretched by more than two bit-periods

in any one clock cycle. When operated with a character-rate

output clock (RXRATE = LOW), the output of properly framed

characters may be delayed by up to nine character-clock cy-

cles from the detection of the selected framing character.

When operated with a half-character-rate output clock

(RXRATE = HIGH), the output of properly framed characters

may be delayed by up to 14 character-clock cycles from the

detection of the selected framing character.

The 10B/8B Decoder operates in two normal modes, and can

also be bypassed. The operating mode for the Decoder is con-

trolled by the DECMODE input.

When DECMODE = LOW, the Decoder is bypassed and raw

10-bit characters are passed to the Output Register. In this

mode, the receive Elasticity Buffers are bypassed, and RXCK-

SEL must be MID. This clock mode generates separate RX-

CLK± outputs for the receive channel.

When DECMODE = MID (or open), the 10-bit transmission

characters are decoded using Table 21 and Table 22. Re-

ceived Special Code characters are decoded using the Cy-

press column of Table 22.

NOTE: When Receive BIST is enabled on a channel, the

Low-Latency Framer must not be enabled. The BIST se-

quence contains an aliased K28.5 framing character, which

would cause the Receiver to update its character bound-

aries incorrectly.

When DECMODE = HIGH, the 10-bit transmission characters

are decoded using Table 21 and Table 22. Received Special

Code characters are decoded using the Alternate column of

Table 22.

When RFMODE = MID (open) the Cypress-mode multi-byte

Framer is selected. The required detection of multiple framing

characters makes the link much more robust to incorrect fram-

ing due to aliased SYNC characters in the data stream. In this

mode, the Framer does not adjust the character clock bound-

ary, but instead aligns the character to the already recovered

character clock. This ensures that the recovered clock does

not contain any significant phase changes or hops during nor-

mal operation or framing, and allows the recovered clock to be

replicated and distributed to other external circuits or compo-

nents using PLL-based clock distribution elements. In this

framing mode the character boundaries are only adjusted if the

selected framing character is detected at least twice within a

span of 50 bits, with both instances on identical 10-bit charac-

ter boundaries.

Receive BIST Operation

The Receiver interface contains an internal pattern generator

that can be used to validate both device and link operation.

This generator is enabled by the BOE[0] signal as listed in

Table 8 (when the BISTLE latch enable input is HIGH). When

enabled, a register in the Receive channel becomes a pattern

generator and checker by logically converting to a Linear

Feedback Shift Register (LFSR). This LFSR generates a 511-

character sequence that includes all Data and Special Char-

acter codes, including the explicit violation symbols. This pro-

vides a predictable yet pseudo-random sequence that can be

matched to an identical LFSR in the attached Transmitter.

When synchronized with the received data stream, the Receiv-

er checks each character in the Decoder with each character

generated by the LFSR and indicates compare errors and

BIST status at the RXST[2:0] bits of the Output Register.

When RFMODE = HIGH, the Alternate-mode multi-byte

Framer is enabled. Like the Cypress-mode multi-byte Framer,

multiple framing characters must be detected before the char-

acter boundary is adjusted. In this mode, the data stream must

contain a minimum of four of the selected framing characters,

received as consecutive characters, on identical 10-bit bound-

aries, before character framing is adjusted.

When the BISTLE signal is HIGH, if the BOE[0] input is LOW

the BIST generator/checker in the Receive channel is enabled

(and if BOE[1] = LOW the BIST generator in the transmit chan-

nel is enabled). When BISTLE returns LOW, the values of the

BOE[1:0] signals are captured in the BIST Enable Latch.

These values remain in the BIST Enable Latch until BISTLE is

returned high to open the latch again. All captured signals in

the BIST Enable Latch are set HIGH (i.e., BIST is disabled)

following a device reset (TRSTZ is sampled LOW).

Framing is enabled when RFEN = HIGH. If RFEN = LOW, the

Framer is disabled. When the Framer is disabled, no changes

are made to the recovered character boundary, regardless of

the presence of framing characters in the data stream.

10B/8B Decoder Block

When BIST is first recognized as being enabled in the Receiv-

er, the LFSR is preset to the BIST-loop start-code of D0.0. This

D0.0 character is sent only once per BIST loop. The status of

the BIST progress and any character mismatches is presented

on the RXST[2:0] status outputs.

The Decoder logic block performs three primary functions:

• decoding the received transmission characters back into

Data and Special Character codes,

• comparing generated BIST patterns with received charac-

ters to permit at-speed link and device testing,

Code rule violations or running disparity errors that occur as

part of the BIST loop do not cause an error indication.

RXST[2:0] indicates 010b or 100b for one character period per

BIST loop to indicate loop completion. This status can be used to

check test pattern progress. These same status values are present-

ed when the Decoder is bypassed and BIST is enabled on the

Receive channel.

• and generation of ODD parity on the decoded characters.

10B/8B Decoder

The framed parallel output of the Deserializer Shifter is passed

to the 10B/8B Decoder where, if the Decoder is enabled

(DECMODE ≠ LOW), it is transformed from a 10-bit transmis-

sion character back to the original Data and Special Character

Document #: 38-02061 Rev. **

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PRELIMINARY

CYP15G0101DXA

The specific status reported by the BIST state machine are

listed in Table 17. These same codes are reported on the re-

ceive status outputs regardless of the state of DECMODE.

Table 13. Receive Operating Modes

RX Mode Operating Mode

The specific patterns checked by each receiver are described

in detail in the Cypress application note “HOTLink Built-In Self-

Test.” The sequence compared by the CYP15G0101DXA is

identical to that in the CY7B933 and CY7C924DX, allowing

interoperable systems to be built when used at compatible se-

rial signaling rates.

Channel Mode RXST Status Reporting

0

1

2

L

M

H

Independent

Status A

Reserved for test

Status B

If the number of invalid characters received ever exceeds the

number of valid characters by 16, the receive BIST state ma-

chine aborts the compare operations and resets the LFSR to

the D0.0 state to look for the start of the BIST sequence again.

Independent

ity Buffer must be able to insert K28.5 characters and delete

framing characters as appropriate.

When the receive paths are configured for common clock op-

eration (RXCKSEL = LOW) each pass must be preceded by a

16-character Word Sync Sequence to allow output buffer

alignment and management of clock frequency variations.

This is automatically generated by the transmitter when its lo-

cal RXCKSEL = LOW.

The insertion of a K28.5 or deletion of a framing character can

occur at any time, however, the actual timing on these inser-

tions and deletions is controlled in part by the how the trans-

mitter sends its data. Insertion of a K28.5 character can only

occur when the receiver has a framing character in the Elas-

ticity Buffer. Likewise, to delete a framing character, one must

also be in the Elasticity Buffer. To prevent an Elasticity Buffer

overflow or underflow in the receive channel, a minimum den-

sity of framing characters must be present in the received data

stream.

The BIST state machine requires the characters to be correctly

framed for it to detect the BIST sequence. If the Low-Latency

Framer is enabled (RFMODE = LOW), the Framer will mis-

align to an aliased SYNC character within the BIST sequence.

If the Alternate-mode Multi-Byte Framer is enabled

(RFMODE = HIGH) and the Receiver outputs are clocked rel-

ative to a recovered clock (RXCKSEL = MID), it is generally

necessary to frame the Receiver before BIST is enabled. If the

Receiver outputs are clocked relative to REFCLK

(RXCKSEL = LOW), the transmitter precedes every 511 char-

acter BIST sequence with a 16-character Word Sync Se-

quence. This sequence will frame the Receiver regardless of

the setting of RFMODE.

Prior to reception of valid data, at least one Word Sync Se-

quence (or that portion of one necessary to center the Elastic-

ity Buffer) must be received to allow the receive Elasticity Buff-

er to be centered. The Elasticity Buffer may also be centered

by a device reset operation initiated through the TRSTZ input,

however, following such an event the CYP15G0101DXA will

normally require a framing event before it will correctly decode

characters.

When RXCKSEL = MID (or open), the received channel Out-

put Register is clocked by the recovered clock. Since no char-

acters may be added or deleted, the receiver Elasticity Buffer

is bypassed.

Receive Elasticity Buffer

The receive channel contains an Elasticity Buffer that is de-

signed to support multiple clocking modes. This buffer allows

data to be read using an Elasticity Buffer read-clock that is

asynchronous in both frequency and phase from the Elasticity

Buffer write clock, or to use a read clock that is frequency

coherent but with uncontrolled phase relative to the Elasticity

Buffer write clock.

Power Control

The CYP15G0101DXA supports user control of the powered

up or down state of the Transmit and Receive channel. The

Receive channel is controlled by the RXLE signal and the val-

ues present on the BOE[1:0] bus. The Transmit channel is

controlled by the OELE signal and the values present on the

BOE[1:0] bus. If either the Transmit or the Receive channel is

not used, then powering down the unused channel will save

power and reduce system heat generation. Controlling system

power dissipation will improve the system performance.

The Elasticity Buffer is a minimum of 10-characters deep, and

supports a 12-bit wide data path. It is capable of supporting a

decoded character, three status bits, and a parity bit for each

character present in the buffer. The write clock for this buffer

is always the recovered clock for the read channel.

The read clock for the Elasticity Buffer may come from one of

two selectable sources. It may be a

Receive Channel

• character-rate REFCLK

• recovered clock from the receive channel

When RXLE = HIGH, the signal on the BOE[0] input directly

controls the power enable for the receive PLL and the analog

circuit. When BOE[0] = HIGH, the Receive channel and its an-

alog circuits are active. When BOE[0] = LOW, the Receive

channel and its analog circuits are powered down. When a

disabled receive channel is re-enabled, the status of the LFI

output and data on the parallel outputs for the Receive channel

may be indeterminate for up to 10 ms.

Receive Modes

The operating mode of the receive path is set through the

RXMODE input. This RXMODE input is only interpreted when

the Decoder is enabled (DECMODE ≠ LOW). These modes

determine the RXST status reporting. The different receive

modes are listed in Table 13.

Transmit Channel

When RXCKSEL = LOW, the Receive channel is clocked by

REFCLK. The RXCLK± and RXCLKC+ outputs presents buff-

ered and delayed forms of REFCLK. In this mode, the receive

Elasticity Buffer is enabled. For REFCLK clocking, the Elastic-

When OELE = HIGH, the signals on the BOE[1:0] inputs

directly control the power enables for the Serial Drivers. When

a BOE[1:0] input is HIGH, the associated Serial Driver is en-

Document #: 38-02061 Rev. **

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PRELIMINARY

CYP15G0101DXA

abled. When a BOE[1:0] input is LOW, the associated Serial

Driver is disabled. When OELE returns LOW, the values

present on the BOE[1:0] inputs are latched in the Output En-

able Latch.

Table 15. Decoder Bypass Mode (DECMODE = LOW)

Signal Name

RXST[2] (LSB)

RXST[1]

RXST[0]

RXD[0]

Bus Weight

10B Name

COMDET

2⁰

2¹

2²

2³

2⁴

2⁵

2⁶

2⁷

2⁸

2⁹

a

b

c

d

e

i

Device Reset State

When the CYP15G0101DXA is reset by assertion of TRSTZ,

both the Transmit Enable and Receive Enable Latches are

cleared, and the BIST Enable Latch is preset. In this state, the

Transmit and Receive channels are disabled, and BIST is dis-

abled.

RXD[1]

RXD[2]

RXD[3]

Following a device reset, it is necessary to enable the transmit

and receive channels for normal operation. This can be done

by sequencing the appropriate values on the BOE[1:0] inputs

while the OELE and RXLE signals are raised and lowered. For

systems that do not require dynamic control of power, or want

the part to power up in a fixed configuration, it is also possible

to strap the RXLE and OELE control signals HIGH to perma-

nently enable their associated latches. Connection of the as-

sociated BOE[1:0] signals HIGH will then enable the Transmit

and Receive channels as soon as the TRSTZ signal is deas-

serted.

RXD[4]

f

RXD[5]

g

h

j

RXD[6]

RXD[7] (MSB)

The COMDET status output operates the same regardless of

the bit combination selected for character framing by the

FRAMCHAR input. It is HIGH when the character in the Output

Register contains the selected framing character at the proper

character boundary, and LOW for all other bit combinations.

Output Bus

When the Low-Latency Framer and half-rate receive port

clocking is also enabled (RFMODE = LOW, RXRATE = HIGH,

and RXCKSEL = MID), the Framer will stretch the recovered

clock to the nearest 20-bit boundary such that the rising edge

of RXCLK+ occurs when COMDET = HIGH in the Output Reg-

ister.

The receive channel presents a 12-signal output bus consist-

ing of

• an 8-bit data bus

• a 3-bit status bus

• a parity bit

When the Cypress or Alternate-mode Framer is enabled and

half-rate receive port clocking is also enabled

(RFMODE ≠ LOW and RXRATE = HIGH), the output clock is

not modified when framing is detected, but a single pipeline

stage may be added or subtracted from the data stream by the

Framer logic such that the rising edge of RXCLK+ occurs

when COMDET = HIGH in the Output Register.

The signals present on this output bus are modified by the

present operating mode of the CYP15G0101DXA as selected

by DECMODE. This mapping is shown in Table 14.

Table 14. Output Register Bit Assignments^[8]

DECMODE = MID

Signal Name

RXST[2] (LSB)

RXST[1]

RXST[0]

RXD[0]

DECMODE = LOW

COMDET

DOUT[0]

or HIGH

RXST[2]

RXST[1]

RXST[0]

RXD[0]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

This adjustment only occurs when the Framer is enabled

(RFEN = HIGH). When the Framer is disabled, the clock

boundaries are not adjusted, and COMDET may be asserted

during the rising edge of RXCLK– (if an odd number of char-

acters were received following the initial framing).

DOUT[1]

DOUT[2]

Parity Generation

RXD[1]

DOUT[3]

In addition to the eleven data and status bits that are present-

ed, an RXOP parity output is also available. This allows the

CYP15G0101DXA to support ODD parity generation. To han-

RXD[2]

DOUT[4]

RXD[3]

DOUT[5]

RXD[4]

DOUT[6]

dle

a

wide range of system environments, the

CYP15G0101DXA supports multiple different forms of parity

generation (in addition to no parity). When the Decoder is en-

abled (DECMODE ≠ LOW), parity can be generated on

RXD[5]

DOUT[7]

RXD[6]

DOUT[8]

RXD[7] (MSB)

DOUT[9]

• the RXD[7:0] character

Note:

• the RXD[7:0] character and RXST[2:0] status

8. The RXOP output is also driven from the Output Register, but its inter-

pretation is under the separate control of PARCTL.

When the Decoder is bypassed (DECMODE = LOW), parity

can be generated on

When the 10B/8B Decoder is bypassed (DECMODE = LOW),

the framed 10-bit character and a single status bit are present-

ed to the receiver Output Register, along with a status output

indicating if the character in the Output Register is one of the

selected framing characters. The bit usage and mapping of the

external signals to the raw 10B transmission character is

shown in Table 15.

• the RXD[7:0] and RXST[1:0] bits

• the RXD[7:0] and RXST[2:0] bits

These modes differ in the number bits which are included in

the parity calculation. For all cases, only ODD parity is provid-

ed which ensures that at least one bit of the data bus is always

a logic-1. Those bits covered by parity generation are listed in

Table 16.

Document #: 38-02061 Rev. **

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PRELIMINARY

CYP15G0101DXA

Table 16. Output Register Parity Generation

Receive Parity Generate Mode (PARCTL)

Receive Status Bits

When the 10B/8B Decoder is enabled (DECMODE ≠ LOW),

each character presented at the Output Register includes

three associated status bits. These bits are used to identify

LOW^[9]

MID

HIGH

Signal

Name

DECMODE

• if the contents of the data bus are valid,

• the type of character present,

• the state of receive BIST operations (regardless of the state

of DECMODE),

= LOW

≠ LOW

RXST[2]

RXST[1]

RXST[0]

RXD[0]

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

X^[10]

X

• character violations.

X

These conditions normally overlap; e.g., a valid data character

received with incorrect running disparity is not reported as a

valid data character. It is instead reported as a Decoder viola-

tion of some specific type. This implies a hierarchy or priority

level to the various status bit combinations. The hierarchy and

value of each status is listed in Table 17.

X

Within these status decodes, there are three forms of status

reporting. The two normal or data status reporting modes

(Type A and Type B) are selectable through the RXMODE in-

put. These status types allow compatibility with legacy sys-

tems, while allowing full reporting in new systems. The third

status type is used for reporting receive BIST status and

progress.

X

Notes:

9. Receive path parity output drivers (RXOPx) are disabled (High-Z) when

PARCTL = LOW

BIST Status State Machine

10. When the Decoder is bypassed (DECMODE = LOW) and BIST is not

enabled (Receive BIST Latch output is HIGH), RXSTx[2] is driven to a

logic-0, except when the character in the output buffer is a framing char-

acter.

When the receive path is enabled to look for and compare the

received data stream with the BIST pattern, the RXST[2:0] bits

identify the present state of the BIST compare operation.

The BIST state machine has multiple states, as shown in

Figure 2 and Table 17. When the receive PLL detects an out-

of-lock condition, the BIST state is forced to the Start-of-BIST

state, regardless of the present state of the BIST state ma-

chine. If the number of detected errors ever exceeds the num-

ber of valid matches by greater than 16, the state machine is

forced to the WAIT_FOR_BIST state where it monitors the in-

terface for the first character (D0.0) of the next BIST se-

quence. Also, if the Elasticity Buffer ever hits and overflow/un-

derflow condition, the status is forced to the BIST_START until

the buffer is re-centered (approximately nine character peri-

ods).

Parity generation is enabled through the 3-level select

PARCTL input. When PARCTL = LOW, parity checking is dis-

abled, and the RXOP output is disabled (High-Z).

When PARCTL = MID (open) and the Decoder is enabled

(DECMODE ≠ LOW), ODD parity is generated for the received

and decoded character in the RXD[7:0] signals and is present-

ed on the RXOP output.

When PARCTL = MID (open) and the Decoder is bypassed

(DECMODE = LOW), ODD parity is generated for the received

and decoded character in the RXD[7:0] and RXST[1:0] bit po-

sitions.

When PARCTL = HIGH, ODD parity is generated for the

TXD[7:0] and the RXST[2:0] status bits.

To ensure compatibility between the source and destination

systems when operating in BIST, the sending and receiving

ends of the BIST sequence must use the same clock set-up

(RXCKSEL = MID or RXCKSEL = LOW).

When the Output Register clocking is such that the decoded

character is passed through the receive Elasticity Buffer prior

to the addition of the RXST[2:0] status bits, the output parity

calculation becomes a two-step process. The first parity calcu-

lation takes place as soon as the character is framed and de-

coded. This generates proper parity for the data portion of the

decoded character which is then written to the Elasticity Buffer.

If the parity calculation also includes the RXST[2:0] status bits

(PARCTL = HIGH), a second parity calculation is made prior

to loading the data and status bits into the receive Output Reg-

ister. This is necessary because the status bits with a charac-

ter in the Output Register are not necessarily determined until

after the character is read from the receive Elasticity Buffer.

JTAG Support

The CYP15G0101DXA contains a JTAG port to allow system

level diagnosis of device interconnect. Of the available JTAG

modes, only boundary scan is supported. This capability is

present only on the LVTTL inputs and outputs and the REF-

CLK± clock input. The high-speed serial inputs and outputs are

not part of the JTAG test chain.

JTAG ID

The JTAG device ID for the CYP15G0101DXA is ‘0C800069’x.

This second parity calculation is based only on the content of

the status bits, and the singular parity bit associated with the

character read from the Elasticity Buffer.

3-Level Select Inputs

Each 3-Level select inputs reports as two bits in the scan reg-

ister. These bits report the LOW, MID, and HIGH state of the

associated input as 00, 10, and 11 respectively.

Document #: 38-02061 Rev. **

Page 20 of 40

PRELIMINARY

CYP15G0101DXA

Table 17. Receive Character Status Bits

Description

Receive BIST Status

(Receive BIST = Enabled)

RXST[2:0] Priority Type-A Status

Type-B Status

000

7

Normal Character Received. The valid Data character on the output BIST Data Compare. Charac-

bus meets all the formatting requirements of Data characters listed in ter compared correctly

Table 21.

001

7

Special Code Detected. The valid special character on the output bus BIST Command Compare.

meets all the formatting requirements of the Special Code characters Character compared correctly

listed in Table 22, but is not the presently selected framing character or

a Decoder violation indication.

010

011

2

5

Receive Elasticity Buffer Under- RESERVED

run/Overrun Error. The receive

buffer was not able to add/drop a

K28.5 or framing character.

BIST Last Good. Last Charac-

ter of BIST sequence detected

and valid.

Framing Character detected. This indicates that a character matching

the patterns identified as a framing character (as selected by FRAM-

CHAR) was detected. The decoded value of this character is present in

the output bus.

100

101

4

1

Codeword Violation. The character on the output bus is a C0.7. This BIST Last Bad. Last Character

indicates that the received character cannot be decoded into any valid of BIST sequence detected in-

character.

valid.

Loss of Sync. The character on Loss of Sync. The character on BIST Start. Receive BIST is en-

the bus is invalid, due to an event the bus is invalid, due to an event abled on this channel, but char-

that has caused the receive chan- that has caused the receive chan- acter compares have not yet

nels to lose synchronization. This nels to lose synchronization. This commenced. This also indi-

indicates a PLL Out of Lock condi- indicates a loss of character fram- cates a PLL Out of Lock condi-

tion.

ing. Also used to indicate receive tion, and Elasticity Buffer over-

Elasticity Buffer underflow/overflow flow/underflow conditions.

errors.

110

111

6

3

Running Disparity Error. The character on the output bus is a C4.7, BIST Error. While comparing

C1.7, or C2.7.

characters, a mismatch was

found in one or more of the de-

coded character bits.

RESERVED

BIST Wait. The receiver is com-

paring characters. but has not

yet found the start of BIST char-

acter to enable the LFSR.

Document #: 38-02061 Rev. **

Page 21 of 40

PRELIMINARY

CYP15G0101DXA

Monitor Data

Receive BIST

Received

Detected LOW

RXST =

BIST_START (101)

RX PLL

Out of Lock

RXST =

BIST_START (101)

RXST =

BIST_WAIT (111)

Elasticity

Buffer Error

Yes

Start of

BIST Detected

No

Yes, RXST = BIST_DATA_COMPARE (000)

OR BIST_COMMAND_COMPARE(001)

Compare

Next Character

RXST =

Mismatch

Match

BIST_COMMAND_COMPARE (001)

Command

Data or

Auto-Abort

Command

Condition

Yes

RXST =

BIST_DATA_COMPARE (000)

No

Data

End-of-BIST

State

End-of-BIST

State

No

Yes, RXST =

BIST_LAST_BAD (100)

Yes, RXST =

BIST_LAST_GOOD (010)

No, RXST =

BIST_ERROR (110)

Figure 2. Receive BIST State Machine

Document #: 38-02061 Rev. **

Page 22 of 40

PRELIMINARY

CYP15G0101DXA

DC Input Voltage ..................................... –0.5V to V_CC+0.5V

Maximum Ratings

Static Discharge Voltage...............................................> 2000 V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current...........................................................> 200 mA

Storage Temperature ..................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Ambient

Supply Voltage to Ground Potential............... –0.5V to +3.8V

Range

Commercial

Industrial

Temperature

0°C to +70°C

–40°C to +85°C

V_CC

DC Voltage Applied to LVTTL Outputs

in High-Z State .......................................–0.5V to V_CC+ 0.5V

+3.3V + 5%

Output Current into LVTTL Outputs (LOW)..................60 mA

CYP15G0101DXA DC Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

Max.

Unit

LVTTL Compatible Outputs

V_OHT

V_OLT

I_OST

I_OZL

Output HIGH Voltage

Output LOW Voltage

I_OH= −4 mA, V_CC= Min.

I_OL= 4 mA, V_CC= Min.

V_OUT= 0V ^[11]

2.4

0

V_CC

0.4

−15

20

V

Output Short Circuit Current

−50

−20

mA

µA

High-Z Output Leakage Current

LVTTL Compatible Inputs

V_IHT

V_ILT

I_IHT

Input HIGH Voltage

2.0

V_CC+ 0.3

0.8

V

Input LOW Voltage

Input HIGH Current

−0.5

V

REFCLK Input, V_IN= V_CC

Other Inputs, V_IN= V_CC

REFCLK Input, V_IN= 0.0V

Other Inputs, V_IN= 0.0V

1.5

mA

µA

mA

µA

+40

I_ILT

Input LOW Current

−1.5

−40

I_IHPDT

I_ILPUT

Input HIGH Current with internal pull-down V_IN= V_CC

+200

−200

Input LOW Current with internal pull-up

V_IN= 0.0V

LVDIFF Inputs: REFCLK±

[12]

V_DIFF

Input Differential Voltage

400

1.2

0.0

1.0

V_CC

mV

V

V_IHHP

Highest Input HIGH Voltage

Lowest Input LOW voltage

Common Mode Range

V_ILLP

V_CC/ 2

V

[13]

V_COMREF

V

_CC− 1.2

V

3-Level Inputs

V_IHH

V_IMM

V_ILL

I_IHH

Three-Level Input HIGH Voltage

Three-Level Input MID Voltage

Three-Level Input LOW Voltage

Input HIGH Current

Min. < V_CC< Max.

V_IN= V_CC

0.87 * V_CC

V_CC

V

0.47 * V_CC0.53 * V_CC

0.0

0.13 * V_CC

200

V

µA

I_IMM

I_ILL

Input MID current

V_IN= V_CC/ 2

−50

50

Input LOW current

V_IN= GND

−200

Differential CML Serial Outputs: OUT1±, OUT2±

V_OHC

Output HIGH Voltage

(V_CCreferenced)

100Ω differential load

150Ω differential load

100Ω differential load

150Ω differential load

V

_CC− 0.5

_CC− 1.1

V

_CC− 0.2

_CC− 0.7

V

V_OLC

Output LOW Voltage

(V_CCreferenced)

V

Notes:

11. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

12. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when

the true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.

13. The common mode range defines the allowable range of REFCLK+ and REFCLK− when REFCLK+ = REFCLK−. This marks the zero-crossing between the

true and complement inputs as the signal switches between a logic-1 and a logic-0.

Document #: 38-02061 Rev. **

Page 23 of 40

PRELIMINARY

CYP15G0101DXA

CYP15G0101DXA DC Electrical Characteristics Over the Operating Range (continued)

Parameter

Description

Test Conditions

100Ω differential load

Min.

450

560

Max.

800

Unit

mV

V_ODIF

Output Differential Voltage

|(OUT+) − (OUT−)|

150Ω differential load

1000

mV

Differential Serial Line Receiver Inputs: IN1±, IN2±

[12]

V_DIFFS

V_IHE

V_ILE

I_IHE

Input Differential Voltage |(IN+) − (IN−)|

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

100

1200

V_CC

mV

V

_CC− 2.0

V

V_IN= V_IHEMax.

V_IN= V_ILEMin.

1350

+3.1

µA

V

I_ILE

Input LOW Current

−700

[14]

V_COM

Common mode Input range

((V_CC− 2.0) + 0.05) Min.,

(Min. V_CC− 0.05) Max.

+1.25

Miscellaneous

Typ.

Max.

305

[15]

I_CC

Power Supply Current

REFCLK= Commercial

mA

Max.

Industrial

TBD

[16]

I_CC

Typ Power Supply Current

REFCLK=

125 MHz

260

Capacitance^[17]

Parameter

C_INTTL

Description

TTL Input Capacitance

PECL input Capacitance

Test Conditions

T_A= 25°C, f₀= 1 MHz, V_CC= 3.3V

Max.

Unit

7

4

pF

C_INPECL

AC Test Loads and Waveforms

3.3V

C

R = 100Ω

L

R

L

R1

R2

C < 5 pF

R1 = 590Ω

R2 = 435Ω

L

(Includes fixture and

probe capacitance)

(b) CML Output Test Load^{Note 18}

C

L

C ≤ 7 pF

(Includes fixture and

probe capacitance)

(a) LVTTL Output Test Load ^{Note 18}

V

3.0V

IHE

V

IHE

2.0V

0.8V

2.0V

0.8V

80%

V

= 1.4V

V

= 1.4V

th

20%

≤ 270 ps

GND

ILE

V

ILE

≤ 270 ps

≤ 1 ns

(c) LVTTL Input Test Waveform ^{Note 19}

(d) CML/LVPECL Input Test Waveform

Notes:

14. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and

complement inputs as the signal switches between a logic-1 and a logic-0.

15. Maximum I_CCis measured with V_CC= MAX, RFEN = LOW, TA = 25°C, with all Serial Line Drivers enabled, sending a constant alternating 01 pattern, and

outputs unloaded.

16. Typical I_CCis measured under similar conditions except with V_CC= 3.3V, TA = 25°C, RFEN = LOW, with one Serial Line Driver sending a continuous

alternating 01 pattern and parallel outputs unloaded.

17. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

18. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.

19. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses this threshold voltage.

Document #: 38-02061 Rev. **

Page 24 of 40

PRELIMINARY

CYP15G0101DXA

CYP15G0101DXA Transmitter LVTTL Switching Characteristics Over the Operating Range

Parameter

f_TS

Description

TXCLK Clock Cycle Frequency

Min.

20

Max

150

50

Unit

MHz

ns

t_TXCLK

TXCLK Period

6.66

2.2

[17]

t_TXCLKH

TXCLK HIGH Time

ns

[17]

t_TXCLKL

TXCLK LOW Time

2.2

ns

[17, 20, 21]

t_TXCLKR

t_TXCLKF

t_TXDS

TXCLK Rise Time

0.3

1.7

ns

[17, 20, 21]

TXCLK Fall Time

0.3

ns

Transmit Data Set-up Time to TXCLK↑ (TXCKSEL ≠ LOW)

Transmit Data Hold Time from TXCLK↑ (TXCKSEL ≠ LOW)

TXCLKO Clock Cycle Frequency (= 1x or 2x REFCLK Frequency)

TXCLKO Period

1.7

ns

t_TXDH

f_TOS

0.8

ns

20

150

50

MHz

ns

t_TXCLKO

6.66

–1.0

–0.0

t_TXCLKOD+

t_TXCLKOD–

TXCLKO+ Duty Cycle with 65% HIGH time

TXCLKO− Duty Cycle with 35% HIGH time

+0.0

+1.0

ns

CYP15G0101DXA Receiver LVTTL Switching Characteristics Over the Operating Range

Parameter

f_RS

t_RXCLKP

t_RXCLKH

Description

RXCLK Clock Output Frequency

Min.

10

Max.

150

100

26.5

51

Unit

MHz

ns

RXCLK Period

6.66

RXCLK HIGH Time (RXRATE = LOW)

RXCLK HIGH Time (RXRATE = HIGH)

RXCLK LOW Time (RXRATE = LOW)

RXCLK LOW Time (RXRATE = HIGH)

RXCLK Duty Cycle centered at 50%

RXCLK Rise Time

2.33^[17]

ns

5.20

ns

t_RXCLKL

2.33^[17]

5.66

26

ns

51

ns

t_RXCLKD

−1.0

+1.0

1.2

ns

[17]

t_RXCLKR

0.3

ns

[17]

t_RXCLKF

RXCLK Fall Time

0.3

1.2

ns

[22]

t_RXDV–

Status and Data Valid Time From RXCLK (RXCKSEL = MID)

5UI − 1.5

–1.5

ns

Status and Data Valid Time From RXCLK (HALF RATE RECOVERED

CLOCK)

ns

[22]

t_RXDV+

Status and Data Invalid Time From RXCLK (RXCKSEL = MID)

5UI − 1.8

–1.5

ns

Status and Data Invalid Time From RXCLKx (HALF RATE RECOVERED

CLOCK)

Notes:

20. The ratio of rise time to falling time must not vary by greater than 2:1.

21. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.

22. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.

Document #: 38-02061 Rev. **

Page 25 of 40

PRELIMINARY

CYP15G0101DXA

CYP15G0101DXA REFCLK Switching Characteristics Over the Operating Range

Parameter

f_REF

t_REFCLK

t_REFH

Description

Min.

20

Max.

150

50

Unit

MHz

ns

%

REFCLK Clock Frequency

REFCLK Period

6.6

REFCLK HIGH Time (TXRATE = HIGH)

5.9

REFCLK HIGH Time (TXRATE = LOW)

2.9^[17]

t_REFL

REFCLK LOW Time (TXRATE = HIGH)

5.9

REFCLK LOW Time (TXRATE = LOW)

2.9^[17]

30

[23]

t_REFD

REFCLK Duty Cycle

70

2

[17, 20, 21]

t_REFR

REFCLK Rise Time (20%-80%)

ns

%

[17, 20, 21]

t_REFF

REFCLK Fall Time (20%-80%)

2

t_TREFDS

Transmit Data or TXRST Set-up Time to REFCLK (TXCKSEL = LOW)

Transmit Data or TXRST Hold Time from REFCLK (TXCKSEL = LOW)

Receive Data Access Time from REFCLK (RXCKSEL = LOW)

Receive Data Valid Time from REFCLK (RXCKSEL = LOW)

Receive Data Access Time from RXCLK (RXCKSEL = LOW)

Receive Data Valid Time from RXCLK (RXCKSEL = LOW)

Receive Data Access Time from RXCLK (RXCKSEL = LOW)

Receive Data Valid Time from RXCLK (RXCKSEL = LOW)

REFCLK Frequency Referenced to Received Clock Period^[24]

1.7

0.8

t_TREFDH

t_RREFDA

t_RREFDV

t_RREFADV–

t_RREFADV+

t_RREFCDV–

t_RREFCDV+

t_REFRX

9.5

4.0

10UI – 4.7

1.0

10UI – 4.3

0.2

−0.02

+0.02

CYP15G0101DXA Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range

Parameter

t_B

t_RISE

Description

Condition

Min.

5000

50

Max.

660

Unit

ps

UI

Bit Time

[17]

CML Output Rise Time 20%-80% (CML Test Load)

CML Output Fall Time 80%-20% (CML Test Load)

SPDSEL = HIGH

SPDSEL = MID

SPDSEL = LOW

SPDSEL = HIGH

SPDSEL = MID

SPDSEL = LOW

0.2−1.5 Gbps

270

100

200

50

500

1000

270

[17]

t_FALL

100

200

500

1000

TBD

[17, 25, 27]

[17, 26, 27]

t_DJ

t_RJ

Deterministic Jitter (peak-peak)

Random Jitter (σ)

0.2−1.5 Gbps

ps

ns

t_TXLOCK

Transmit PLL Lock to REFCLK

TBD

Notes:

23. The duty cycle specification is a simultaneous condition with the t_REFHand t_REFLparameters. This means that at faster character rates the REFCLK duty

cycle cannot be as large as 30%-70%,

24. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.

REFCLK must be within ±200 PPM (±0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a ±100-PPM crystal.

25. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the crosspoint of the differential outputs over the operating range.

26. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the

operating range.

27. Total jitter is calculated at an assumed BER of 1E −12. Hence: Total Jitter (t_J) = (t_RJ* 14) + t_DJ

.

Document #: 38-02061 Rev. **

Page 26 of 40

PRELIMINARY

CYP15G0101DXA

CYP15G0101DXA Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range

Parameter

Description

Receive PLL lock to input data stream (cold start)

Receive PLL lock to input data stream

Receive PLL Unlock Rate

Min.

Max.

10

Unit

ms

UI

t_RXLOCK

2500

TBD

t_RXUNLOCK

t_SA

TBD

ns

Static Alignment^{[17, 28]}

ps

t_jtol

Jitter Tolerance^{[17, 29, 30, 31]}

UI

Notes:

28. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in

3,000 nominal transitions until a character error occurs.

29. Receiver UI (Unit Interval) iscalculatedas1/(f_REF* 20)(whenRXRATE = HIGH)or1/(f_REF* 10) (whenRXRATE = LOW)if no data is being received, or 1/(f_REF* 20)

(when RXRATE = HIGH) or 1/(f_REF* 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t_B.

30. All measurements were done using a CJTPAT.

31. Measured at a datarate of 1.25Gbps.

Document #: 38-02061 Rev. **

Page 27 of 40

PRELIMINARY

CYP15G0101DXA

CYP15G0101DXA HOTLink II Transmitter Switching Waveforms

Transmit Interface

Write Timing

t_TXCLK

TXCKSEL ≠ LOW

t_TXCLKH

t_TXCLKL

TXCLKx

t_TXDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t_TXDH

Transmit Interface

Write Timing

TXCKSEL = LOW

TXRATE = LOW

t_REFCLK

t_REFH

t_REFL

REFCLK

t_TREFDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t_TREFDH

Transmit Interface

Write Timing

TXCKSEL = LOW

TXRATE = HIGH

t_REFCLK

t_REFH

t_REFL

Note 32

REFCLK

t_TREFDS

TXD[7:0],

TXCT[1:0],

TXOP,

SCSEL

t_TREFDH

Transmit Interface

TXCLKO Timing

TXCKSEL = LOW

TXRATE = HIGH

t

REFCLK

t

t_REFL

REFH

REFCLK

t

TXCLKO

Note 34

t_TXCLKOD+

t_TXCLKOD

–

Note 33

TXCLKO

Note:

32. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL = LOW),

data is captured using both the rising and falling edges of REFCLK.

33. The TXCLKO output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLK.

34. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.

Document #: 38-02061 Rev. **

Page 28 of 40

PRELIMINARY

CYP15G0101DXA

CYP15G0101DXA HOTLink II Transmitter Switching Waveforms (continued)

Transmit Interface

TXCLKO Timing

TXCKSEL = LOW

TXRATE = LOW

t_REFCLK

t_REFH

t_REFL

Note 33

REFCLK

TXCLKO

t_TXCLKO

t_TXCLKOD+

Note 34

t_TXCLKOD

–

Switching Waveforms for the CYP15G0101DXA HOTLink II Receiver

Receive Interface

t_REFCLK

Read Timing

RXCKSEL = LOW

RXRATE = LOW

t_REFH

t_REFL

REFCLK

t_RREFDV

t_RREFDA

RXD[7:0],

RXST[2:0],

RXOP

t_REFADV+

t_REFCDV+

t_REFADV

–

t_REFCDV

–

Note 35

RXCLK

RXCLKC

Receive Interface

Read Timing

RXCKSEL = LOW

TXRATE = HIGH

t_REFCLK

t_REFH

t_REFL

REFCLK

t_RREFDA

t_RREFDV

RXD[7:0],

RXST[2:0],

RXOP

t_REFADV+

t_REFCDV+

t_REFADV

–

t_REFCDV

Note 35

Note 36

RXCLK

RXCLKC

Note:

35. RXCLK and RXCLKC are a delayed in phase from REFCLK, and are different in phase from each other.

36. When operated with a half-rate REFCLK, the setup and hold specifications for data relative to RXCLK and RXCLKC are relative to both rising and falling

edges of the clock output

Document #: 38-02061 Rev. **

Page 29 of 40

PRELIMINARY

CYP15G0101DXA

Switching Waveforms for the CYP15G0101DXA HOTLink II Receiver (continued)

Receive Interface

t_RXCLKP

Read Timing

RXCKSEL = MID

RXRATE = LOW

t_RXCLKH

t_RXCLKL

RXCLK+

RXCLK–

t_RXDV

–

RXD[7:0],

RXST[2:0],

RXOP

t_RXDV+

Receive Interface

Read Timing

RXCKSEL = MID

RXRATE = HIGH

t_RXCLKP

t_RXCLKH

t_RXCLKL

RXCLK+

RXCLK–

t_RXDV

–

RXD[7:0],

RXST[2:0],

RXOP

t_RXDV+

Static Alignment

t_B/2 – t_SA

INxy±

SAMPLE WINDOW

Document #: 38-02061 Rev. **

Page 30 of 40

PRELIMINARY

CYP15G0101DXA

Table 18. Package Coordinate Signal Allocation

Ball

ID

Ball

ID

Ball

ID

Signal Name

VCC

Signal Type

POWER

Signal Name

GND

Signal Type

GROUND

Signal Name

Signal Type

LVTTL OUT

LVTTL IN

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

F1

G9

G10

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

J1

TXCLKO+

TXCLKO–

RXD[0]

RXD[2]

RXD[6]

LFI

IN2+

CML IN

GND

GROUND

VCC

POWER

GND

GROUND

OUT2–

RXMODE

TXMODE[1]

IN1+

CML OUT

TMS

LVTTL IN PU

3-LEVEL SEL

LVTTL IN PU

GROUND

3-LEVEL SEL

CML IN

TRSTZ

TDI

BISTLE

DECMODE

OELE

TXCT[1]

TXD[6]

TXD[3]

TXCLK

TXRST

#NC

VCC

POWER

LVTTL IN

OUT1–

VCC

CML OUT

LVTTL IN

POWER

GND

LVTTL IN PD

LVTTL IN PU

NO CONNECT

POWER

VCC

POWER

GND

GROUND

IN2–

CML IN

GND

GROUND

TDO

LVTTL 3-S OUT

CML OUT

GND

GROUND

VCC

OUT2+

TXRATE

TXMODE[0]

IN1–

TCLK

LVTTL IN PD

3-LEVEL SEL

LVTTL OUT

GROUND

J2

RXD[3]

RXD[7]

RXCLK–

TXCT[0]

TXD[5]

TXD[2]

TXD[0]

#NC

LVTTL OUT

LVTTL IN

LVTTL IN PD

3-LEVEL SEL

CML IN

RXCKSEL

TXCKSEL

RXST[2]

RXST[1]

RXST[0]

GND

J3

J4

J5

#NC

NO CONNECT

CML OUT

F2

J6

LVTTL IN

OUT1+

VCC

F3

J7

LVTTL IN

POWER

F4

J8

LVTTL IN

RFEN

LVTTL IN PD

LVTTL IN PU

LVTTL OUT

LVTTL IN PD

3-LEVEL SEL

LVTTL IN

F5

GND

GROUND

J9

NO CONNECT

POWER

LPEN

F6

GND

GROUND

J10

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

VCC

RXLE

F7

GND

GROUND

VCC

POWER

RXCLKC+

RXRATE

SDASEL

SPDSEL

PARCTL

RFMODE

INSEL

F8

TXPER

REFCLK–

REFCLK+

RXOP

RXD[1]

RXD[5]

GND

LVTTL OUT

PECL IN

RXD[4]

VCC

LVTTL OUT

POWER

F9

F10

G1

G2

G3

G4

G5

G6

G7

G8

PECL IN

RXCLK+

TXD[7]

TXD[4]

TXD[1]

VCC

LVTTL OUT

LVTTL IN

LVTTL 3-S OUT

LVTTL OUT

GROUND

LVTTL IN

POWER

BOE[0]

BOE[1]

FRAMCHAR

GND

LVTTL IN PU

3-LEVEL SEL

GROUND

GND

GROUND

SCSEL

VCC

LVTTL IN PD

POWER

GND

GROUND

GND

GROUND

TXOP

LVTTL IN PU

NOTE: #NC = DO NOT CONNECT

Document #: 38-02061 Rev. **

Page 31 of 40

PRELIMINARY

CYP15G0101DXA

the bits E, D, C, B, and A in that order, and the y is the decimal value

of the binary number composed of the bits H, G, and F in that order.

When c is set to K, xx and y are derived by comparing the encoded

bit patterns of the Special Character to those patterns derived from

encoded Valid Data bytes and selecting the names of the patterns

most similar to the encoded bit patterns of the Special Character.

X3.230 Codes and Notation Conventions

Information to be transmitted over a serial link is encoded eight

bits at a time into a 10-bit Transmission Character and then

sent serially, bit by bit. Information received over a serial link

is collected ten bits at a time, and those Transmission Charac-

ters that are used for data characters are decoded into the

correct eight-bit codes. The 10-bit Transmission Code sup-

ports all 256 8-bit combinations. Some of the remaining Trans-

mission Characters (Special Characters) are used for func-

tions other than data transmission.

Under the above conventions, the Transmission Character

used for the examples above, is referred to by the name D5.2.

The Special Character K29.7 is so named because the first six

bits (abcdei) of this character make up a bit pattern similar to

that resulting from the encoding of the unencoded 11101 pat-

tern (29), and because the second four bits (fghj) make up a

bit pattern similar to that resulting from the encoding of the

unencoded 111 pattern (7).

The primary use of a Transmission Code is to improve the

transmission characteristics of a serial link. The encoding de-

fined by the Transmission Code ensures that sufficient transi-

tions are present in the serial bit stream to make clock recov-

ery possible at the Receiver. Such encoding also greatly

increases the likelihood of detecting any single or multiple bit

errors that may occur during transmission and reception of

information. In addition, some Special Characters of the

Transmission Code selected by Fibre Channel Standard con-

tain a distinct and easily recognizable bit pattern that assists

the receiver in achieving character alignment on the incoming

bit stream.

NOTE: This definition of the 10-bit Transmission Code is

based on the following references, which describe the

same 10-bit transmission code.

A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-

tioned-Block, 8B/10B Transmission Code” IBM Journal of Re-

search and Development, 27, No. 5: 440-451 (September, 1983).

U.S. Patent 4,486,739. Peter A. Franaszek and Albert X. Wid-

mer. “Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned

Block Transmission Code” (December 4, 1984).

Notation Conventions

Fibre Channel Physical and Signaling Interface (ANS X3.230-

1994 ANSI FC-PH Standard).

The documentation for the 8B/10B Transmission Code uses

letter notation for the bits in an 8-bit byte. Fibre Channel Stan-

dard notation uses a bit notation of A, B, C, D, E, F, G, H for

the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d,

e, i, f, g, h, j for encoded 10-bit data. There is a correspon-

dence between bit A and bit a, B and b, C and c, D and d, E

and e, F and f, G and g, and H and h. Bits i and j are derived,

respectively, from (A,B,C,D,E) and (F,G,H).

IBM Enterprise Systems Architecture/390 ESCON I/O Inter-

face (document number SA22-7202).

8B/10B Transmission Code

The following information describes how the tables are used

for both generating valid Transmission Characters (encoding)

and checking the validity of received Transmission Characters

(decoding). It also specifies the ordering rules to be followed

when transmitting the bits within a character and the charac-

ters within any higher-level constructs specified by a standard.

The bit labeled A in the description of the 8B/10B Transmission

Code corresponds to bit 0 in the numbering scheme of the FC-

2 specification, B corresponds to bit 1, as shown below.

FC-2 bit designation—

HOTLink D/Q designation— 7

8B/10B bit designation—

7

6

G F

5

4

E

3

D

2

C

1

B

0

A

Transmission Order

H

Within the definition of the 8B/10B Transmission Code, the bit

positions of the Transmission Characters are labeled a, b, c,

d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c,

d, e, i, f, g, h, and j in that order.

To clarify this correspondence, the following example shows

the conversion from an FC-2 Valid Data Byte to a Transmission

Character.

FC-2 45H

Note that bit i is transmitted between bit e and bit f, rather than

in alphabetical order.

Bits: 7654 3210

0100 0101

Valid and Invalid Transmission Characters

Converted to 8B/10B notation, note that the order of bits has

been reversed):

The following tables define the valid Data Characters and valid

Special Characters (K characters), respectively. The tables

are used for both generating valid Transmission Characters

and checking the validity of received Transmission Charac-

ters. In the tables, each Valid-Data-byte or Special-Character-

code entry has two columns that represent two Transmission

Characters. The two columns correspond to the current value

of the running disparity. Running disparity is a binary parame-

ter with either a negative (–) or positive (+) value.

Data Byte Name D5.2

Bits: ABCDE FGH

10100 010

Translated to a transmission Character in the 8B/10B Trans-

mission Code:

Bits: abcdei fghj

101001 0101

After powering on, the Transmitter may assume either a posi-

tive or negative value for its initial running disparity. Upon

transmission of any Transmission Character, the transmitter

will select the proper version of the Transmission Character

based on the current running disparity value, and the Trans-

mitter calculates a new value for its running disparity based on

the contents of the transmitted character. Special Character

Each valid Transmission Character of the 8B/10B Transmis-

sion Code has been given a name using the following conven-

tion: cxx.y, where c is used to show whether the Transmission

Character is a Data Character (c is set to D, and SC/D = LOW)

or a Special Character (c is set to K, and SC/D = HIGH). When c is

set to D, xx is the decimal value of the binary number composed of

Document #: 38-02061 Rev. **

Page 32 of 40

PRELIMINARY

CYP15G0101DXA

codes C1.7 and C2.7 can be used to force the transmission of

a specific Special Character with a specific running disparity

as required for some special sequences in X3.230.

byte or Special Character byte to be encoded and transmitted.

Table 19 shows naming notations and examples of valid transmis-

sion characters.

After powering on, the Receiver may assume either a positive

or negative value for its initial running disparity. Upon reception

of any Transmission Character, the Receiver decides whether

the Transmission Character is valid or invalid according to the

following rules and tables and calculates a new value for its

Running Disparity based on the contents of the received char-

acter.

Use of the Tables for Checking the Validity of Received

Transmission Characters

The column corresponding to the current value of the Receiv-

er’s running disparity is searched for the received Transmis-

sion Character. If the received Transmission Character is

found in the proper column, then the Transmission Character

is valid and the Data byte or Special Character code is deter-

mined (decoded). If the received Transmission Character is

not found in that column, then the Transmission Character is

invalid. This is called a code violation. Independent of the

Transmission Character’s validity, the received Transmission

Character is used to calculate a new value of running disparity.

The new value is used as the Receiver’s current running dis-

parity for the next received Transmission Character.

The following rules for running disparity are used to calculate

the new running-disparity value for Transmission Characters

that have been transmitted (Transmitter’s running disparity)

and that have been received (Receiver’s running disparity).

Running disparity for a Transmission Character is calculated

from sub-blocks, where the first six bits (abcdei) form one sub-

block and the second four bits (fghj) form the other sub-block.

Running disparity at the beginning of the 6-bit sub-block is the

running disparity at the end of the previous Transmission

Character. Running disparity at the beginning of the 4-bit sub-

block is the running disparity at the end of the 6-bit sub-block.

Running disparity at the end of the Transmission Character is

the running disparity at the end of the 4-bit sub-block.

Table 19. Valid Transmission Characters

Data

D_INor Q_OUT

Byte Name

765

43210

Hex Value

Running disparity for the sub-blocks is calculated as follows:

D0.0

000

00000

00

1. Running disparity at the end of any sub-block is positive if

the sub-block contains more ones than zeros. It is also pos-

itive at the end of the 6-bit sub-block if the 6-bit sub-block

is 000111, and it is positive at the end of the 4-bit sub-block

if the 4-bit sub-block is 0011.

D1.0

D2.0

000

00001

00010

01

02

.

2. Running disparity at the end of any sub-block is negative if

the sub-block contains more zeros than ones. It is also neg-

ative at the end of the 6-bit sub-block if the 6-bit sub-block

is 111000, and it is negative at the end of the 4-bit sub-block

if the 4-bit sub-block is 1100.

D5.2

010

00101

45

.

3. Otherwise, running disparity at the end of the sub-block is

the same as at the beginning of the sub-block.

D30.7

D31.7

111

11110

11111

FE

FF

Use of the Tables for Generating Transmission Characters

The appropriate entry in the table is found for the Valid Data

byte or the Special Character byte for which a Transmission

Character is to be generated (encoded). The current value of

the Transmitter’s running disparity is used to select the Trans-

mission Character from its corresponding column. For each

Transmission Character transmitted, a new value of the run-

ning disparity is calculated. This new value is used as the

Transmitter’s current running disparity for the next Valid Data

Detection of a code violation does not necessarily show that

the Transmission Character in which the code violation was

detected is in error. Code violations may result from a prior

error that altered the running disparity of the bit stream which

did not result in a detectable error at the Transmission Char-

acter in which the error occurred. Table 20 shows an example

of this behavior.

Table 20. Code Violations Resulting from Prior Errors

RD

−

Character

D21.1

RD

−

Character

D10.2

RD

−

Character

D23.5

RD

+

Transmitted data character

Transmitted bit stream

Bit stream after error

−

101010 1001

101010 1011

D21.0

−

010101 0101

D10.2

−

111010 1010

Code Violation

+

−

+

Decoded data character

−

+

Document #: 38-02061 Rev. **

Page 33 of 40

PRELIMINARY

CYP15G0101DXA

Table 21. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)

Data

Byte

Data

Byte

Name HGF EDCBA

Bits

Current RD−

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Name HGF EDCBA

abcdei fghj

D0.0

D1.0

000 00000

000 00001

000 00010

000 00011

000 00100

000 00101

000 00110

000 00111

000 01000

000 01001

000 01010

000 01011

000 01100

000 01101

000 01110

000 01111

000 10000

000 10001

000 10010

000 10011

000 10100

000 10101

000 10110

000 10111

000 11000

000 11001

000 11010

000 11011

000 11100

000 11101

000 11110

000 11111

100111 0100 011000 1011

011101 0100 100010 1011

101101 0100 010010 1011

110001 1011 110001 0100

110101 0100 001010 1011

101001 1011 101001 0100

011001 1011 011001 0100

111000 1011 000111 0100

111001 0100 000110 1011

100101 1011 100101 0100

010101 1011 010101 0100

110100 1011 110100 0100

001101 1011 001101 0100

101100 1011 101100 0100

011100 1011 011100 0100

010111 0100 101000 1011

011011 0100 100100 1011

100011 1011 100011 0100

010011 1011 010011 0100

110010 1011 110010 0100

001011 1011 001011 0100

101010 1011 101010 0100

011010 1011 011010 0100

111010 0100 000101 1011

110011 0100 001100 1011

100110 1011 100110 0100

010110 1011 010110 0100

110110 0100 001001 1011

001110 1011 001110 0100

101110 0100 010001 1011

011110 0100 100001 1011

101011 0100 010100 1011

D0.1

D1.1

001 00000

001 00001

001 00010

001 00011

001 00100

001 00101

001 00110

001 00111

001 01000

001 01001

001 01010

001 01011

001 01100

001 01101

001 01110

001 01111

001 10000

001 10001

001 10010

001 10011

001 10100

001 10101

001 10110

001 10111

001 11000

001 11001

001 11010

001 11011

001 11100

001 11101

001 11110

001 11111

100111 1001 011000 1001

011101 1001 100010 1001

101101 1001 010010 1001

110001 1001 110001 1001

110101 1001 001010 1001

101001 1001 101001 1001

011001 1001 011001 1001

111000 1001 000111 1001

111001 1001 000110 1001

100101 1001 100101 1001

010101 1001 010101 1001

110100 1001 110100 1001

001101 1001 001101 1001

101100 1001 101100 1001

011100 1001 011100 1001

010111 1001 101000 1001

011011 1001 100100 1001

100011 1001 100011 1001

010011 1001 010011 1001

110010 1001 110010 1001

001011 1001 001011 1001

101010 1001 101010 1001

011010 1001 011010 1001

111010 1001 000101 1001

110011 1001 001100 1001

100110 1001 100110 1001

010110 1001 010110 1001

110110 1001 001001 1001

001110 1001 001110 1001

101110 1001 010001 1001

011110 1001 100001 1001

101011 1001 010100 1001

D2.0

D2.1

D3.0

D3.1

D4.0

D4.1

D5.0

D5.1

D6.0

D6.1

D7.0

D7.1

D8.0

D8.1

D9.0

D9.1

D10.0

D11.0

D12.0

D13.0

D14.0

D15.0

D16.0

D17.0

D18.0

D19.0

D20.0

D21.0

D22.0

D23.0

D24.0

D25.0

D26.0

D27.0

D28.0

D29.0

D30.0

D31.0

D10.1

D11.1

D12.1

D13.1

D14.1

D15.1

D16.1

D17.1

D18.1

D19.1

D20.1

D21.1

D22.1

D23.1

D24.1

D25.1

D26.1

D27.1

D28.1

D29.1

D30.1

D31.1

Document #: 38-02061 Rev. **

Page 34 of 40

PRELIMINARY

CYP15G0101DXA

Table 21. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Byte

Data

Byte

Bits

Current RD−

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Name HGF EDCBA

abcdei fghj

Name HGF EDCBA

D0.2

D1.2

010 00000

010 00001

010 00010

010 00011

010 00100

010 00101

010 00110

010 00111

010 01000

010 01001

010 01010

010 01011

010 01100

010 01101

010 01110

010 01111

010 10000

010 10001

010 10010

010 10011

010 10100

010 10101

010 10110

010 10111

010 11000

010 11001

010 11010

010 11011

010 11100

010 11101

010 11110

010 11111

100111 0101 011000 0101

011101 0101 100010 0101

101101 0101 010010 0101

110001 0101 110001 0101

110101 0101 001010 0101

101001 0101 101001 0101

011001 0101 011001 0101

111000 0101 000111 0101

111001 0101 000110 0101

100101 0101 100101 0101

010101 0101 010101 0101

110100 0101 110100 0101

001101 0101 001101 0101

101100 0101 101100 0101

011100 0101 011100 0101

010111 0101 101000 0101

011011 0101 100100 0101

100011 0101 100011 0101

010011 0101 010011 0101

110010 0101 110010 0101

001011 0101 001011 0101

101010 0101 101010 0101

011010 0101 011010 0101

111010 0101 000101 0101

110011 0101 001100 0101

100110 0101 100110 0101

010110 0101 010110 0101

110110 0101 001001 0101

001110 0101 001110 0101

101110 0101 010001 0101

011110 0101 100001 0101

101011 0101 010100 0101

D0.3

D1.3

011 00000

011 00001

011 00010

011 00011

011 00100

011 00101

011 00110

011 00111

011 01000

011 01001

011 01010

011 01011

011 01100

011 01101

011 01110

011 01111

011 10000

011 10001

011 10010

011 10011

011 10100

011 10101

011 10110

011 10111

011 11000

011 11001

011 11010

011 11011

011 11100

011 11101

011 11110

011 11111

100111 0011 011000 1100

011101 0011 100010 1100

101101 0011 010010 1100

110001 1100 110001 0011

110101 0011 001010 1100

101001 1100 101001 0011

011001 1100 011001 0011

111000 1100 000111 0011

111001 0011 000110 1100

100101 1100 100101 0011

010101 1100 010101 0011

110100 1100 110100 0011

001101 1100 001101 0011

101100 1100 101100 0011

011100 1100 011100 0011

010111 0011 101000 1100

011011 0011 100100 1100

100011 1100 100011 0011

010011 1100 010011 0011

110010 1100 110010 0011

001011 1100 001011 0011

101010 1100 101010 0011

011010 1100 011010 0011

111010 0011 000101 1100

110011 0011 001100 1100

100110 1100 100110 0011

010110 1100 010110 0011

110110 0011 001001 1100

001110 1100 001110 0011

101110 0011 010001 1100

011110 0011 100001 1100

101011 0011 010100 1100

D2.2

D2.3

D3.2

D3.3

D4.2

D4.3

D5.2

D5.3

D6.2

D6.3

D7.2

D7.3

D8.2

D8.3

D9.2

D9.3

D10.2

D11.2

D12.2

D13.2

D14.2

D15.2

D16.2

D17.2

D18.2

D19.2

D20.2

D21.2

D22.2

D23.2

D24.2

D25.2

D26.2

D27.2

D28.2

D29.2

D30.2

D31.2

D10.3

D11.3

D12.3

D13.3

D14.3

D15.3

D16.3

D17.3

D18.3

D19.3

D20.3

D21.3

D22.3

D23.3

D24.3

D25.3

D26.3

D27.3

D28.3

D29.3

D30.3

D31.3

Document #: 38-02061 Rev. **

Page 35 of 40

PRELIMINARY

CYP15G0101DXA

Table 21. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Byte

Data

Byte

Bits

Current RD−

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Name HGF EDCBA

abcdei fghj

Name HGF EDCBA

D0.4

D1.4

100 00000

100 00001

100 00010

100 00011

100 00100

100 00101

100 00110

100 00111

100 01000

100 01001

100 01010

100 01011

100 01100

100 01101

100 01110

100 01111

100 10000

100 10001

100 10010

100 10011

100 10100

100 10101

100 10110

100 10111

100 11000

100 11001

100 11010

100 11011

100 11100

100 11101

100 11110

100 11111

100111 0010 011000 1101

011101 0010 100010 1101

101101 0010 010010 1101

110001 1101 110001 0010

110101 0010 001010 1101

101001 1101 101001 0010

011001 1101 011001 0010

111000 1101 000111 0010

111001 0010 000110 1101

100101 1101 100101 0010

010101 1101 010101 0010

110100 1101 110100 0010

001101 1101 001101 0010

101100 1101 101100 0010

011100 1101 011100 0010

010111 0010 101000 1101

011011 0010 100100 1101

100011 1101 100011 0010

010011 1101 010011 0010

110010 1101 110010 0010

001011 1101 001011 0010

101010 1101 101010 0010

011010 1101 011010 0010

111010 0010 000101 1101

110011 0010 001100 1101

100110 1101 100110 0010

010110 1101 010110 0010

110110 0010 001001 1101

001110 1101 001110 0010

101110 0010 010001 1101

011110 0010 100001 1101

101011 0010 010100 1101

D0.5

D1.5

101 00000

101 00001

101 00010

101 00011

101 00100

101 00101

101 00110

101 00111

101 01000

101 01001

101 01010

101 01011

101 01100

101 01101

101 01110

101 01111

101 10000

101 10001

101 10010

101 10011

101 10100

101 10101

101 10110

101 10111

101 11000

101 11001

101 11010

101 11011

101 11100

101 11101

101 11110

101 11111

100111 1010 011000 1010

011101 1010 100010 1010

101101 1010 010010 1010

110001 1010 110001 1010

110101 1010 001010 1010

101001 1010 101001 1010

011001 1010 011001 1010

111000 1010 000111 1010

111001 1010 000110 1010

100101 1010 100101 1010

010101 1010 010101 1010

110100 1010 110100 1010

001101 1010 001101 1010

101100 1010 101100 1010

011100 1010 011100 1010

010111 1010 101000 1010

011011 1010 100100 1010

100011 1010 100011 1010

010011 1010 010011 1010

110010 1010 110010 1010

001011 1010 001011 1010

101010 1010 101010 1010

011010 1010 011010 1010

111010 1010 000101 1010

110011 1010 001100 1010

100110 1010 100110 1010

010110 1010 010110 1010

110110 1010 001001 1010

001110 1010 001110 1010

101110 1010 010001 1010

011110 1010 100001 1010

101011 1010 010100 1010

D2.4

D2.5

D3.4

D3.5

D4.4

D4.5

D5.4

D5.5

D6.4

D6.5

D7.4

D7.5

D8.4

D8.5

D9.4

D9.5

D10.4

D11.4

D12.4

D13.4

D14.4

D15.4

D16.4

D17.4

D18.4

D19.4

D20.4

D21.4

D22.4

D23.4

D24.4

D25.4

D26.4

D27.4

D28.4

D29.4

D30.4

D31.4

D10.5

D11.5

D12.5

D13.5

D14.5

D15.5

D16.5

D17.5

D18.5

D19.5

D20.5

D21.5

D22.5

D23.5

D24.5

D25.5

D26.5

D27.5

D28.5

D29.5

D30.5

D31.5

Document #: 38-02061 Rev. **

Page 36 of 40

PRELIMINARY

CYP15G0101DXA

Table 21. Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data

Byte

Data

Byte

Bits

Current RD−

Current RD+

abcdei fghj

Bits

Current RD−

abcdei fghj

Current RD+

abcdei fghj

Name HGF EDCBA

abcdei fghj

Name HGF EDCBA

D0.6

D1.6

110 00000

110 00001

110 00010

110 00011

110 00100

110 00101

110 00110

110 00111

110 01000

110 01001

110 01010

110 01011

110 01100

110 01101

110 01110

110 01111

110 10000

110 10001

110 10010

110 10011

110 10100

110 10101

110 10110

110 10111

110 11000

110 11001

110 11010

110 11011

110 11100

110 11101

110 11110

110 11111

100111 0110 011000 0110

011101 0110 100010 0110

101101 0110 010010 0110

110001 0110 110001 0110

110101 0110 001010 0110

101001 0110 101001 0110

011001 0110 011001 0110

111000 0110 000111 0110

111001 0110 000110 0110

100101 0110 100101 0110

010101 0110 010101 0110

110100 0110 110100 0110

001101 0110 001101 0110

101100 0110 101100 0110

011100 0110 011100 0110

010111 0110 101000 0110

011011 0110 100100 0110

100011 0110 100011 0110

010011 0110 010011 0110

110010 0110 110010 0110

001011 0110 001011 0110

101010 0110 101010 0110

011010 0110 011010 0110

111010 0110 000101 0110

110011 0110 001100 0110

100110 0110 100110 0110

010110 0110 010110 0110

110110 0110 001001 0110

001110 0110 001110 0110

101110 0110 010001 0110

011110 0110 100001 0110

101011 0110 010100 0110

D0.7

D1.7

111 00000

111 00001

111 00010

111 00011

111 00100

111 00101

111 00110

111 00111

111 01000

111 01001

111 01010

111 01011

111 01100

111 01101

111 01110

111 01111

111 10000

111 10001

111 10010

111 10011

111 10100

111 10101

111 10110

111 10111

111 11000

111 11001

111 11010

111 11011

111 11100

111 11101

111 11110

111 11111

100111 0001 011000 1110

011101 0001 100010 1110

101101 0001 010010 1110

110001 1110 110001 0001

110101 0001 001010 1110

101001 1110 101001 0001

011001 1110 011001 0001

111000 1110 000111 0001

111001 0001 000110 1110

100101 1110 100101 0001

010101 1110 010101 0001

110100 1110 110100 1000

001101 1110 001101 0001

101100 1110 101100 1000

011100 1110 011100 1000

010111 0001 101000 1110

011011 0001 100100 1110

100011 0111 100011 0001

010011 0111 010011 0001

110010 1110 110010 0001

001011 0111 001011 0001

101010 1110 101010 0001

011010 1110 011010 0001

111010 0001 000101 1110

110011 0001 001100 1110

100110 1110 100110 0001

010110 1110 010110 0001

110110 0001 001001 1110

001110 1110 001110 0001

101110 0001 010001 1110

011110 0001 100001 1110

101011 0001 010100 1110

D2.6

D2.7

D3.6

D3.7

D4.6

D4.7

D5.6

D5.7

D6.6

D6.7

D7.6

D7.7

D8.6

D8.7

D9.6

D9.7

D10.6

D11.6

D12.6

D13.6

D14.6

D15.6

D16.6

D17.6

D18.6

D19.6

D20.6

D21.6

D22.6

D23.6

D24.6

D25.6

D26.6

D27.6

D28.6

D29.6

D30.6

D31.6

D10.7

D11.7

D12.7

D13.7

D14.7

D15.7

D16.7

D17.7

D18.7

D19.7

D20.7

D21.7

D22.7

D23.7

D24.7

D25.7

D26.7

D27.7

D28.7

D29.7

D30.7

D31.7

Document #: 38-02061 Rev. **

Page 37 of 40

PRELIMINARY

CYP15G0101DXA

Table 22. Valid Special Character Codes and Sequences (TXCTx = special character code or RXSTx[2:0] = 001)^{[37, 38]}

S.C. Byte Name

Cypress

S.C. Byte

Alternate

S.C. Code

Name

Bits

HGF EDCBA

S.C. Byte

Bits

Current RD−

Current RD+

abcdei fghj

Name^[39]

C0.0

Name^[39]

HGF EDCBA

abcdei fghj

K28.0

(C00)

(C01)

(C02)

(C03)

(C04)

(C05)

(C06)

(C07)

(C08)

(C09)

000 00000

000 00001

000 00010

000 00011

000 00100

000 00101

000 00110

000 00111

000 01000

000 01001

000 01010

000 01011

C28.0 (C1C)

C28.1 (C3C)

C28.2 (C5C)

C28.3 (C7C)

C28.4 (C9C)

C28.5 (CBC)

C28.6 (CDC)

C28.7 (CFC)

C23.7 (CF7)

C27.7 (CFB)

C29.7 (CFD)

C30.7 (CFE)

000 11100

001 11100

010 11100

011 11100

100 11100

101 11100

110 11100

111 11100

111 10111

111 11011

111 11101

111 11110

001111 0100

001111 1001

001111 0101

001111 0011

001111 0010

001111 1010

001111 0110

001111 1000

111010 1000

110110 1000

101110 1000

011110 1000

110000 1011

110000 0110

110000 1010

110000 1100

110000 1101

110000 0101

110000 1001

110000 0111

000101 0111

001001 0111

010001 0111

100001 0111

K28.1^[40]

K28.2^[40]

K28.3

K28.4^[40]

K28.5^{[40, 41]}

K28.6^[40]

K28.7^{[40, 42]}

K23.7

C1.0

C2.0

C3.0

C4.0

C5.0

C6.0

C7.0

C8.0

C9.0

K27.7

K29.7

C10.0 (C0A)

C11.0 (C0B)

K30.7

End of Frame Sequence

EOFxx^[43]

C2.1

(C22)

001 00010

C2.1

(C22)

001 00010

−K28.5,Dn.xxx0

+K28.5,Dn.xxx1

Code Rule Violation and SVS Tx Pattern

Exception^{[42, 44]}C0.7

(CE0)

(CE1)

(CE2)

111 00000

111 00001

111 00010

C0.7

C1.7

C2.7

(CE0) 111 00000^[48]

(CE1) 111 00001^[48]

(CE2) 111 00010^[48]

100111 1000

001111 1010

110000 0101

011000 0111

001111 1010

110000 0101

−K28.5^[45]

C1.7

C2.7

+K28.5^[46]

Running Disparity Violation Pattern

Exception^[47]

C4.7

(CE4)

111 00100

C4.7

(CE4) 111 00100 ^[48]

110111 0101

001000 1010

Notes:

37. All codes not shown are reserved.

38. Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to

describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through

C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).

39. Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes. The decoding process for received

characters generates Cypress codes or Alternate codes as selected by the DECMODE configuration input.

40. These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON

protocols.

41. The K28.5 character is used for framing operations by the receiver. It is also the pad or fill character transmitted to maintain the serial link when no user data

is available.

42. Care must be taken when using this Special Character code. When a C7.0 is followed by a D11.x or D20.x, or when an SVS (C0.7) is followed by a D11.x,

an alias K28.5 sync character is created. These sequences can cause erroneous framing and should be avoided while RFEN = HIGH.

43. C2.1 = Transmit either −K28.5+ or +K28.5− as determined by Current RD and modify the Transmission Character that follows, by setting its least significant

bit to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus (−) the LSB becomes 1. This

modification allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.

For example, to send “EOFdt” the controller could issue the sequence C2.1−D21.4− D21.4−D21.4, and the HOTLink Transmitter will send either K28.5−D21.4−

D21.4−D21.4 or K28.5−D21.5− D21.4−D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence C2.1−D10.4−D21.4−

D21.4, and the HOTLink Transmitter will send either K28.5−D10.4−D21.4− D21.4 or K28.5−D10.5−D21.4− D21.4 based on Current RD. The receiver will

never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.

44. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. The receiver will only output

this Special Character if the Transmission Character being decoded is not found in the tables.

45. C1.7 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong

running disparity. The receiver will output C1.7 if −K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.

46. C2.7 = Transmit Positive K28.5 (+K28.5−) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong

running disparity. The receiver will output C2.7 if +K28.5 is received with RD−, otherwise K28.5 is decoded as C5.0 or C1.7.

47. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation. The receiver will only output this Special Character if the Transmission

Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.

48. Supported only for data transmission. The receive status for these conditions will be reported by specific combinations of receive status bits.

Document #: 38-02061 Rev. **

Page 38 of 40

PRELIMINARY

CYP15G0101DXA

Ordering Information

Operating

Range

Speed

Standard

Ordering Code

Package Name

BB100

Package Type

100-Ball Grid Array

CYP15G0101DXA-BBC

CYP15G0101DXA-BBI

Commercial

Industrial

BB100

Package Diagram

100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100

51-85107-*B

HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor Corporation. IBM

and ESCON are registered trademarks and FICON is a trademark of International Business Machines. All product and company

names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-02061 Rev. **

Page 39 of 40

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

PRELIMINARY

CYP15G0101DXA

Revision History

Document Title: CYP15G0101DXA Single Channel HOTLink II™ Transceiver (Preliminary)

Document Number: 38-02061

ISSUE

DATE

ORIG. OF

CHANGE

REV.

ECN NO.

DESCRIPTION OF CHANGE

**

117226

08/21/02

AMV

New Data Sheet

Document #: 38-02061 Rev. **

Page 40 of 40

厂商	型号	描述	页数
NIDEC	CYP	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0200TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201MC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TB	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0201TC	[ PIANO SWITCHES (FULL PITCH) ]	5 页
NIDEC	CYP-0202MB	[ PIANO SWITCHES (FULL PITCH) ]	5 页