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AZV99

型号：

AZV99

描述：

PECL / LVDS振荡器增益级和缓冲区，可选择启用[ PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable ]

品牌：

AZM[ ARIZONA MICROTEK, INC ]

页数：

15 页

PDF大小：

226 K

下载PDF手册
ARIZONA MICROTEK, INC.  
AZV99  
PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable  
PACKAGE AVAILABILITY  
FEATURES  
PACKAGE  
PART NUMBER  
MARKING  
NOTES  
•
•
Green and RoHS Compliant /  
Lead (Pb) Free Packages Available  
Similar Operation as AZ100LVEL16VT  
except with LVDS Outputs  
Operating Range of 3.0V to 5.5V  
Minimizes External Components  
Selectable Enable Polarity and  
Threshold (CMOS/TTL or PECL)  
Available in a 2x2 or 3x3mm  
MLP Package  
MLP 8 (2x2x0.75)  
Green / RoHS  
Compliant / Lead (Pb)  
Free  
V1G  
<Date Code>  
AZV99NG  
1,2  
•
•
•
V9  
MLP 8 (2x2x0.75)  
AZV99NA  
1,2  
1,2  
<Date Code>  
MLP 8 (2x2x0.75)  
Green / RoHS  
Compliant / Lead (Pb)  
Free  
MLP 8 (2x2x0.75)  
Green / RoHS  
Compliant / Lead (Pb)  
Free  
MLP 16 (3x3) Green /  
RoHS Compliant /  
Lead (Pb) Free  
TSSOP 8 RoHS  
Compliant / Lead (Pb) AZV99T+  
Free  
V8G  
<Date Code>  
AZV99NBG  
•
•
S–Parameter (.s2p) and IBIS Model  
Files Available on Arizona Microtek  
Website  
V2G  
<Date Code>  
AZV99NDG  
AZV99LG  
1,2  
1,2  
AZMG  
V99  
<Date Code>  
AZ+  
V99  
1,2,3  
4
DIE  
1
AZV99XP  
N/A  
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape &  
Reel.  
2
3
4
Date code format: “Y” for year followed by “WW” for week.  
Date Code “YWW” on underside of part.  
Waffle Pack  
DESCRIPTION  
The AZV99 is a specialized oscillator gain stage with LVDS output buffer including an enable. The enable  
input (EN) allows continuous oscillator operation by only controlling the QHG /Q¯HG outputs.  
The AZV99 also provides a VBB and 470Ω internal bias resistors from D to VBB and D¯ to VBB. The VBB pin can  
support 1.5 mA sink/source current. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.  
MLP 16, 3x3 mm Package (L) or DIE (X)  
The MLP 16 and die versions of the AZV99 provide a selectable enable (EN). Enable polarity and threshold can  
be selected to accommodate either CMOS/TTL or PECL input levels. See the enable truth table for enable function.  
If enable pull-up is desired in the CMOS/TTL mode, an external ≤20kΩ resistor connecting EN to VCC will override  
the on-chip pull-down resistor.  
Outputs Q/Q¯ each have a selectable on-chip pull-down current source. See the current source truth table for  
current source functions. External resistors may also be used to increase pull-down current to a maximum of 25mA  
(includes internal on-chip current source).  
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541  
www.azmicrotek.com  
AZV99  
MLP 8, 2x2 mm Package, NA, NB & ND Options  
The MLP 8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (¯E¯N¯). When the  
¯E¯N¯ input is LOW, the Q¯ and QHG/Q¯HG outputs pass data from the inputs. When ¯E¯N¯ is HIGH, the Q¯ output  
continues to pass data while the QHG output is forced high and the Q¯HG output is forced low.  
Only the Q¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of  
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes  
4mA on-chip current source).  
The AZV99NB and AZV99ND versions operates with a single ended data input (D). The D¯ input is internally  
bonded directly to the VBB pin bypassing the 470Ω bias resistor.  
TSSOP 8 Package (T), MLP 8 Package, (N)  
The TSSOP 8 (T) and MLP 8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When  
the EN input is HIGH, the Q¯ and QHG/Q¯HG outputs pass data from the inputs. When EN is LOW, the Q¯ output  
continues to pass data while the QHG output is forced high and the Q¯HG output is forced low.  
Only the Q¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of  
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes  
4mA on-chip current source).  
The TSSOP 8 (T) and MLP 8 (N) AZV99 operates with a single ended data input (D). The D¯ input is internally  
bonded directly to the VBB pin bypassing the 470Ω bias resistor.  
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.  
PIN DESCRIPTION  
4mA EA.  
Q
PIN  
D/D¯  
Q/Q¯  
QHG/Q¯HG LVDS Data Outputs  
VBB Reference Voltage Output  
EN-SEL Selects Enable Logic  
FUNCTION  
Data Inputs  
PECL Data Outputs  
Q
D
D
CS-SEL  
QHG  
QHG  
470  
VBB  
EN/E¯N¯  
CS-SEL  
VEE  
Enable Input  
Selects Q and Q¯ Current Source Magnitude  
Negative Supply  
VEE  
EN/EN  
VCC  
Positive Supply  
CMOS/TTL  
THRESHOLD  
EN-SEL  
ENABLE TRUTH TABLE  
EN-SEL  
EN/¯E¯N¯  
Q/Q¯ QHG Q¯HG  
Data Data Data  
Data High Low  
Data High Low  
Data Data Data  
CURRENT SOURCE TRUTH TABLE  
NC  
NC  
VEE  
VEE  
PECL Low or NC  
PECL High or VCC  
CMOS/TTL Low, VEE or NC  
CMOS/TTL High or VCC  
CS-SEL  
Q
4mA typ.  
8mA typ.  
0
Q¯  
NC  
VEE  
VCC  
4mA typ.  
8mA typ.  
4mA typ.  
1
1
1
1
2
1 EN-SEL connections must be less than 1Ω.  
1 CS-SEL connections must be less than 1Ω.  
2 An external ≤20kΩ pull-up resistor between EN and VCC ensures a  
High when the EN pin is not driven.  
April 2007 * REV - 9  
www.azmicrotek.com  
2
AZV99  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
Characteristic  
Rating  
Unit  
VCC  
VI  
VD/D¯  
Power Supply  
Input Voltage  
D/D¯ Input Voltage  
Output Current  
0 to +6.0  
0 to +6.0  
±0.75 with respect to VBB  
Vdc  
Vdc  
Vdc  
— Continuous  
— Surge  
— Continuous QHG/Q¯HG  
— Surge QHG/Q¯HG  
Q/Q¯  
Q/Q¯  
25  
50  
5
10  
IOUT  
mA  
TA  
TSTG  
Operating Temperature Range  
Storage Temperature Range  
-40 to +85  
-65 to +150  
°C  
°C  
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
2255  
1375  
Max  
2465  
1745  
Min  
2275  
1400  
Max  
2465  
1680  
Min  
2275  
1400  
Max  
2465  
1680  
Min  
2275  
1400  
Max  
2465  
1680  
VOH  
VOL  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Input HIGH Voltage  
Q/Q¯  
Q/Q¯  
mV  
mV  
VIH  
VIL  
D/D¯1, EN (EN-SEL open)1  
2135  
2000  
2560  
VCC  
2135  
2000  
2560  
VCC  
2135  
2000  
2560  
VCC  
2135  
2000  
2560  
VCC  
mV  
mV  
EN (EN-SEL tied to VEE  
Input LOW Voltage  
D/D¯1, EN (EN-SEL open)1  
EN (EN-SEL tied to VEE  
)
1400  
GND  
1910  
0.5  
1825  
800  
2050  
1400  
GND  
1910  
0.5  
1825  
800  
2050  
1400  
GND  
1910  
0.5  
1825  
800  
2050  
1400  
GND  
1910  
0.5  
1825  
800  
2050  
)
VBB  
IIL  
IIH  
Reference Voltage1  
mV  
μA  
μA  
mA  
Input LOW Current EN3  
Input HIGH Current EN3  
Power Supply Current2  
150  
48  
150  
48  
150  
48  
150  
52  
IEE  
1.  
2.  
3.  
Voltage levels vary 1:1 with VCC.  
Specified with CS-SEL open.  
Specified with EN-SEL open.  
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
3955  
3075  
Max  
4165  
3445  
Min  
3975  
3100  
Max  
4165  
3380  
Min  
3975  
3100  
Max  
4165  
3380  
Min  
3975  
3100  
Max  
4165  
3380  
VOH  
VOL  
Output HIGH Voltage1,2  
Output LOW Voltage1,2  
Input HIGH Voltage  
Q/Q¯  
Q/Q¯  
mV  
mV  
VIH  
VIL  
D/D¯1, EN (EN-SEL open)1  
3835  
2000  
4260  
VCC  
3835  
2000  
4260  
VCC  
3835  
2000  
4260  
VCC  
3835  
2000  
4260  
VCC  
mV  
mV  
EN (EN-SEL tied to VEE  
Input LOW Voltage  
D/D¯1, EN (EN-SEL open)1  
EN (EN-SEL tied to VEE  
)
3100  
GND  
3610  
0.5  
3525  
800  
3750  
3100  
GND  
3610  
0.5  
3525  
800  
3750  
3100  
GND  
3610  
0.5  
3525  
800  
3750  
3100  
GND  
3610  
0.5  
3525  
800  
3750  
)
VBB  
IIL  
IIH  
Reference Voltage1  
mV  
μA  
μA  
mA  
Input LOW Current EN3  
Input HIGH Current EN3  
Power Supply Current2  
150  
48  
150  
48  
150  
48  
150  
52  
IEE  
1.  
2.  
3.  
Voltage levels vary 1:1 with VCC.  
Specified with CS-SEL open.  
Specified with EN-SEL open.  
April 2007 * REV - 9  
www.azmicrotek.com  
3
AZV99  
LVDS DC Characteristics for QHG/Q¯HG Outputs1 (VEE = GND, VCC = +3.0V to +5.5V)  
-40°C  
0°C  
25°C  
85°C  
Symbol  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
VOH  
VOL  
VOC  
ΔVOC  
VOUT  
Output HIGH Voltage  
Output LOW Voltage  
1600  
1600  
1600  
1600  
mV  
mV  
mV  
mV  
mV  
mV  
900  
1125  
-50  
250  
500  
900  
1125  
-50  
250  
500  
900  
1125  
-50  
250  
500  
900  
1125  
-50  
250  
500  
Output Common Mode Voltage2  
Change in Common Mode Voltage3  
Single-Ended Output Swing  
1375  
50  
450  
900  
1375  
50  
450  
900  
1375  
50  
450  
900  
1375  
50  
450  
900  
VDIFF_OUT Differential Output Swing  
1.  
2.  
3.  
Specified with 100Ω resistor connecting QHG and Q¯HG together.  
Common mode voltage is the center voltage between QHG and Q¯HG during a steady state.  
Change in common mode voltage is the difference between common mode voltages at opposite binary states.  
AC Characteristics (VEE = GND, VCC = +3.0V to +5.5V)  
-40°C  
Typ  
0°C  
Typ  
25°C  
Typ  
85°C  
Typ  
Symbol  
tPLH / tPHL  
tSKEW  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Propagation Delay  
D to Q/Q¯ Outputs1  
(SE)  
(SE)  
(SE)  
400  
550  
20  
400  
550  
20  
400  
550  
20  
430  
630  
20  
ps  
D to QHG/Q¯HG Outputs2  
Duty Cycle Skew Q/Q¯3  
5
5
5
5
ps  
mV  
VPP (AC) Differnetial Input Swing4  
Output Rise/Fall Times  
80  
1000  
80  
1000  
80  
1000  
80  
1000  
tr / tf  
(20% - 80%)  
Q/Q¯1  
100  
180  
260  
280  
100  
180  
260  
280  
100  
180  
260  
280  
100  
180  
260  
280  
ps  
2
QHG/Q¯HG  
1.  
2.  
3.  
4.  
Specified with CS-SEL connected to VEE and Q/Q¯ with AC coupled 50Ω loads.  
Specified with 100Ω resistor connecting QHG and Q¯HG together.  
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.  
The peak-to-peak differential input swing is the range for which AC parameters guaranteed. VD and VD¯ must remain within the range of ±750 mV  
with respect to VBB  
.
AC PP INPUT  
D
D
VPP (AC)  
April 2007 * REV - 9  
www.azmicrotek.com  
4
AZV99  
0.95  
0.9  
0
-10  
-20  
-30  
-40  
-50  
0.85  
0.8  
S11 MAG 8mA  
S11 MAG 4mA  
S11 PHASE 8mA  
S11 PHASE 4mA  
0.75  
0.7  
50  
150  
250  
350  
450  
550  
650  
750  
850  
950 1050 1150 1250 1350  
Frequency (MHz)  
S11, D to Q¯, 50 Ω AC load on Q¯  
0.025  
0.02  
0.015  
0.01  
0.005  
0
250.00  
200.00  
150.00  
100.00  
50.00  
S12 MAG 8mA  
S12 MAG 4mA  
S12 PHASE 8mA  
S21 PHASE 4mA  
0.00  
50  
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350  
Frequency (MHz)  
S12, D to Q¯, 50 Ω AC load on Q¯  
April 2007 * REV - 9  
www.azmicrotek.com  
5
AZV99  
40  
35  
30  
25  
20  
15  
10  
5
180  
160  
140  
120  
100  
80  
S21 MAG 8mA  
S21 MAG 4mA  
S21 PHASE 8mA  
S21 PHASE 4mA  
60  
40  
0
20  
50  
150  
250  
350  
450  
550  
650  
750  
850  
950 1050 1150 1250 1350  
Frequency (MHz)  
S21, D to Q¯, 50 Ω AC load on Q¯  
0.8  
0.7  
0.6  
0.5  
0.4  
180.00  
160.00  
140.00  
120.00  
100.00  
S22 MAG 8mA  
S22 MAG 4mA  
S22 PHASE 8mA  
S22 PHASE 4mA  
50  
150  
250  
350  
450  
550  
650  
750  
850  
950 1050 1150 1250 1350  
Frequency (MHz)  
S22, D to Q¯, 50 Ω AC load on Q¯  
April 2007 * REV - 9  
www.azmicrotek.com  
6
AZV99  
AC Coupling Capacitor  
C2  
3.3 or 5 V  
CMOS  
R1  
See table  
AZV99  
Front End  
D
D
VBB  
C1  
0.01 μF  
Application Circuit for CMOS Inputs  
R11  
AC  
Coupled  
(C2 in  
DC  
Coupled  
(C2  
Input  
Type  
circuit)  
shorted)  
3.3 V  
CMOS  
5 V CMOS  
1.1 kΩ  
1.6 kΩ  
2.0 kΩ  
3.3 kΩ  
1 R1 should be chosen so that the input swing on the D input  
with respect to D¯ is in the range of ±80 to ±1000 mV, per the  
AC Characteristics table and the D input is < ±750 mV with  
respect to VBB.  
Recommended Component Values for CMOS Single Ended Inputs  
April 2007 * REV - 9  
www.azmicrotek.com  
7
AZV99  
TIMING DIAGRAM  
D
(PECL)  
EN-SEL OPEN (EN)  
EN/  
EN  
{
(CMOS/TTL)  
EN-SEL SHORTED TO VEE (EN)  
Q
Q
QHG  
QHG  
PINOUT FOR AZV99L  
MLP 16, 3x3mm  
AZV99L  
VCC  
13  
NC  
14  
Q
Q
15  
16  
NC  
D
1
CS-SEL  
QHG  
12  
11  
2
3
4
QHG  
10  
9
D
VBB  
EN-SEL  
5
6
7
8
VEE  
NC  
NC  
EN  
TOP VIEW  
Bottom Center Pad may be left open or tied to VEE  
April 2007 * REV - 9  
www.azmicrotek.com  
8
AZV99  
LOGIC DIAGRAMS AND PINOUTS FOR  
AZV99NA, AZV99NB, AZV99ND  
4mA  
4mA  
Q
Q
VEE  
VEE  
D
QHG  
D
D
QHG  
QHG  
QHG  
470  
470  
470  
VBB/D  
VBB  
EN  
AZV99NB  
AZV99ND  
AZV99NA  
EN  
EN operation follows PECL functionality. See the  
Timing Diagram.  
MLP 8, 2x2mm  
MLP 8, 2x2mm  
AZV99NB  
AZV99NA  
D
D
D
1
2
3
1
2
3
Q
Q
8
7
8
7
VCC  
QHG  
QHG  
VCC  
QHG  
QHG  
VBB/D  
EN  
VEE  
6
5
VBB  
EN  
6
5
VEE  
4
4
TOP VIEW  
TOP VIEW  
Bottom Center Pad is the VEE  
return.  
Bottom Center Pad may be left open  
or tied to VEE. Pin 4 is the VEE return.  
MLP 8, 2x2mm  
AZV99ND  
1
2
3
Q
D
8
7
VCC  
QHG  
QHG  
VBB/D  
EN  
6
5
4
VEE  
TOP VIEW  
Bottom Center Pad may be left open  
or tied to VEE. Pin 5 is the VEE return.  
April 2007 * REV - 9  
www.azmicrotek.com  
9
AZV99  
LOGIC DIAGRAM AND PINOUTS FOR  
AZV99T, AZV99N  
4mA  
Q
VEE  
D
QHG  
QHG  
470  
VBB/D  
EN  
AZV99T  
AZV99N  
CMOS/TTL  
THRESHOLD  
EN follows CMOS/TTL functionality. See the  
Timing Diagram.  
1
2
3
4
8
7
6
5
VCC  
QHG  
Q
D
AZV99T  
TSSOP 8  
QHG  
VEE  
VBB / D  
EN  
MLP 8, 2x2mm  
AZV99N  
1
2
3
Q
D
8
7
VCC  
QHG  
QHG  
VBB/D  
EN  
6
4
5
VEE  
TOP VIEW  
Bottom Center Pad may be left open  
or tied to VEE. Pin 5 is the VEE return.  
April 2007 * REV - 9  
www.azmicrotek.com  
10  
AZV99  
DIE PAD COORDINATES  
AZV99 DIE:  
AZV99  
L K  
M
A
J
I
B
DIE SIZE: 950u X 940u  
DIE THICKNESS: 180u  
BOND PAD: 85u X 85u  
C
D
H
G
E F  
PAD COORDINATES1  
NAME  
PAD CENTERS  
PAD DESIGNATION  
X(Microns)  
Y(Microns)  
312.5  
A
B
C
D
E
F
G
H
I
J
K
L
M
D
D¯  
VBB  
EN/¯E¯N¯  
VEE  
NC  
EN-SEL  
Q¯HG  
QHG  
CS-SEL  
VCC  
-342.5  
-342.5  
-342.5  
-342.5  
-33.5  
126.5  
312.5  
312.5  
312.5  
312.5  
302.5  
142.5  
-140.5  
144.5  
-87.0  
-255.0  
-312.5  
-312.5  
-248.5  
-98.5  
51.5  
201.5  
342.5  
342.5  
Q
Q¯  
342.5  
1. 0, 0 is center of die.  
April 2007 * REV - 9  
www.azmicrotek.com  
11  
AZV99  
PACKAGE DIAGRAM  
MLP 16  
A
D
D2  
D2/2  
2.  
D
2
B
INDEX AREA  
(D/2 x E/2)  
E2/2  
E2  
E
2
3 x  
e
E
2
1
e
5.  
2 x  
aaa C  
16 x b  
3.  
TOP VIEW  
2 x  
aaa C  
M
bbb C A B  
L
3 x  
e
BOTTOM VIEW  
ccc C  
A3  
A
0.08 C  
SEATING  
PLANE  
4.  
SIDE  
VIEW  
C
A1  
MILLIMETERS  
NOTES:  
DIM MIN  
MAX  
1.00  
1. DIMENSIONING AND TOLERANCING  
CONFORM TO ASME T14-1994.  
2. THE TERMINAL #1 AND PAD  
NUMBERING CONVENTION SHALL  
CONFORM TO JESD 95-1 SPP-012.  
0.80  
0.00  
A
A1  
A3  
b
0.05  
0.25 REF  
0.18  
2.90  
0.25  
2.90  
0.25  
0.30  
3.10  
1.95  
3.10  
1.95  
D
3. DIMENSION b APPLIES TO METALLIZED  
D2  
E
PAD AND IS MEASURED BETWEEN 0.25  
AND 0.30 mm FROM PAD TIP.  
E2  
e
4. COPLANARITY APPLIES TO THE  
0.50 BSC  
EXPOSED PADS AS WELL AS THE  
TERMINALS.  
0.30  
0.50  
L
0.25  
0.10  
0.10  
aaa  
bbb  
ccc  
INSIDE CORNERS OF METALLIZED PAD  
MAY BE SQUARE OR ROUNDED  
5.  
April 2007 * REV - 9  
www.azmicrotek.com  
12  
AZV99  
PACKAGE DIAGRAM  
MLP 8 2x2mm  
Pin 1 Dot  
By Marking  
2.000±0.050  
MLP 8  
(2x2mm)  
2.000±0.050  
TOP VIEW  
Pin 1 Identification  
R0.100 TYP  
0.350±0.050  
0.250±0.050  
8
7
6
5
1
2
3
4
1.200±0.050 1.750  
exp. pad Ref.  
0.500 bsc  
0.600±0.050  
exp. pad  
BOTTOM VIEW  
1
2
3
4
0.900±0.050  
0.000-0.050  
0.203±0.025  
SIDE VIEW  
Note: All dimensions are in mm  
April 2007 * REV - 9  
www.azmicrotek.com  
13  
AZV99  
PACKAGE DIAGRAM  
TSSOP 8  
MILLIMETERS  
DIM  
MIN  
MAX  
1.10  
0.15  
0.95  
A
A1  
A2  
A3  
bp  
c
0.05  
0.80  
0.25  
0.25  
0.15  
2.90  
2.90  
0.45  
0.28  
3.10  
3.10  
NOTES:  
1.  
2.  
3.  
DIMENSIONS D AND E DO NOT  
INCLUDE MOLD PROTRUSION.  
MAXIMUM MOLD PROTRUSION  
FOR D IS 0.15mm.  
MAXIMUM MOLD PROTRUSION  
FOR E IS 0.25mm.  
D
E
e
HE  
L
Lp  
v
w
y
0.65  
0.94  
4.70  
0.40  
5.10  
0.70  
0.10  
0.10  
0.10  
Z
θ
0.35  
0O  
0.70  
6O  
April 2007 * REV - 9  
www.azmicrotek.com  
14  
AZV99  
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.  
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona  
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all  
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license  
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems  
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a  
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such  
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,  
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly  
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.  
April 2007 * REV - 9  
www.azmicrotek.com  
15  
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