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CYK256K16SCBU-70BVXI

型号：

CYK256K16SCBU-70BVXI

描述：

4兆位（ 256K ×16 ）伪静态RAM[ 4-Mbit (256K x 16) Pseudo Static RAM ]

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

313 K

下载PDF手册
CYK256K16SCCB  
4-Mbit (256K x 16) Pseudo Static RAM  
in portable applications such as cellular telephones. The  
device can be put into standby mode reducing power  
consumption dramatically when deselected (CE1 LOW, CE2  
HIGH or both BHE and BLE are HIGH). The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected (CE1 HIGH, CE2 LOW, OE is deasserted  
HIGH), or during a write operation (Chip Enabled and Write  
Enable WE LOW).  
Features  
• Advanced low-power MoBL® architecture  
• High speed: 55 ns, 60 ns and 70 ns  
• Wide voltage range: 2.7V to 3.3V  
• Typical active current: 1 mA @ f = 1 MHz  
• Low standby power  
Reading from the device is accomplished by asserting the  
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable  
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte  
Low Enable (BLE) is LOW, then data from the memory location  
specified by the address pins A0 through A17 will appear on  
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory will appear on I/O8 to I/O15. See the Truth Table for a  
complete description of read and write modes.  
• Automatic power-down when deselected  
Functional Description[1]  
The CYK256K16SCCB is a high-performance CMOS pseudo  
static RAM (PSRAM) organized as 256K words by 16 bits that  
supports an asynchronous memory interface. This device  
features advanced circuit design to provide ultra-low active  
current. This is ideal for providing More Battery Life™ (MoBL)  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
256K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
CE2  
CE1  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05526 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 18, 2006  
[+] Feedback  
CYK256K16SCCB  
Pin Configuration[3, 4, 5]  
48-ball VFBGA  
Top View  
1
4
2
5
3
6
A
A
A
2
CE2  
OE  
BLE  
0
1
A
B
C
A
A
I/O BHE  
CE1 I/O  
4
3
0
8
A
A
6
I/O  
I/O  
I/O  
I/O  
5
10  
1
2
9
VCC  
A
V
I/O  
I/O  
3
A17  
D
E
F
SS  
7
11  
VSS  
DNU  
A
16  
V
CC  
I/O  
I/O  
12  
4
A
A
15  
I/O  
I/O  
5
I/O  
I/O  
14  
13  
14  
6
A
A
G
H
I/O  
I/O  
NC  
WE  
13  
12  
15  
7
A
A
A
A
NC  
NC  
10  
9
11  
8
Product Portfolio  
Power Dissipation  
Operating, ICC (mA)  
f = 1 MHz f = fMAX  
VCC Range  
(V)  
Standby, ISB2  
(µA)  
Speed  
(ns)  
Product  
Min.  
Typ.  
Max.  
Typ.[2]  
Max.  
Typ.[2]  
Max.  
Typ.[2]  
Max.  
CYK256K16SCCB  
2.7  
3.0  
3.3  
55  
60  
70  
1
5
14  
8
22  
17  
40  
15  
Notes:  
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V (typ) and T = 25°C.  
CC  
CC  
A
3. Ball H1, G2, H6 are the address expansion pins for the 8-Mb, 16-Mb, and 32-Mb densities, respectively.  
4. NC “no connect”—not connected internally to the die.  
5. DNU (Do Not Use) pins have to be left floating or tied to V to ensure proper application.  
SS  
Document #: 38-05526 Rev. *H  
Page 2 of 10  
[+] Feedback  
CYK256K16SCCB  
DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V  
Maximum Ratings  
Output Current into Outputs (LOW) ............................ 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage ......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-up Current ....................................................> 200 mA  
Ambient Temperature with  
Power Applied ..............................................–40°C to +85°C  
Operating Range  
Supply Voltage to Ground Potential ................ −0.4V to 4.6V  
Range  
Ambient Temperature (TA)  
VCC  
DC Voltage Applied to Outputs  
Industrial  
−25°C to +85°C  
2.7V to 3.3V  
in High-Z State[6, 7, 8] ....................................... −0.4V to 3.7V  
DC Electrical Characteristics (Over the Operating Range)  
CYK256K16SCCB -55, 60, 70  
Parameter  
VCC  
Description  
Test Conditions  
Min.  
2.7  
Typ.[2]  
Max.  
Unit  
V
Supply Voltage  
3.0  
3.3  
VOH  
VOL  
Output HIGH Voltage IOH = −0.1 mA  
Output LOW Voltage IOL = 0.1 mA  
Input HIGH Voltage  
VCC – 0.4  
V
0.4  
V
VIH  
0.8 * VCC  
−0.4  
VCC + 0.4  
0.62  
V
V
VIL  
Input LOW Voltage F = 0  
IIX  
Input Leakage  
Current  
GND < VIN < Vcc  
−1  
+1  
µA  
IOZ  
ICC  
Output Leakage  
Current  
GND < VOUT < Vcc, Output  
Disabled  
−1  
+1  
µA  
VCC Operating  
Supply Current  
f = fMAX = 1/tRC VCC = 3.3V,  
IOUT = 0 mA,  
14 for –55  
14 for –60  
8 for –70  
22 for –55  
22 for –60  
15 for –70  
mA  
CMOS level  
f = 1 MHz  
1 for all speeds 5 for all speeds  
ISB1  
Automatic CE1  
Power-down Current VIN > VCC − 0.2V, VIN < 0.2V,  
—CMOS Inputs  
CE > VCC − 0.2V, CE2 < 0.2V  
150  
250  
µA  
µA  
f = fMAX(Address and Data Only),  
f = 0 (OE, WE, BHE and BLE)  
ISB2  
Automatic CE1  
Power-down Current VIN > VCC − 0.2V or VIN < 0.2V,  
—CMOS Inputs  
CE > VCC − 0.2V, CE2 < 0.2V  
17  
40  
f = 0, VCC = 3.3V  
Capacitance[9]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max.  
Unit  
CIN  
TA = 25°C, f = 1 MHz  
CC = VCC(typ)  
8
8
pF  
pF  
V
COUT  
Thermal Resistance[9]  
Parameter  
Description  
Test Conditions  
VFBGA Unit  
θJA  
θJC  
Thermal Resistance (Junction to Ambient)  
Thermal Resistance (Junction to Case)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance,  
per EIA/JESD51.  
55  
17  
°C/W  
°C/W  
Notes:  
6. V  
7. V  
= V + 0.5V for pulse durations less than 20 ns.  
CC  
= –0.5V for pulse durations less than 20 ns.  
IH(MAX)  
IL(MIN)  
8. Overshoot and undershoot specifications are characterized and are not 100% tested.  
9. Tested initially and after design or process changes that may affect these parameters.  
Document #: 38-05526 Rev. *H  
Page 3 of 10  
[+] Feedback  
CYK256K16SCCB  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
VCC  
VCC  
90%  
OUTPUT  
10%  
GND  
Fall Time = 1 V/ns  
R2  
30 pF  
INCLUDING  
JIG AND  
Rise Time = 1 V/ns  
Equivalent to: THEVENIN EQUIVALENT  
RTH  
SCOPE  
OUTPUT  
VTH  
Parameters  
3.0V VCC  
22000  
22000  
11000  
1.50  
Unit  
Ω
R1  
R2  
Ω
RTH  
VTH  
Ω
V
Switching Characteristics (Over the Operating Range)[10]  
–55  
–60  
–70  
Parameter  
Description  
Min.  
55[14]  
5
Max.  
Min.  
60  
Max.  
Min.  
70  
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
Address to Data Valid  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
55  
60  
70  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
Data Hold from Address Change  
CE1 LOW and CE2 HIGH to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z[11, 12]  
OE HIGH to High Z[11, 12]  
8
10  
55  
25  
60  
25  
70  
35  
5
5
5
5
5
5
25  
25  
25  
CE1 LOW and CE2 HIGH to  
Low Z[11, 12]  
tHZCE  
CE1 HIGH and CE2 LOW to  
High Z[11, 12]  
25  
55  
25  
60  
25  
70  
ns  
tDBE  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[11, 12]  
BLE/BHE HIGH to High-Z[11, 12]  
Address Skew  
ns  
ns  
ns  
ns  
tLZBE  
tHZBE  
5
5
5
10  
0
10  
5
25  
10  
[14]  
tSK  
Write Cycle[13]  
tWC Write Cycle Time  
55  
45  
45  
0
60  
45  
45  
0
70  
60  
55  
0
ns  
ns  
ns  
ns  
ns  
tSCE  
tAW  
tHA  
CE1 LOW and CE2 HIGH to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
tSA  
0
0
0
Notes:  
10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V  
/2, input pulse levels of 0V to V  
and output loading of  
CC(typ)  
CC(typ),  
the specified I /I and 30-pF load capacitance  
OL OH  
11. t  
, t  
, t  
and t  
transitions are measured when the outputs enter a high-impedance state.  
HZOE HZCE HZBE  
HZWE  
12. High-Z and Low-Z parameters are characterized and are not 100% tested.  
13. The internal write time of the memory is defined by the overlap of WE, CE = V , CE = V , BHE and/or BLE =V . All signals must be ACTIVE to initiate a write  
1
IL  
2
IH  
IL  
and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that  
terminates write.  
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t  
is the critical parameter and t is satisfied when the addresses are  
ACE  
SK  
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.  
Document #: 38-05526 Rev. *H  
Page 4 of 10  
[+] Feedback  
CYK256K16SCCB  
Switching Characteristics (Over the Operating Range)[10] (continued)  
–55  
–60  
–70  
Parameter  
tPWE  
Description  
WE Pulse Width  
Min.  
40  
50  
25  
0
Max.  
Min.  
40  
50  
25  
0
Max.  
Min.  
45  
55  
25  
0
Max.  
Unit  
ns  
tBW  
BLE/BHE LOW to Write End  
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High Z[11, 12]  
WE HIGH to Low Z[11, 12]  
ns  
tSD  
ns  
tHD  
ns  
tHZWE  
tLZWE  
25  
25  
25  
ns  
5
5
5
ns  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]  
tRC  
ADDRESS  
t
AA  
tSK  
PREVIOUS DATA VALID  
t
OHA  
DATA OUT  
DATA VALID  
Read Cycle 2 (OE Controlled)[14, 16]  
ADDRESS  
tRC  
tSK  
CE1  
tHZCE  
CE  
2
tACE  
BHE/BLE  
tDBE  
tHZBE  
tLZBE  
OE  
tHZOE  
tDOE  
tLZOE  
HIGH IMPEDANCE  
HIGH  
IMPEDANCE  
DATA OUT  
DATA VALID  
tLZCE  
I
CC  
t
V
CC  
Notes:  
15. Device is continuously selected. OE, CE = V  
16. WE is HIGH for Read Cycle.  
.
IL  
Document #: 38-05526 Rev. *H  
Page 5 of 10  
[+] Feedback  
CYK256K16SCCB  
Switching Waveforms (continued)  
Write Cycle No. 1(WE Controlled)[12, 13, 17, 18, 19]  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
t
BW  
BHE/BLE  
OE  
t
SD  
t
HD  
VALID DATA  
DATAI/O  
DO N’T CARE  
t
HZOE  
Notes:  
17. Data I/O is high impedance if OE > V  
.
IH  
18. If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state.  
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05526 Rev. *H  
Page 6 of 10  
[+] Feedback  
CYK256K16SCCB  
Switching Waveforms (continued)  
Write Cycle 2 (CE1 or CE2 Controlled)[12, 13, 17, 18, 19]  
tWC  
ADDRESS  
CE1  
tSCE  
CE  
2
tSA  
tAW  
tHA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tSD  
VALID DATA  
tHD  
DATA I/O  
DON’T CARE  
tHZOE  
Write Cycle 3 (WE Controlled, OE LOW)[18, 19]  
tWC  
ADDRESS  
CE1  
tSCE  
CE  
2
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
t
HD  
tSD  
VALID DATA  
DON’T CARE  
DATAI/O  
tLZWE  
tHZWE  
Document #: 38-05526 Rev. *H  
Page 7 of 10  
[+] Feedback  
CYK256K16SCCB  
Switching Waveforms (continued)  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18, 19]  
t
WC  
ADDRESS  
CE1  
CE  
2
t
SCE  
AW  
t
t
HA  
tBW  
BH E/BLE  
WE  
t
SA  
tPWE  
t
HD  
t
SD  
DON’T CARE  
DATA I/O  
VALID DATA  
Truth Table[20]  
CE1  
H
CE2  
X
WE  
X
OE  
X
BHE BLE  
Inputs/Outputs  
High Z  
Mode  
Power  
Standby (ISB  
Standby (ISB  
Standby (ISB  
X
X
H
L
X
X
H
L
Deselect/Power-down  
Deselect/Power-down  
Deselect/Power-down  
)
X
L
X
X
High Z  
)
X
X
X
X
High Z  
)
L
H
H
L
Data Out (I/O0–I/O15  
)
Read (Upper Byte and Lower Active (ICC)  
Byte)  
L
L
H
H
H
H
L
L
H
L
L
Data Out (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Read (Upper Byte only)  
Active (ICC  
)
H
Data Out (I/O8–I/O15);  
I/O0–I/O7 in High Z  
Read (Lower Byte only)  
Active (ICC)  
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
X
L
H
L
L
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
H
L
)
L
Data In (I/O0–I/O15  
)
Write (Upper Byte and Lower Active (ICC)  
Byte)  
L
L
H
H
L
L
X
X
H
L
L
Data In (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Write (Lower Byte Only)  
Active (ICC  
)
H
Data In (I/O8–I/O15);  
I/O0 –I/O7 in High Z  
Write (Upper Byte Only)  
Active (ICC)  
Note:  
20. H = Logic HIGH, L = Logic LOW, X = Don’t Care.  
Document #: 38-05526 Rev. *H  
Page 8 of 10  
[+] Feedback  
CYK256K16SCCB  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
55  
CYK256K16SCCBU-55BVI  
CYK256K16SCBU-55BVXI  
CYK256K16SCCBU-60BVI  
CYK256K16SCCBU-70BVI  
CYK256K16SCBU-70BVXI  
51-85150 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm)  
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)  
51-85150 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm)  
51-85150 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm)  
48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free)  
Industrial  
60  
70  
Industrial  
Industrial  
Package Diagram  
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05ꢀ(48X  
A1 CORNER  
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15ꢀ(8X  
51-85150-*D  
SEATING PLANE  
C
MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All  
product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05526 Rev. *H  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
[+] Feedback  
CYK256K16SCCB  
Document History Page  
Document Title: CYK256K16SCCB 4-Mbit (256K x 16) Pseudo Static RAM  
Document Number: 38-05526  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
215621  
218183  
230855  
See ECN  
See ECN  
See ECN  
REF  
REF  
AJU  
New data sheet  
*A  
Changed ball E3 on package pinout from DNU to NC  
*B  
Changed from Advance Information to Preliminary  
Modified MAX limit on DC Input voltage in ‘Maximum Ratings’ section  
Fixed package name typo in ‘Thermal Resistance’ table  
Changed ordering code from CYK256K16SCCB to CYK256K16SCCBU in  
‘Ordering Information’ section  
*C  
*D  
*E  
*F  
*G  
234474  
260330  
298651  
314013  
522566  
See ECN  
See ECN  
See ECN  
See ECN  
See ECN  
SYT  
PCI  
Changed ball E3 on package pinout from NC to DNU.  
Changed from Preliminary to Final  
PCI  
Added 60-ns speed bin  
RKF  
NXR  
Added Pb-Free parts to the Ordering information  
Changed VIL Max spec from 0.4 V to 0.6 V in DC Electrical Characteristics  
table  
*H  
562386  
See ECN  
NXR  
Changed VIL Max spec from 0.6 V to 0.62 V in DC Electrical Characteristics  
table  
Document #: 38-05526 Rev. *H  
Page 10 of 10  
[+] Feedback  
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 		CYK001M16SCAU-70BAXI 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 10 页

CYPRESS

 		CYK001M16SCCA 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 10 页

ETC

 		CYK001M16SCCAU 内存\n[ Memory ] 10 页

CYPRESS

 		CYK001M16SCCAU-55BAI 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 10 页

CYPRESS

 		CYK001M16SCCAU-70BAI 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 10 页

CYPRESS

 		CYK001M16ZCCA 16兆位（ 1M ×16 ）伪静态RAM[ 16-Mbit (1M x 16) Pseudo Static RAM ] 11 页

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