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8Q512K32

型号：

8Q512K32

描述：

16Megabit SRAM MCM[ 16Megabit SRAM MCM ]

品牌：

AEROFLEX[ AEROFLEX CIRCUIT TECHNOLOGY ]

页数：

14 页

PDF大小：

138 K

下载PDF手册
Standard Products  
QCOTSTM UT8Q512K32 16Megabit SRAM MCM  
Data Sheet  
June, 2003  
FEATURES  
INTRODUCTION  
The QCOTSTM UT8Q512K32 Quantified Commercial  
Off-the-Shelf product is a high-performance 2M byte  
(16Mbit) CMOS static RAM multi-chip module (MCM),  
organized as four individual 524,288 x 8 bit SRAMs with a  
common output enable. Memory expansion is provided by  
an active LOW chip enable (En), an active LOW output  
enable (G), and three-state drivers. This device has a power-  
down feature that reduces power consumption by more than  
90% when deselected.  
q
q
25ns maximum (3.3 volt supply) address access time  
MCM contains four (4) 512K x 8 industry-standard  
asynchronous SRAMs; the control architecture allows  
operation as 8, 16, 24, or 32-bit data width  
q
q
TTL compatible inputs and output levels, three-state  
bidirectional data bus  
Typical radiation performance  
- Total dose: 50krads  
- SEL Immune >80 MeV-cm2/mg  
- LETTH(0.25) = >10 MeV-cm2/mg  
- Saturated Cross Section cm2 per bit, 5.0E-9  
- <1E-8 errors/bit-day, Adams 90% geosynchronous  
heavy ion  
Writing to each memory is accomplished by taking the chip  
enable (En) input LOW and write enable ( Wn) inputs LOW.  
Data on the I/O pins is then written into the location  
specified on the address pins (A0 through A18). Reading  
q
q
Packaging options:  
from the device is accomplished by taking the chip enable  
(En) and output enable (G) LOW while forcing write enable  
(Wn) HIGH. Under these conditions, the contents of the  
memory location specified by the address pins will appear  
on the I/O pins.  
- 68-lead dual cavity ceramic quad flatpack (CQFP) -  
(weight 7.37 grams)  
Standard Microcircuit Drawing5962-01533  
- QML T and Q compliant part  
The input/output pins are placed in a high impedance state  
when the device is deselected (En HIGH), the outputs are  
disabled (G HIGH), or during a write operation (En LOW  
and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by  
making Wn along with En a common input to any  
combination of the discrete memory die.  
W3  
W2  
W1  
W0  
E2  
E3  
E0  
E1  
A(18:0)  
G
512K x 8  
512K x 8  
512K x 8  
512K x 8  
DQ(31:24)  
or  
DQ(23:16)  
or  
DQ(15:3)  
or  
DQ(7:0)  
or  
DQ3(7:0)  
DQ2(7:0)  
DQ1(7:0)  
DQ0(7:0)  
Figure 1. UT8Q512K32 SRAM Block Diagram  
DEVICE OPERATION  
Each die in the UT8Q512K32 has three control inputs called  
Enable (En), Write Enable (Wn), and Output Enable (G); 19  
address inputs, A(18:0); and eight bidirectional data lines,  
DQ(7:0). The device enable (En) controls device selection,  
active, and standby modes. Asserting En enables the device,  
causes IDD to rise to its active value, and decodes the 19 address  
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61  
DQ0(0)  
DQ1(0)  
DQ2(0)  
DQ3(0)  
DQ4(0)  
DQ5(0)  
DQ6(0)  
DQ7(0)  
DQ0(2)  
DQ1(2)  
DQ2(2)  
DQ3(2)  
DQ4(2)  
DQ5(2)  
DQ6(2)  
DQ7(2)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
Top View  
inputs to each memory die by selecting the 2,048,000 byte of  
memory. Wn controls read and write operations. During a read  
cycle, G must be asserted to enable the outputs.  
V
V
SS  
SS  
DQ0(1)  
DQ0(3)  
DQ1(3)  
DQ2(3)  
DQ3(3)  
DQ4(3)  
DQ5(3)  
DQ6(3)  
DQ7(3)  
DQ1(1)  
DQ2(1)  
DQ3(1)  
DQ4(1)  
DQ5(1)  
DQ6(1)  
DQ7(1)  
Table 1. Device Operation Truth Table  
G
Wn  
X
En  
1
I/O Mode  
3-state  
Mode  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
X1  
X
1
Standby  
0
1
0
0
Data in  
3-state  
Write  
Read2  
Read  
Figure 2. 25ns SRAM Pinout (68)  
0
1
0
Data out  
Notes:  
PIN NAMES  
1. “X” is defined as a “don’t care” condition.  
2. Device active; outputs disabled.  
A(18:0) Address  
Wn  
G
WriteEnable  
Output Enable  
Power  
READ CYCLE  
DQ(7:0) Data Input/Output  
A combination ofWn greater than V IH (min) withEn and G less  
than VIL (max) defines a read cycle. Read access time is  
En  
VDD  
Device Enable  
measured from the latter of device enable, output enable, or valid  
address to valid data output.  
VSS  
Ground  
SRAM read Cycle 1, the Address Access is initiated by a change  
in address inputs while the chip is enabled with G asserted and  
Wn deasserted. Valid data appears on data outputs DQn(7:0)  
after the specified tAVQV is satisfied. Outputs remain active  
throughout the entire cycle. As long as device enable and output  
enable are active, the address inputs may change at a rate equal  
to the minimum read cycle time (tAVAV).  
SRAM read Cycle 2, the Chip Enable-controlled Access is  
initiated by En going active while G remains asserted, Wn  
remains deasserted, and the addresses remain stable for the  
entire cycle. After the specified tETQV is satisfied, the eight-bit  
word addressed by A(18:0) is accessed and appears at the data  
outputs DQn(7:0).  
SRAM read Cycle 3, the Output Enable-controlled Access is  
initiated by G going active while En is asserted, Wn is  
deasserted, and the addresses are stable. Read access time is  
tGLQV unless tAVQV or tETQV have not been satisfied.  
2
WRITE CYCLE  
TYPICAL RADIATION HARDNESS  
The UT8Q512K32 SRAM incorporates features which allow  
operation in a limited radiation environment.  
A combination of Wn less than VIL(max) and En less than  
VIL(max) defines a write cycle. The state of G is a “don’t care”  
Table 2. Typical Radiation Hardness  
Design Specifications1  
for a write cycle. The outputs are placed in the high-impedance  
state when eitherG is greater than V IH(min), or when Wn is less  
than V (max).  
IL  
Total Dose  
50  
krad(Si) nominal  
Errors/Bit-Day  
Write Cycle 1, the Write Enable-controlled Access is defined  
by a write terminated byWn going high, with En still active.  
The write pulse width is defined by tWLWH when the write is  
Heavy Ion  
Error Rate 2  
<1E-8  
initiated byWn, and by tETWH when the write is initiated byEn.  
Notes:  
Unless the outputs have been previously placed in the high-  
impedance state byG, the user must wait t WLQZ before applying  
1. The SRAM will not latchup during radiation exposure under recommended  
operating conditions.  
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of  
Aluminum.  
data to the eight bidirectional pins DQn(7:0) to avoid bus  
contention.  
Write Cycle 2, the Chip Enable-controlled Access is defined by  
a write terminated by the former ofEn or Wn going inactive.  
The write pulse width is defined by tWLEF when the write is  
initiated by Wn, and by tETEF when the write is initiated by the  
En going active. For the Wn initiated write, unless the outputs  
have been previously placed in the high-impedance state byG,  
the user must wait tWLQZ before applying data to the eight  
bidirectional pins DQn(7:0) to avoid bus contention.  
3
1
ABSOLUTE MAXIMUM RATINGS  
(Referenced to VSS  
)
SYMBOL  
PARAMETER  
DC supply voltage  
LIMITS  
VDD  
-0.5 to 4.6V  
VI/O  
TSTG  
PD  
Voltage on any pin  
-0.5 to 4.6V  
-65 to +150°C  
1.0W (per byte)  
+150°C  
Storage temperature  
Maximum power dissipation  
Maximum junction temperature2  
TJ  
Thermal resistance, junction-to-case3  
DC input current  
QJC  
10°C/W  
II  
±10 mA  
Notes:  
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device  
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability and performance.  
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.  
3. Test per MIL-STD-883, Method 1012.  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
VDD  
PARAMETER  
Positive supply voltage  
Case temperature range  
LIMITS  
3.0 to3.6V  
TC  
-40 to +125°C  
VIN  
DC input voltage  
0V to VDD  
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*  
(-40°C to +125°C) (VDD = 3.3V + 0.3)  
SYMBOL  
PARAMETER  
CONDITION  
MIN  
MAX  
UNIT  
VIH  
High-level input voltage  
(CMOS)  
(CMOS)  
2.0  
V
VIL  
Low-level input voltage  
Low-level output voltage  
Low-level output voltage  
High-level output voltage  
High-level output voltage  
Input capacitance  
0.8  
0.4  
V
V
VOL1  
VOL2  
VOH1  
VOH2  
IOL = 8mA, VDD =3.0V  
IOL = 200mA,VDD =3.0V  
IOH = -4mA,VDD =3.0V  
IOH = -200mA,VDD =3.0V  
¦ = 1MHz @ 0V  
0.08  
V
2.4  
V
VDD-0.10  
V
1
32  
16  
pF  
CIN  
1
Bidirectional I/O capacitance  
¦ = 1MHz @ 0V  
pF  
CIO  
IIN  
Input leakage current  
VSS < VIN < VDD, VDD = VDD (max)  
-2  
-2  
2
2
mA  
mA  
IOZ  
Three-state output leakage current  
0V < VO < VDD  
VDD = VDD (max)  
G = VDD (max)  
2, 3  
Short-circuit output current  
0V < VO < VDD  
-90  
90  
mA  
mA  
IOS  
Supply current operating  
@ 1MHz  
Inputs: VIL = 0.8V,  
VIH = 2.0V  
125  
IDD(OP)  
(per byte)  
IOUT = 0mA  
VDD = VDD (max)  
IDD1(OP) Supply current operating  
Inputs: VIL = 0.8V,  
VIH = 2.0V  
180  
mA  
@40MHz  
(per byte)  
IOUT = 0mA  
VDD = VDD (max)  
-40°C and  
25°C  
IDD2(SB) Nominal standby supply current  
Inputs: VIL = V  
6
mA  
mA  
SS  
@0MHz  
(per byte)  
IOUT = 0mA  
40  
En = VDD - 0.5, VDD = VDD (max)  
VIH = VDD - 0.5V  
+125°C  
Notes:  
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.  
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.  
2. Supplied as a design limit but not guaranteed or tested.  
3. Not more than one output may be shorted at a time for maximum duration of one second.  
5
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*  
(-40°C to +125°C) (VDD = 3.3V + 0.3)  
SYMBOL  
PARAMETER  
MIN  
MAX  
UNIT  
1
Read cycle time  
25  
ns  
tAVAV  
tAVQV  
Read access time  
Output hold time  
25  
ns  
ns  
2
3
3
tAXQX  
2
G-controlled Output Enable time  
ns  
tGLQX  
tGLQV  
G-controlled Output Enable time (Read Cycle 3)  
G-controlled output three-state time  
10  
10  
ns  
ns  
2
tGHQZ  
2,3  
En-controlled Output Enable time  
En-controlled access time  
3
ns  
ns  
ns  
tETQX  
3
25  
10  
tETQV  
1,2,4  
En-controlled output three-state time  
tEFQZ  
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.  
1. Functional test.  
2. Three-state is defined as a 300mV change from steady-state output voltage.  
3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.  
4. The EF (enable false) notation refers to the rising edge ofEn. SEU immunity does not affect the read parameters.  
High Z to Active Levels  
Active to High Z Levels  
VH - 300mV  
VLOAD + 300mV  
}
}
{
{
VLOAD  
VLOAD - 300mV  
VL + 300mV  
Figure 3. 3-Volt SRAM Loading  
6
tAVAV  
A(18:0)  
Previous Valid Data  
Valid Data  
tAVQV  
DQn(7:0)  
Assumptions:  
1. En andG <V (max) and Wn >V (min)  
tAXQX  
IL  
IH  
Figure 4a. SRAM Read Cycle 1: Address Access  
A(18:0)  
En  
tETQV  
tEFQZ  
tETQX  
DQn(7:0)  
DATA VALID  
Assumptions:  
1. G < V (max) and Wn > V (min)  
IL  
IH  
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access  
tAVQV  
A(18:0)  
G
tGHQZ  
tGLQX  
DATA VALID  
DQn(7:0)  
tGLQV  
Assumptions:  
1. En < V (max) andW n >V (min)  
IL  
IH  
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access  
7
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*  
(-40°C to +125°C) (VDD = 3.3V + 0.3)  
SYMBOL  
PARAMETER  
MIN  
MAX  
UNIT  
1
Write cycle time  
25  
ns  
tAVAV  
tETWH  
tAVET  
tAVWL  
tWLWH  
tWHAX  
tEFAX  
Device Enable to end of write  
20  
1
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address setup time for write (En - controlled)  
Address setup time for write (Wn - controlled)  
Write pulse width  
0
20  
2
Address hold time for write (Wn - controlled)  
Address hold time for Device Enable (En - controlled)  
Wn- controlled three-state time  
2
2
10  
tWLQZ  
2
Wn - controlled Output Enable time  
5
ns  
tWHQX  
tETEF  
Device Enable pulse width (En - controlled)  
Data setup time  
20  
15  
2
ns  
ns  
ns  
tDVWH  
2
Data hold time  
tWHDX  
tWLEF  
Device Enable controlled write pulse width  
Data setup time  
20  
15  
ns  
ns  
2
tDVEF  
tEFDX  
Data hold time  
2
20  
5
ns  
ns  
ns  
tAVWH  
Address valid to end of write  
Write disable time  
1
tWHWL  
Notes:  
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.  
1. Functional test performed with outputs disabled (G high).  
2. Three-state is defined as 300mV change from steady-state output voltage.  
8
A(18:0)  
En  
tAVAV  
2
tAVWH  
tETWH  
tWHWL  
Wn  
tAVWL  
tWLWH  
tWHAX  
Qn(7:0)  
tWLQZ  
tWHQX  
Dn(7:0)  
APPLIED DATA  
Assumptions:  
tDVWH  
tWHDX  
1. G < V (max). If G > V (min) then Qn(8:0) will be  
IL  
IH  
in three-state for the entire cycle.  
2. G high for t cycle.  
AVAV  
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access  
9
tAVAV  
3
A(18:0)  
tETEF  
tAVET  
tEFAX  
En  
or  
tAVET  
En  
tETEF  
tEFAX  
tWLEF  
Wn  
APPLIED DATA  
Dn(7:0)  
Qn(7:0)  
tWLQZ  
tDVEF  
tEFDX  
Assumptions & Notes:  
1. G < V (max). If G > V IH (min) then Qn(7:0) will be in three-state for the entire cycle.  
IL  
2. Either En scenario above can occur.  
3. G high for t  
cycle.  
AVAV  
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access  
CMOS  
90%  
V
-0.05V 90%  
DD  
300 ohms  
10%  
10%  
V
= 1.55  
LOAD  
0.5V  
< 5ns  
< 5ns  
50pF  
Input Pulses  
Notes:  
1. 50pF including scope probe and test socket capacitance.  
2. Measurement of data output occurs at the low to high or high to low transition mid-point  
(i.e., CMOS input = V /2).  
DD  
Figure 6. AC Test Loads and Input Waveforms  
10  
DATA RETENTION MODE  
VDD  
50%  
tEFR  
50%  
tR  
VDR > 2.0V  
En  
Figure 7. Low VDD Data Retention Waveform  
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)  
(1 Second Data Rentention Test)  
SYMBOL  
PARAMETER  
MINIMUM  
MAXIMUM UNIT  
VDR  
VDD for data retention  
2.0  
--  
V
1,2  
Data retention current (per byte)  
Chip select to data retention time  
Operation recovery time  
--  
0
2.0  
mA  
IDDR  
1,3  
ns  
ns  
tEFR  
1,3  
tAVAV  
tR  
Notes:  
1. En = V - .2V, all other inputs = V  
or V .  
SS  
DD  
DR  
o
2. Data retention current (I  
) Tc = 25 C.  
DDR  
3. Not guaranteed or tested.  
o
o
4. V = T=-40 C and 125 C.  
DR  
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)  
(10 Second Data Retention Test, TC=-40oC and +125oC)  
SYMBOL  
PARAMETER  
VDD for data retention  
MINIMUM  
MAXIMUM UNIT  
1
3.0  
3.6  
V
ns  
ns  
VDD  
2, 3  
Chip select to data retention time  
Operation recovery time  
0
tEFR  
2, 3  
tAVAV  
tR  
Notes:  
1. Performed at V  
(min) and V  
(max).  
DD  
DD  
2. En = V , all other inputs = V  
or V  
.
SS  
SS  
DR  
3. Not guaranteed or tested.  
11  
PACKAGING  
Notes:  
1. Package shipped with non-conductive  
strip (NCS). Leads are not trimmed.  
2. Total weight approx. 7.37g.  
Figure 8. 68-pin Ceramic FLATPACK  
12  
ORDERING INFORMATION  
512K32 16Megabit SRAM MCM:  
UT8Q512K32 -* *  
*
*
Lead Finish:  
(C) Gold  
=
Screening:  
(P) = Prototype flow  
o
o
(W) = Extended Industrial Temperature Range Flow (-40 C to +125 C)  
Package Type:  
(S) = 68-lead dual cavity CQFP  
Device Type:  
- = 25ns access, 3.3V operation  
Aeroflex UTMC Core Part Number  
Notes:  
1. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY.  
2. Extended Industrial Temperature Range Flow per UTMC Manufacturing Flows document. Devices are tested at -40 C to +125 C. Radiation neither  
tested nor guaranteed. Gold lead finish only.  
o
o
13  
512K32 16Megabit SRAM MCM: SMD  
5962 - 01533 **  
* * *  
Lead Finish:  
(C) Gold  
=
Case Outline:  
(X) 68-lead dual cavity CQFP  
=
Class Designator:  
(T)  
(Q)  
=
=
QML Class T  
QML Class Q  
Device Type  
o
o
01 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40 C to +125 C)  
Drawing Number: 01533  
Total Dose  
(-) =none  
(D) = 1E4 (10krad(Si))  
(L) = 5E4 (50krad(Si)) (contact factory)  
(P) = 3E4 (30krad(Si)) (contact factory)  
Federal Stock Class Designator: No Options  
Notes:  
1. Total dose radiation must be specified when ordering. Gold lead finish only.  
2. Only Extended Industrial Temperature -40C to +125C. No military temp. test available.  
14  
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