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YWW7640I

型号：

YWW7640I

描述：

安全SerialFlash[ Secure SerialFlash ]

品牌：

ICMIC[ IC MICROSYSTEMS ]

页数：

14 页

PDF大小：

320 K

下载PDF手册
TM  
ICmic  
512 x 8 bit  
This X76F400 device has been acquired by  
IC MICROSYSTEMS from Xicor, Inc.  
IC MICROSYSTEMS  
4K  
X76F400  
Secure SerialFlash  
FEATURES  
DESCRIPTION  
•64-bit password security  
•One array (496 bytes) two passwords (16 bytes)  
The X76F400 is a password access security supervisor,  
containing one 3968-bit Secure Serial Flash array.  
—Read password  
—Write password  
Access to the memory array can be controlled by two 64-bit  
passwords. These passwords protect read and  
write operations of the memory array.  
•Programmable passwords  
•Retry counter register  
The X76F400 features a serial interface and software  
protocol allowing operation on a popular 2-wire bus.  
—Allows 8 tries before clearing of the array  
•32-bit response to reset (RST input)  
•8 byte sector write mode  
The bus signals are a clock input (SCL) and a bi-directional  
data input and output (SDA).  
•1MHz clock rate •2-wire  
serial interface •Low  
power CMOS  
The X76F400 also features a synchronous response to  
reset, providing an automatic output of a hard-wired  
—2.5 to 5.5V operation  
—Standby current less than 1µA  
—Active current less than 3 mA  
32-bit data stream, thereby meeting the industry standard  
for memory cards.  
The X76F400 utilizes Xicor’s proprietary Direct Write™  
•High reliability endurance:  
—100,000 write cycles  
cell, providing a minimum endurance of 100,000  
cycles and a minimum data retention of 100 years.  
•Data retention: 100 years  
•Available in:  
—8-lead, SOIC,TSSOP  
BLOCK DIAGRAM  
Retry Counter  
Data Transfer  
Erase Logic  
SCL  
SDA  
Array Access  
Enable  
Interface  
Logic  
496 Byte  
EEPROM Array  
Password Array  
and Password  
Verification Logic  
RST  
ISO Reset  
Response Register  
Characteristics subject to change without notice. 1 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
PIN DESCRIPTIONS  
Serial Clock (SCL)  
If the X76F400 is in a nonvolatile write cycle a “no ACK”  
(SDA = High) response will be issued in  
response to loading of the command byte. If a stop is issued  
prior to the nonvolatile write cycle, the write  
The SCL input is used to clock all data into and out of the  
device.  
operation will be terminated; the part will then reset and  
enter into a standby mode.  
Serial Data (SDA)  
(The basic sequence is illustrated in Figure 1.)  
SDA is an open drain serial data input/output pin. During a  
read cycle, data is shifted out on this pin. During  
PIN NAMES  
a write cycle, data is shifted in on this pin. In all other  
cases, this pin is in a high impedance state.  
Symbol  
SDA  
Description  
Serial Data Input/Output  
Serial Clock Input  
Reset Input  
Reset (RST)  
SCL  
RST is a device reset pin. When RST is pulsed high, the  
X76F400 will output 32 bits of fixed data, which  
RST  
V
Supply Voltage  
Ground  
CC  
conforms to the standard for “synchronous response-  
to-reset.” The part must not be in a write cycle for the  
V
SS  
response-to-reset to occur. See Figure 7. If power is  
interrupted during the response-to-reset, the response-  
NC  
No Connect  
to-reset will be aborted and the part will return to the  
standby state. The response to reset is “mask  
programmable” only!  
PIN CONFIGURATION  
SOIC  
DEVICE OPERATION  
VCC  
VSS  
1
8
7
6
5
RST  
NC  
SDA  
NC  
2
The X76F400 memory array consists of 62 8-byte sectors.  
Read or write access to the array always begins at  
SCL  
NC  
3
4
the first address of the sector. Read operations then can  
continue indefinitely. Write operations must total 8 bytes.  
There are two primary modes of operation for the  
X76F400; Protected READ and protected WRITE. Pro-  
TSSOP  
VCC  
NC  
NC  
VSS  
RST  
SCL  
SDA  
1
2
8
7
6
5
tected operations must be performed with one of two 8- byte  
passwords.  
3
4
The basic method of communication for the device is  
generating a start condition, then transmitting a com-  
NC  
mand, followed by the correct password. All parts will be  
shipped from the factory with all passwords equal to ‘0.’  
After each transaction is completed, the X76F400 will  
reset and enter into a standby mode. This will also be  
The user must perform ACK polling to determine the  
validity of the password, prior to starting a data transfer  
the response if an unsuccessful attempt is made to  
access a protected array.  
(see Acknowledge Polling). Only after the correct password  
is accepted, and an ACK polling has been  
performed, can the data transfer occur. See Figure 1.  
To ensure the correct communication, RST must  
remain LOW under all conditions except when running  
a “response-to-reset sequence”.  
Data is transferred in 8-bit segments, with each transfer  
being followed by an ACK, generated by the receiving  
device.  
Characteristics subject to change without notice. 2 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
Figure 1. X76F400 Device Operation  
Clock and Data Conventions  
Data states on the SDA line can change only during SCL  
LOW. SDA changes during SCL HIGH are  
Load Command/Address Byte  
reserved for indicating start and stop conditions. Refer to  
Figures 2 and 3.  
Load 8-Byte  
Password  
Start Condition  
All commands are preceded by the start condition, which  
is a HIGH to LOW transition of SDA when SCL is  
Verify Password  
HIGH. The X76F400 continuously monitors the SDA and  
SCL lines for the start condition, and will not  
Acceptance by  
Use of ACK Polling  
respond to any command until this condition is met.  
A start may be issued to terminate the input of a control  
byte or the input data to be written. This will reset  
Read/Write  
Data Bytes  
the device and leave it ready to begin a new read or write  
command. Because of the push/pull output, a  
start cannot be generated while the part is outputting data.  
Starts are inhibited while a write is in progress.  
Retry Counter  
The X76F400 contains a retry counter. The retry  
counter allows 8 accesses with an invalid password  
Stop Condition  
before any action is taken. The counter will increment with  
any combination of incorrect passwords. If the  
All communications must be terminated by a stop con-  
dition. The stop condition is a LOW to HIGH transition  
retry counter overflows, the memory area and both of the  
passwords are cleared to “0.” If a correct password  
of SDA when SCL is HIGH. The stop condition is also used  
to reset the device during a command or data  
is received prior to retry counter overflow, the retry  
counter is reset and access is granted.  
input sequence, leaving the device in the standby  
power mode. As with starts, stops are inhibited when  
outputting data and while a write is in progress.  
Device Protocol  
The X76F400 supports a bi-directional bus oriented  
protocol. The protocol defines any device that sends  
Acknowledge  
Acknowledge is a software convention used to indicate  
successful data transfer. The transmitting device, either  
data onto the bus as a transmitter and the receiving  
device as a receiver. The device controlling the transfer  
master or slave, will release the bus after transmitting 8 bits.  
During the ninth clock cycle the receiver will pull  
is a master and the device being controlled is the slave.  
The master will always initiate data transfers and  
the SDA line LOW to acknowledge that it received the 8  
bits of data.  
provide the clock for both transmit and receive operations.  
Therefore, the X76F400 will be considered a  
slave in all applications.  
The X76F400 will respond with an acknowledge after  
recognition of a start condition and its slave address. If  
both the device and a write condition have been  
selected, the X76F400 will respond with an acknowl-  
edge after the receipt of each subsequent 8-bit word.  
Figure 2. Data Validity  
SCL  
SDA  
Data Stable  
Data  
Change  
Characteristics subject to change without notice. 3 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
Figure 3. Definition of Start and Stop Conditions  
SCL  
SDA  
START Condition  
STOP Condition  
Table 1. X76F400 Instruction Set  
Command After Start  
Command Description  
Password Used  
Write  
1 S S S S S S 0  
2
Sector Write  
5
4
3
1
0
1 S S S S S S 1  
2
Sector Read  
Read  
5
4
3
1
0
1 1 1 1 1 1 0 0  
1 1 1 1 1 1 1 0  
0 1 0 1 0 1 0 1  
Change Write Password  
Change Read Password  
Password ACK Command  
Write  
Write  
None  
with the nonvolatile write operation, it will issue a “no-  
ACK” in response. If the nonvolatile write operation is  
Illegal command codes will be disregarded. The part will  
respond with a “no-ACK” to the illegal byte and  
completed, an “ACK” will be returned and the host can then  
proceed with the rest of the protocol.  
then return to the standby mode. All write/read operations  
require a password.  
PROGRAM OPERATIONS  
Sector Write  
Data ACK Polling Sequence  
Write Sequence  
Completed Enter ACK  
The sector write mode requires issuing the 8-bit write  
command followed by the password and then the data  
Polling  
bytes transferred as illustrated in Figure 4. The write  
command byte contains the address of the sector to be  
Issue START  
written. Data is written starting at the first address of a  
sector and 8 bytes must be transferred. After the last  
byte to be transferred is acknowledged, a stop condition is  
issued which starts the nonvolatile write cycle. If  
Issue New  
Command Code  
more or less than 8 bytes are transferred, the data in the  
sector remains unchanged.  
ACK Polling  
NO  
ACK  
Returned?  
Once a stop condition is issued to indicate the end of the  
host’s write sequence, the X76F400 initiates the  
internal nonvolatile write cycle. In order to take advantage of  
the typical 5ms write cycle, ACK polling can  
YES  
PROCEED  
begin immediately. This involves issuing the start condition  
followed by the new command code of 8 bits  
(first byte of the protocol). If the X76F400 is still busy  
Characteristics subject to change without notice. 4 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
READ OPERATIONS  
After the password sequence, there is always a nonvola- tile  
write cycle. This is done to discourage random  
Read operations are initiated in the same manner as  
write operations but with a different command code.  
guesses of the password if the device is being tampered with.  
In order to continue the transaction, the X76F400  
requires the master to perform a password ACK polling  
sequence with the specific command code of 55h. As  
Sector Read  
With sector read, a sector address is supplied with the read  
command. Once the password has been  
with regular acknowledge polling the user can either time  
out for 10ms and then issue the ACK polling once,  
acknowledged data may be read from the sector. An  
acknowledge must follow each 8-bit data transfer. A  
or continuously loop as described in the flow.  
If the password inserted is correct, the nonvolatile cycle  
in response to the password ACK polling  
sequence is over, and an “ACK” is returned.  
read operation always begins at the first byte in the  
sector, but may stop at any time. Random accesses to  
the array are not possible. Continuous reading from the  
array will return data from successive sectors. After  
If the password inserted is incorrect, a “no ACK” is  
returned, even if the nonvolatile cycle is over. There-  
reading the last sector in the array, the address is auto-  
matically set to the first sector in the array and data can  
fore, the user cannot be certain that the password is  
incorrect until the 10ms write cycle time has elapsed.  
continue to be read out. After the last bit has been read,  
a stop condition is generated without sending a  
preceding acknowledge.  
Password ACK Polling Sequence  
Password Load  
Completed Enter ACK  
Polling  
Issue START  
Issue Password  
ACK Command  
NO  
ACK  
Returned?  
YES  
PROCEED  
Characteristics subject to change without notice. 5 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
Figure 4. Sector Write Sequence (Password Required)  
Write  
Password  
7
Write  
Password  
0
Host  
Commands  
Write  
Command  
Wait t  
WC  
OR  
Password  
ACK  
Command  
SDA  
S
X76F400  
Response  
If ACK, then  
Password Matches  
Host  
Commands  
Password ACK  
Command  
Wait tWC Data  
ACK Polling  
P
S
X76F400  
Response  
Figure 5. Acknowledge Polling  
8th  
CLK  
th CLK of  
8th  
Pwd. Byte  
SCL  
‘ACK’  
CLK  
‘ACK’  
CLK  
8
8th Bit  
SDA  
‘ACK’  
ACK or  
No ACK  
START  
Condition  
Figure 6. Sector Read Sequence (Password Required)  
Read  
Password  
7
Read  
Password  
0
Host  
Commands  
Read  
Command  
Wait t  
WC  
OR  
Password  
ACK  
Command  
SDA  
S
X76F400  
Response  
If ACK, then  
Password Matches  
Host  
Commands  
Password ACK  
Command  
P
S
Data n  
Data 0  
X76F400  
Response  
Characteristics subject to change without notice. 6 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
PASSWORDS  
After initiating a nonvolatile write cycle, the RST pin must  
not be pulsed until the nonvolatile write cycle is  
Passwords are changed by sending the “change read  
password” or “change write password” commands in a  
complete. If not, the ISO response will not be activated.  
If the RST is pulsed HIGH and the CLK is within  
normal sector write operation. A full 8 bytes containing the  
new password must be sent, following successful  
the RST pulse (meet the t  
NOL  
spec.) in the middle of an  
ISO transaction, it will output the 32 bit sequence again  
(starting at bit 0). Otherwise, this aborts the ISO  
transmission of the current write password and a valid  
password ACK response. The user can use a repeated  
operation and the part returns to standby state. If the RST  
is pulsed HIGH and the CLK is outside the RST  
ACK polling command to check that a new password has  
been written correctly. An ACK indicates that the  
pulse (in the middle of an ISO transaction), this aborts the  
ISO operation and the part returns to standby  
state.  
new password is valid.  
There is no way to read any of the passwords.  
If power is interrupted during the response-to-reset, the  
response-to-reset will be aborted and the part will  
RESPONSE-TO-RESET (DEFAULT = 19 40 AA 55)  
return to the standby state. A response-to-reset is not  
available during a nonvolatile write cycle.  
The ISO Response-to-reset is controlled by the RST and  
CLK pins. When RST is pulsed high during a clock  
pulse, the device will output 32 bits of data, one bit per  
clock, and it resets to the standby state. This conforms  
to the ISO standard for “synchronous response to reset.”  
The part must not be in a write cycle for the  
response-to-reset to occur.  
Figure 7. Response to RESET (RST)  
RST  
SCK  
0
0
1
0
1
SO  
0
0
1
1
00  
1
1
0
10  
0
0
0
0000  
0
0
1
0
11  
0
1
1
MSB  
LSB  
MSB LSB  
LSB  
MSB  
MSB  
LSB  
2
3
Byte  
0
1
Characteristics subject to change without notice. 7 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
ABSOLUTE MAXIMUM RATINGS  
COMMENT  
Temperature under bias....................–65°C to +135°C  
Storage temperature ........................–65°C to +150°C  
Stresses above those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device.  
Voltage on any pin with  
respect to V  
This is a stress rating only; functional operation of the  
device (at these or any other conditions above those  
.........................................–1V to +7V  
SS  
D.C. output current............................................... 5mA  
Lead temperature (soldering, 10 seconds).........300°C  
listed in the operational sections of this specification) is not  
implied. Exposure to absolute maximum rating conditions  
for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
Temperature  
Commercial  
Industrial  
Min.  
0°C  
Max.  
+70°C  
+85°C  
Supply Voltage  
X76F400  
Limits  
4.5V to 5.5V  
2.5V to 5.5V  
–40°C  
X76F400 – 2.5  
D.C. OPERATING CHARACTERISTICS  
(Over the recommended operating conditions unless otherwise specified.)  
Limits  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Test Conditions  
I
V
Supply current  
CC  
(Read)  
1
mA  
f
= V  
x 0.1/V  
x 0.9 Levels @ 400 kHz,  
CC1  
SCL  
CC  
CC  
SDA = Open  
RST = V  
SS  
CC  
(3)  
I
V
3
mA  
f = V  
SCL  
x 0.1/V  
x 0.9 Levels @ 400 kHz,  
Supply current  
CC2  
CC  
(Write)  
CC  
SDA = Open  
RST = V  
SS  
(1)  
I
V
1
1
µA  
µA  
V
f
= V  
x 0.1, V = V x 0.9  
CC IH CC  
Supply current  
SB1  
CC  
(Standby)  
IL  
= 400 kHz, f  
= 400 kHz  
SCL  
SDA  
(1)  
I
V
Supply current  
CC  
(Standby)  
V
= V  
= V  
SCC CC  
SB2  
SDA  
Other = GND or VCC  
–0.3V  
I
V
= V to V  
IN CC  
Input leakage current  
Output leakage current  
Input LOW voltage  
Input HIGH voltage  
Output LOW voltage  
10  
10  
µA  
µA  
V
LI  
SS  
= V to V  
CC  
I
V
OUT  
LO  
SS  
(2)  
V
V
V
x 0.1  
–0.5  
CC  
IL  
(2)  
V
V
x 0.9  
+ 0.5  
CC  
V
CC  
IH  
V
OL  
I
= 3mA  
OL  
0.4  
V
CAPACITANCE T = +25°C, f = 1MHz, V = 5V  
A
CC  
Symbol  
Test  
Max.  
Unit  
pF  
Conditions  
(3)  
C
V
I/O  
= 0V  
= 0V  
Output capacitance (SDA)  
8
6
OUT  
(3)  
C
V
IN  
Input capacitance (RST, SCL)  
pF  
IN  
Notes:  
(1)Must perform a stop command after a read command prior to measurement (2)V  
min. and V  
IL  
IH  
max. are for reference only and are not tested  
(3)This parameter is periodically sampled and not 100% test  
Characteristics subject to change without notice. 8 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
EQUIVALENT A.C. LOAD CIRCUIT  
A.C. TEST CONDITIONS  
V
CC  
x 0.1 to V x 0.9  
CC  
Input pulse levels  
5V  
3V  
Input rise and fall times  
Input and output timing level  
Output load  
10ns  
1.53KΟ  
1.3KΟ  
V
CC  
x 0.5  
Output  
Output  
100pF  
100pF  
100pF  
AC CHARACTERISTICS (T = -40°C to +85°C, V = +2.5V to +5.5V, unless otherwise specified)  
CC  
A
Symbol  
Parameter  
Min.  
Max.  
1
Unit  
MHz  
µs  
µs  
µs  
µs  
µs  
µs  
ns  
f
SCL clock frequency  
0
0.1  
SCL  
t
SCL LOW to SDA data out valid  
Time the Bus must be free before a new transmission can start  
Start condition hold time  
0.9  
AA(2)  
t
1.2  
BUF  
t
0.6  
HD:STA  
t
Clock LOW period  
1.2  
LOW  
t
Clock HIGH period  
0.6  
HIGH  
t
Start condition setup time (for a repeated start condition)  
Data in hold time  
0.6  
SU:STA  
t
10  
HD:DAT  
t
Data in setup time  
100  
20+0.1XC  
20+0.1XC  
0.6  
ns  
SU:DAT  
(1)  
(1)  
t
SDA and SCL rise time  
300  
300  
ns  
R
b
b
t
SDA and SCL fall time  
ns  
F
t
Stop condition setup time  
µs  
µs  
ns  
SU:STO  
t
Data out hold time  
0
DH  
t
RST to SCL non-overlap  
500  
0
NOL  
t
RST LOW to SDA valid during response to reset  
CLK LOW to SDA valid during response to reset  
RST high time  
450  
450  
ns  
RDV  
t
0
ns  
CDV  
t
1.5  
µs  
ns  
RST  
t
RST setup time  
500  
SU:RST  
Notes: (1)C = total capacitance of one bus line in pF  
b
(2)t = 1.1µs Max below V  
AA  
= 2.5V.  
CC  
RESET AC SPECIFICATIONS  
Power Up Timing  
Symbol  
Parameter  
Min.  
Typ.(2)  
Max.  
Unit  
(1)  
t
Time from power up to read  
Time from power up to write  
1
5
ms  
ms  
PUR  
(1)  
t
PUW  
Notes: (1)Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled  
and not 100% tested.  
(2)Typical values are for TA = 25°C and VCC = 5.0V  
Characteristics subject to change without notice. 9 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
Nonvolatile Write Cycle Timing  
Symbol  
Parameter  
Min.  
Typ.(1)  
Max.  
Unit  
(1)  
WC  
t
Write cycle time  
5
10  
ms  
Note:  
(1)tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the  
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.  
Bus Timing  
tHIGH  
tLOW  
tR  
tF  
SCL  
tSU:STA  
tHD:STA  
tHD:DAT  
tSU:DAT  
tSU:STO  
SDA IN  
tAA  
tDH  
tBUF  
SDA OUT  
Write Cycle Timing  
SCL  
SDA  
8th Bit of Last Byte  
ACK  
tWC  
STOP  
Condition  
START  
Condition  
RST Timing Diagram—Response to a Synchronous Reset  
RST  
tRST  
t
HIGH_RST  
tNOL  
tNOL  
st  
nd  
2
CLK  
Pulse  
rd  
3
1
CLK  
CLK  
I/O  
CLK  
Pulse  
t
LOW_RST  
Pulse  
tSU:RST  
tCDV  
tRDV  
Data Bit (2)  
Data Bit (1)  
Characteristics subject to change without notice. 10 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS  
100  
V
CCMAX  
------------------------=-- 1.8KΟ  
OLMIN  
80  
R
=
MIN  
I
RMAX  
60  
40  
20  
t
R
------------------  
R
=
MAX  
C
RMIN  
BUS  
40 60 80 100  
Bus Capacitance in pF  
tR = maximum allowable SDA rise time  
20  
Characteristics subject to change without notice. 11 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
PACKAGING INFORMATION  
8-Lead Plastic Small Outline Gull Wing Package Type S  
0.150 (3.80) 0.228 (5.80)  
0.158 (4.00) 0.244 (6.20)  
Pin 1 Index  
Pin 1  
0.014 (0.35)  
0.019 (0.49)  
0.188 (4.78)  
0.197 (5.00)  
(4X) 7°  
0.053 (1.35)  
0.069 (1.75)  
0.004 (0.19)  
0.010 (0.25)  
0.050 (1.27)  
0.050" Typical  
0.010 (0.25)  
0.020 (0.50)  
X 45°  
0.050"  
Typical  
0°- 8°  
0.0075 (0.19)  
0.010 (0.25)  
0.250"  
0.016 (0.410)  
0.037 (0.937)  
0.030"  
Typical  
8 Places  
FOOTPRINT  
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)  
Characteristics subject to change without notice. 12 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
PACKAGING INFORMATION  
8-Lead Plastic, TSSOP, Package Type V  
.025 (.65) BSC  
.169  
(4.3) .177  
(4.5)  
.252 (6.4) BSC  
.114  
(2.9) .122  
(3.1)  
.047 (1.20)  
.002  
(.05) .006  
(.15)  
.0075  
(.19) .0118  
(.30)  
.010 (.25)  
Gage Plane  
0°– 8°  
Seating Plane  
.019  
(.50) .029  
(.75)  
Detail A (20X)  
(7.72)  
(4.16)  
(1.78)  
(0.42)  
.031  
(.80) .041  
(1.05)  
(0.65)  
All Measurements Are Typical  
See Detail “A”  
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)  
Characteristics subject to change without notice. 13 of 14  
REV 1.0 7/5/00  
www.icmic.com  
X76F400  
Ordering Information  
X76F400  
P
T
G –V  
V
Limits  
CC  
Blank = 5V 10%  
2.5 = 2.5V to 5.5V  
Device  
RoHS Compliant Lead Free package  
Blank – Standard package. Non lead free  
Temperature Range  
Blank = Commercial = 0°C to +70°C  
I = Industrial= –40°C to +85°C  
Package  
S8 = 8-Lead SOIC  
V8 = 8-Lead TSSOP  
H = Die in waffle packs (Contact Factory)  
W = Die in wafer form (Contact Factory)  
Part Mark Convention  
8-Lead SOIC  
8-Lead TSSOP  
YWW  
7640XX  
X76F400 XG  
XX  
Blank = 8-Lead SOIC  
G = RoHS compliant lead free  
Blank = 4.5 to 5.5V, 0 to 70°C  
I = 4.5 to 5.5V, -40 to +85°C  
AE = 2.5 to 5.5V, 0 to 70°C  
AF = 2.5 to 5.5V, -40 to +85°C  
AE = 2.5 to 5.5V, 0 to +70°C  
AF = 2.5 to 5.5V, -40 to +85°C  
Blank = 4.5 to 5.5V, 0 to +70°C  
I = 4.5 to 5.5V, -40 to +85°C  
©Xicor, Inc. 2000 Patents Pending  
LIMITED WARRANTY  
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory,  
implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of  
merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice.  
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.  
TRADEMARK DISCLAIMER:  
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others  
belong to their respective owners.  
U.S. PATENTS  
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706;  
4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774;  
5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.  
LIFE RELATED POLICY  
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and  
correction, redundancy and back-up features to prevent such an occurrence.  
Xicor’s products are not authorized for use in critical components in life support devices or systems.  
1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to  
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical  
component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or effectiveness.  
Characteristics subject to change without notice. 14 of 14  
REV 1.0 7/5/00  
www.icmic.com  
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