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CYP15G0401TB-BGC

型号：

CYP15G0401TB-BGC

描述：

四路的HOTLink II™变送器[ Quad HOTLink II⑩ Transmitter ]

品牌：

CYPRESS[ CYPRESS ]

页数：

30 页

PDF大小：

286 K

下载PDF手册
PRELIMINARY  
CYP15G0401TB  
Quad HOTLink II™ Transmitter  
• Single 3.3V supply  
Features  
• 256-ball thermally enhanced BGA  
• Pb free package option available  
• 0.25µ BiCMOS technology  
• Quadtransmitterfor195to1500MBaudserialsignaling  
rate  
— Aggregate throughput of 6 GBits/second  
• Second-generation HOTLink® technology  
• Compliant to multiple standards  
Functional Description  
The CYP15G0401TB Quad HOTLink II™ Transmitter is a  
point-to-point or point-to-multipoint communications building  
block allowing the transfer of data over high-speed serial links  
(optical fiber, balanced, and unbalanced copper transmission  
lines) at signaling speeds ranging from 195-to-1500 MBaud  
per serial link.  
— ESCON, DVB-ASI, Fibre Channel and Gigabit  
Ethernet (IEEE802.3z)  
— 8B/10B encoded or 10-bit unencoded data  
• Selectable parity check  
• Selectable input clocking options  
• Synchronous LVTTL parallel interface  
• Optional Phase Align Buffer in Transmit Path  
Each transmitter accepts parallel characters in an Input  
Register, encodes each character for transport, and converts  
it to serial data. Figure 1 illustrates typical connections  
between independent host systems and corresponding  
CYP15G0401TB and CYP15G0401RB parts.  
• Internal phase-locked loop (PLL) with no external PLL  
components  
As a second-generation HOTLink device, the CYP15G0401TB  
extends the HOTLink family with enhanced levels of  
integration and faster data rates, while maintaining serial-link  
compatibility (data, command, and BIST) with other HOTLink  
devices. The transmitters (TX) of the CYP15G0401TB Quad  
HOTLink II consist of four byte-wide channels. Each channel  
can accept either eight-bit data characters or pre-encoded  
10-bit transmission characters. Data characters are passed  
from the Transmit Input Register to an embedded 8B/10B  
Encoder to improve their serial transmission characteristics.  
These encoded characters are then serialized and output from  
dual Positive ECL (PECL)-compatible differential trans-  
mission-line drivers at a bit-rate of either 10- or 20-times the  
input reference clock. The integrated 8B/10B Encoder may be  
bypassed for systems that present externally encoded or  
scrambled data at the parallel interface.  
• Dual differential PECL-compatible serial outputs per  
channel  
— Source matched for 50Ω transmission lines  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
• Compatible with  
— fiber-optic modules  
— copper cables  
— circuit board traces  
• JTAG boundary scan  
• Built-In Self-Test (BIST) for at-speed link testing  
• Low power 1.9W @ 3.3V typical  
Serial Link  
10  
10  
10  
10  
10  
Serial Link  
10  
10  
10  
Serial Link  
Serial Link  
Backplane or  
Cabled  
Connections  
Figure 1. HOTLink II System Connections  
Cypress Semiconductor Corporation  
Document #: 38-02112 Rev. **  
•
3901 North First Street  
•
San Jose  
,
CA 95134  
•
408-943-2600  
Revised February 14, 2005  
PRELIMINARY  
CYP15G0401TB  
The parallel input interface may be configured for numerous  
forms of clocking to provide the highest flexibility in system  
architecture.  
HOTLink II devices are ideal for a variety of applications where  
parallel interfaces can be replaced with high-speed,  
point-to-point serial links. Some applications include  
interconnecting backplanes on switches, routers, servers and  
video transmission systems.  
Each transmitter contains an independent BIST pattern  
generator. This BIST hardware allows at-speed testing of the  
high-speed serial data paths in each transmit section, and  
across the interconnecting links.  
CYP15G0401TB Transmitter Logic Block Diagram  
x10  
x10  
x10  
x10  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Phase  
Align  
Buffer  
Encoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Serializer  
Serializer  
Serializer  
Serializer  
TX  
TX  
TX  
TX  
Document #: 38-02112 Rev. **  
Page 2 of 30  
PRELIMINARY  
CYP15G0401TB  
Transmit Path Block Diagram  
REFCLK+  
REFCLK–  
TXRATE  
TRSTZ  
Transmit PLL  
Clock Multiplier  
Bit-rate Clock  
BISTLE  
SPDSEL  
Character-Rate Clock  
TXCLKO+  
TXCLKO–  
BOE[7:0]  
BIST Enable  
Latch  
2
Transmit  
Mode  
TXMODE[1:0]  
Output  
Enable  
Latch  
OELE  
4
TXCKSEL  
TXPERA  
8
SCSEL  
12  
10  
12  
12  
OUTA1+  
OUTA1–  
TXDA[7:0]  
8
TXOPA  
OUTA2+  
OUTA2–  
2
TXCTA[1:0]  
H M L  
TXCLKA  
TXPERB  
10  
12  
TXDB[7:0]  
8
11  
11  
OUTB1+  
OUTB1–  
TXOPB  
2
OUTB2+  
OUTB2–  
TXCTB[1:0]  
H M L  
TXCLKB  
TXPERC  
12  
10  
11  
11  
OUTC1+  
OUTC1–  
TXDC[7:0]  
8
TXOPC  
OUTC2+  
OUTC2–  
2
TXCTC[1:0]  
H M L  
TXCLKC  
TXPERD  
10  
12  
TXDD[7:0]  
8
11  
11  
OUTD1+  
OUTD1–  
TXOPD  
OUTD2+  
OUTD2–  
TXCTD[1:0]  
H M L  
TXCLKD  
TXRST  
TMS  
TCLK  
TDI  
JTAG  
Boundary  
Scan  
Controller  
PARCTL  
TDO  
Document #: 38-02112 Rev. **  
Page 3 of 30  
PRELIMINARY  
CYP15G0401TB  
[1]  
Pin Configuration (Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
N/C  
OUT  
C1-  
N/C  
OUT  
C2-  
V
N/C  
OUT  
D1-  
GND  
GND  
OUT  
D2-  
GND  
OUT  
A1-  
GND  
N/C  
OUT  
A2-  
V
V
V
V
N/C  
OUT  
B1-  
N/C  
OUT  
B2-  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
A
B
C
D
E
F
V
OUT  
C1+  
V
V
V
V
OUT  
C2+  
V
V
V
V
OUT  
D1+  
GND  
N/C  
OUT  
D2+  
N/C  
OUT  
A1+  
GND  
GND  
OUT  
A2+  
V
CC  
OUT  
B1+  
GND  
GND  
N/C  
OUT  
B2+  
CC  
CC  
CC  
CC  
CC  
CC  
TDI  
TMS  
V
V
V
PAR  
CTL  
N/C  
GND BOE[7] BOE[5] BOE[3] BOE[1] GND  
GND BOE[6] BOE[4] BOE[2] BOE[0] GND  
TX  
MODE  
[0]  
GND  
GND  
TX  
RATE  
GND  
GND  
TDO  
N/C  
CC  
CC  
CC  
TCLK TRSTZ  
V
SPD  
SEL  
TX  
MODE  
[1]  
V
V
CC  
CC  
CC  
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
TXPER TXOP TXDC  
[0]  
N/C  
BISTLE  
GND  
GND  
N/C  
N/C  
OELE  
GND  
N/C  
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
N/C  
N/C  
C
C
TXDC TXCK TXDC TXDC  
[7]  
G
H
J
SEL  
[4]  
[1]  
GND  
GND  
GND  
GND  
TXCTC TXDC TXDC TXDC  
[1]  
[5]  
[2]  
[3]  
N/C  
N/C  
TXCTC  
[0]  
N/C  
N/C  
N/C  
K
L
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
GND  
N/C  
N/C  
TXCLK TXDC  
C
N/C  
N/C  
TXDB  
[6]  
[6]  
N/C  
N/C  
TXCTB TXCTB TXDB TXCLK  
[1]  
M
N
P
R
T
[0]  
[7]  
B
GND  
N/C  
GND  
N/C  
GND  
GND  
GND  
GND  
TXDB TXDB TXDB TXDB  
[5] [4] [3] [2]  
TXPER TXOP  
D
TXDB TXDB TXOP TXPER  
[1] [0]  
D
B
B
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
TXDD TXDD TXDD TXCTD  
V
V
V
V
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
GND  
N/C  
N/C  
N/C  
N/C  
REF  
TXDA  
[1]  
GND  
GND  
TXDA TXCTA  
[4] [0]  
V
V
V
V
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
U
V
W
[0]  
[1]  
[2]  
[1]  
CLK-  
TXDD TXDD TXCTD  
N/C  
REF  
CLK+  
N/C  
TXDA TXDA  
[3] [7]  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
[3]  
[4]  
[0]  
TXDD TXDD  
[5] [7]  
N/C  
N/C  
N/C  
GND TXCLK TXRST TXOPA SCSEL GND  
O-  
TXDA TXDA  
[2] [6]  
TXDD TXCLK  
N/C  
GND TXCLK  
O+  
N/C  
TXCLK TXPER GND  
A
TXDA TXDA  
[0] [5]  
TXCTA  
[1]  
Y
[6]  
D
A
Note:  
1. N/C = Do Not Connect  
Document #: 38-02112 Rev. **  
Page 4 of 30  
PRELIMINARY  
CYP15G0401TB  
[1]  
Pin Configuration (Bottom View)  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
OUT  
B2-  
N/C  
OUT  
B1-  
N/C  
V
V
V
V
OUT  
A2-  
N/C  
GND  
OUT  
A1-  
GND  
OUT  
D2-  
GND  
GND  
OUT  
D1-  
N/C  
V
OUT  
C2-  
N/C  
OUT  
C1-  
N/C  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
A
B
C
D
E
F
OUT  
B2+  
GND  
GND  
N/C  
OUT  
B1+  
V
OUT  
A2+  
GND  
GND  
OUT  
A1+  
N/C  
OUT  
D2+  
N/C  
GND  
GND  
GND  
OUT  
D1+  
V
V
V
V
OUT  
C2+  
V
V
V
V
OUT  
C1+  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
TDO  
N/C  
GND  
GND  
TX  
RATE  
GND  
GND  
TX  
MODE  
[0]  
GND BOE[1] BOE[3] BOE[5] BOE[7]  
GND BOE[0] BOE[2] BOE[4] BOE[6]  
N/C  
PAR  
CTL  
V
V
V
TMS  
TDI  
CC  
CC  
CC  
V
V
TX  
MODE  
[1]  
SPD  
SEL  
V
TRSTZ TCLK  
CC  
CC  
CC  
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
OELE  
GND  
N/C  
BISTLE  
GND  
GND  
N/C  
N/C  
TXDC TXOP TXPER  
[0]  
C
C
TXDC TXDC TXCK TXDC  
[1]  
G
H
J
[4]  
SEL  
[7]  
GND  
GND  
GND  
GND  
TXDC TXDC TXDC TXCTC  
[3]  
[2]  
[5]  
[1]  
N/C  
N/C  
N/C  
TXCTC  
[0]  
N/C  
N/C  
K
L
TXDB  
[6]  
N/C  
N/C  
TXDC TXCLK  
[6]  
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
GND  
N/C  
N/C  
C
TXCLK TXDB TXCTB TXCTB  
B
N/C  
N/C  
M
N
P
R
T
[7]  
[0]  
[1]  
GND  
GND  
GND  
GND  
GND  
N/C  
GND  
N/C  
TXDB TXDB TXDB TXDB  
[2] [3] [4] [5]  
TXPER TXOP TXDB TXDB  
[0] [1]  
TXOP TXPER  
D
B
B
D
V
V
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
V
V
V
V
TXCTA TXDA  
[0] [4]  
GND  
GND  
TXDA  
[1]  
REF  
N/C  
N/C  
N/C  
N/C  
GND  
GND  
GND  
GND  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
V
V
V
V
TXCTD TXDD TXDD TXDD  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
U
V
W
Y
CLK-  
[1]  
[2]  
[1]  
[0]  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
TXDA TXDA  
[7] [3]  
N/C  
REF  
CLK+  
N/C  
TXCTD TXDD TXDD  
[0]  
[4]  
[3]  
TXDA TXDA  
[6] [2]  
GND SCSEL TXOP TXRST TXCLK  
N/C  
N/C  
N/C  
TXDD TXDD  
[7] [5]  
A
O-  
TXCTA  
[1]  
TXDA TXDA  
[5] [0]  
GND TXPER TXCLK  
N/C  
TXCLK  
O+  
N/C  
TXCLK TXDD  
[6]  
A
A
D
Document #: 38-02112 Rev. **  
Page 5 of 30  
PRELIMINARY  
CYP15G0401TB  
Pin Descriptions  
CYP15G0401TB Quad HOTLink II Transmitter  
Pin Name  
I/O Characteristics  
Signal Description  
Transmit Path Data Signals  
TXPERA  
TXPERB  
TXPERC  
TXPERD  
LVTTL Output, changes Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is  
[2]  
relative to REFCLK  
↑
enabled and a parity error is detected at the Encoder. This output is HIGH for one  
transmit character clock period to indicate detection of a parity error in the character  
presented to the Encoder.  
If a parity error is detected, the character in error is replaced with a C0.7 character to  
force a corresponding bad-character detection at the remote end of the link. This  
replacement takes place regardless of the encoded/non-encoded state of the  
interface.  
When BIST is enabled for the specific transmit channel, BIST progress is presented  
on these outputs. Once every 511 character times, the associated TXPERx signal will  
pulse HIGH for one transmit-character clock period to indicate a complete pass  
through the BIST sequence. Therefore, in this case TXPERx signal will pulse HIGH  
for one transmit-character clock period.  
These outputs also provide indication of a transmit Phase-align Buffer underflow or  
overflow. When the transmit Phase-align Buffers are enabled (TXCKSEL  
≠ LOW, or  
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is  
detected, TXPERx for the channel in error is asserted and remains asserted until  
either an atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to  
re-center the transmit Phase-align Buffers.  
TXCTA[1:0]  
TXCTB[1:0] synchronous,  
TXCTC[1:0] sampled by the  
LVTTL Input,  
Transmit Control. These inputs are captured on the rising edge of the transmit  
interface clock as selected by TXCKSEL, and are passed to the Encoder or Transmit  
Shifter. They identify how the associated TXDx[7:0] characters are interpreted. When  
the Encoder is bypassed, these inputs are interpreted as data bits of 10-bit input  
character. When the Encoder is enabled, these inputs determine if the TXDx[7:0]  
character is encoded as Data, a Special Character code, a K28.5 fill character or a  
Word Sync Sequence. See Table 1 for details.  
TXCTD[1:0] selected TXCLKx  
↑
↑
or  
or  
[2]  
REFCLK  
↑
TXDA[7:0]  
TXDB[7:0]  
TXDC[7:0]  
TXDD[7:0]  
LVTTL Input,  
synchronous,  
sampled by the  
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit  
interface clock as selected by TXCKSEL and passed to the Encoder or Transmit  
Shifter.  
selected TXCLKx  
When the Encoder is enabled (TXMODE[1:0]  
data or command character to be sent. When the Encoder is bypassed, these inputs  
≠ LOW), TXDx[7:0] specify the specific  
[2]  
REFCLK  
↑
are interpreted as data bits of the 10-bit input character. See Table 1 for details.  
TXOPA  
TXOPB  
TXOPC  
TXOPD  
LVTTL Input,  
Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the  
synchronous,  
internal pull-up,  
sampled by the  
parity captured at these inputs is XORed with the data on the associated TXDx bus  
(and sometimes TXCT[1:0]) to verify the integrity of the captured character. See  
Table 2 for details.  
respective TXCLKx↑ or  
[2]  
REFCLK  
↑
SCSEL  
LVTTL Input,  
synchronous,  
internal pull-down,  
sampled by  
Special Character Select. Used in some transmit modes along with TXCTx[1:0] to  
encode special characters or to initiate a Word Sync Sequence. When the transmit  
paths are configured for independent input clocks (TXCKSEL = MID), SCSEL is  
captured relative to TXCLKA↑.  
TXCLKA  
↑
[2]  
or REFCLK  
↑
Note:  
2. When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling  
edges of REFCLK.  
Document #: 38-02112 Rev. **  
Page 6 of 30  
PRELIMINARY  
CYP15G0401TB  
Pin Descriptions (continued)  
CYP15G0401TB Quad HOTLink II Transmitter  
Pin Name  
TXRST  
I/O Characteristics  
Signal Description  
LVTTL Input,  
asynchronous,  
internal pull-up,  
Transmit Clock Phase Reset. Active LOW. When sampled LOW, the transmit  
Phase-align Buffers are allowed to adjust their data-transfer timing (relative to the  
selected input clock) to allow clean transfer of data from the Input Register to the  
Encoder or Transmit Shifter. When TXRST is sampled HIGH, the internal phase  
relationship between the associated TXCLKx and the internal character-rate clock is  
fixed and the device operates normally.  
sampled by  
[2]  
REFCLK  
↑
When configured for half-rate REFCLK sampling of the transmit character stream  
(TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear  
Phase-align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs  
with excessive cycle-to-cycle jitter. During this alignment period, one or more  
characters may be added to or lost from all the associated transmit paths as the  
transmit Phase-align Buffers are adjusted. TXRST must be sampled LOW by a  
minimum of two consecutive rising edges REFCLK to ensure the reset operation is  
initiated correctly on all channels. This input is ignored when both TXCKSEL and  
TXRATE are LOW, since the phase align buffer is bypassed. In all other configura-  
tions, TXRST should be asserted during device initialization to ensure proper  
operation of the Phase-align buffer. TXRST should be asserted after the presence of  
a valid TXCLKx and after allowing enough time for the TXPLL to lock to the reference  
clock (as specified by parameter t  
).  
TXLOCK  
Transmit Path Clock and Clock Control  
[3]  
TXCKSEL  
Three-level Select  
static control input  
,
Transmit Clock Select. Selects the clock source, used to write data into the transmit  
[2]  
Input Register of the transmit channel(s). When LOW, REFCLK  
Input Register clock for TXDx[7:0] and TXCTx[1:0] of all channels. When MID,  
TXCLKx is used as the Input Register clock for TXDx[7:0] and TXCTx[1:0]. When  
↑
is used as the  
↑
HIGH, TXCLKA  
↑ is used as the Input Register clock for TXDx[7:0] and TXCTx[1:0] of  
all channels.  
TXCLKO  
TXRATE  
±
LVTTL Output  
Transmit Clock Output. This true and complement output clock is synthesized by  
the transmit PLL and is synchronous to the internal transmit character clock. It has  
the same frequency as REFCLK (when TXRATE = LOW), or twice the frequency of  
REFCLK (when TXRATE = HIGH). This output clock has no direct phase relationship  
to REFCLK.  
LVTTL Input,  
static control input,  
internal pull-down  
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multi-  
plies REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the  
transmit PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See Table 9  
for a list of operating serial rates.  
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input  
register), configuring TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of  
operation.  
TXCLKA  
TXCLKB  
TXCLKC  
TXCLKD  
LVTTL Clock Input,  
internal  
pull-down  
Transmit Path Input Clocks. These clocks must be frequency-coherent to  
TXCLKO±, but may be offset in phase. The internal operating phase of each input  
clock (relative to REFLCK or TXCLKO  
when TXRST = HIGH.  
±) is adjusted when TXRST = LOW and locked  
Transmit Path Mode Control  
[3]  
TXMODE[1:0] Three-level Select  
Transmit Operating Mode. These inputs are interpreted to select one of nine  
operating modes of the transmit path. See Table 3 for a list of operating modes.  
static control inputs  
Note:  
3. Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and  
HIGH. The LOW level is usually implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V . When  
SS  
CC  
not connected or allowed to float, a Three-level select input will self-bias to the MID level.  
Document #: 38-02112 Rev. **  
Page 7 of 30  
PRELIMINARY  
CYP15G0401TB  
Pin Descriptions (continued)  
CYP15G0401TB Quad HOTLink II Transmitter  
Pin Name  
I/O Characteristics  
Signal Description  
Device Control Signals  
[3]  
PARCTL  
Three-level Select  
,
Parity Check Control. Used to control the different parity check functions. When  
static control input  
LOW, parity check is disabled. When MID, and the 8B/10B Encoder is enabled  
(TXMODE[1]  
≠
LOW), TXDx[7:0] inputs are checked (along with TXOPx) for valid  
ODD parity. When the Encoder is disabled (TXMODE[1]  
=
LOW), theTXDx[7:0] and  
TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity. When HIGH,  
parity check is enabled. The TXDx[7:0] and TXCTx[1:0] inputs are checked (along  
with TXOPx) for valid ODD parity. See Table 2 for details.  
[3]  
SPDSEL  
TRSTZ  
Three-level Select  
static control input  
Serial Rate Select. This input specifies the operating bit-rate range of the transmit  
PLLs. LOW = 195–400 MBd, MID = 400–800 MBd, HIGH = 800–1500 MBd. When  
SPDSEL is LOW, setting TXRATE = HIGH (Half-rate Reference Clock) is invalid.  
LVTTL Input,  
Device Reset. Active LOW. Initializes all state machines and counters in the device.  
internal pull-up  
When sampled LOW by the rising edge of REFCLK  
state machines. When the reset is removed (TRSTZ sampled HIGH by REFCLK  
↑
, this input resets the internal  
↑
),  
the status and data outputs will become deterministic in less than 16 REFCLK cycles.  
The BISTLE and OELE latches are reset by TRSTZ. If the Phase-align Buffer is used,  
TRSTZ should be applied after power up to initialize the internal pointers into these  
memory arrays.  
REFCLK  
±
Differential LVPECL or  
single-ended  
LVTTL Input Clock  
Reference Clock. This clock input is used as the timing reference for the transmit  
PLL. This input clock may also be selected to clock the transmit parallel interfaces.  
When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock  
source to either the true or complement REFCLK input, and leave the alternate  
REFCLK input open (floating). When driven by an LVPECL clock source, the clock  
must be a differential clock, using both inputs. When TXCKSEL = LOW, REFCLK is  
also used as the clock for the parallel transmit data (input) interface.  
Analog I/O and Control  
OUTA1  
OUTB1  
OUTC1  
OUTD1  
±
CML Differential  
Output  
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs  
(+3.3V referenced) are capable of driving terminated transmission lines or standard  
fiber-optic transmitter modules.  
±
±
±
OUTA2  
OUTB2  
OUTC2  
OUTD2  
±
CML Differential  
Output  
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs  
(+3.3V referenced) are capable of driving terminated transmission lines or standard  
fiber-optic transmitter modules.  
±
±
±
OELE  
LVTTL Input,  
asynchronous,  
internal pull-up  
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the  
signals on the BOE[7:0] inputs directly control the OUTxy± differential drivers. When  
the BOE[x] input is HIGH, the associated OUTxy  
the BOE[x] input is LOW, the associated OUTxy  
±
±
differential driver is enabled. When  
differential driver is powered down.  
The specific mapping of BOE[7:0] signals to transmit output enables is listed in  
Table 8. When OELE returns LOW, the last values present on BOE[7:0] are captured  
in the internal Output Enable Latch. If the device is reset (TRSTZ is sampled LOW),  
the latch is reset to disable all outputs.  
BISTLE  
LVTTL Input,  
asynchronous,  
internal pull-up  
Transmit BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the signals on  
the BOE[7:0] inputs directly control the transmit BIST enables. When the BOE[x] input  
is LOW, the associated transmit channel is configured to generate the BIST sequence.  
When the BOE[x] input is HIGH, the associated transmit channel is configured for  
normal data transmission. The specific mapping of BOE[7:0] signals to transmit BIST  
enables is listed in Table 8. When BISTLE returns LOW, the last values present on  
BOE[7:0] are captured in the internal BIST Enable Latch. When the latch is closed, if  
the device is reset (TRSTZ is sampled LOW), the latch is reset to disable BIST on all  
transmit channels.  
Document #: 38-02112 Rev. **  
Page 8 of 30  
PRELIMINARY  
CYP15G0401TB  
Pin Descriptions (continued)  
CYP15G0401TB Quad HOTLink II Transmitter  
Pin Name  
I/O Characteristics  
Signal Description  
BOE[7:0]  
LVTTL Input,  
asynchronous,  
internal pull-up  
BIST and Serial Output, and Enables. These inputs are passed to and through the  
Output Enable Latch when OELE is HIGH, and captured in this latch when OELE  
returns LOW. These inputs are passed to and through the BIST Enable Latch when  
BISTLE is HIGH, and captured in this latch when BISTLE returns LOW.  
JTAG Interface  
TMS  
LVTTL Input,  
internal pull-up  
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high  
for ≥5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset  
automatically upon application of power to the device.  
TCLK  
TDO  
LVTTL Input,  
internal pull-down  
JTAG Test Clock  
Three-state  
LVTTL Output  
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not  
selected.  
TDI  
LVTTL Input, internal pull-up Test Data In. JTAG data input port.  
Power  
V
+3.3V Power  
CC  
GND  
Signal and power ground for all internal circuits.  
TXCLKA↑. While the value on SCSEL still affects all channels,  
CYP15G0401TB HOTLink II Operation  
it is interpreted when the character containing it is read from  
the transmit Phase-align Buffer (where all four paths are inter-  
nally clocked synchronously).  
The CYP15G0401TB is a highly configurable device designed  
to support reliable transfer of large quantities of data, using  
high-speed serial links, from one source to one or multiple  
destinations. This device supports four single-byte or  
single-character channels.  
Table 1. Input Register Bit Assignments [4]  
Encoded  
2-bit  
3-bit  
CYP15G0401TB Transmit Data Path  
Signal Name  
TXDx[0] (LSB)  
TXDx[1]  
Unencoded  
DINx[0]  
DINx[1]  
DINx[2]  
DINx[3]  
DINx[4]  
DINx[5]  
DINx[6]  
DINx[7]  
DINx[8]  
DINx[9]  
N/A  
Control  
Control  
Operating Modes  
TXDx[0]  
TXDx[1]  
TXDx[2]  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1]  
N/A  
TXDx[0]  
TXDx[1]  
TXDx[2]  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1]  
SCSEL  
The transmit path of the CYP15G0401TB supports four  
character-wide data paths. These data paths are used in  
multiple operating modes as controlled by the TXMODE[1:0]  
inputs.  
TXDx[2]  
TXDx[3]  
TXDx[4]  
Input Register  
TXDx[5]  
The bits in the Input Register for each channel support  
different assignments, based on if the character is unencoded,  
encoded with two control bits, or encoded with three control  
bits. These assignments are shown in Table 1. Each Input  
Register captures a minimum of eight data bits and two control  
bits on each input clock cycle. When the Encoder is bypassed,  
the TXCTx[1:0] control bits, are part of the preencoded 10-bit  
character.  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1] (MSB)  
SCSEL  
When the Encoder is enabled (TXMODE[1]  
TXCTx[1:0] bits are interpreted along with the associated  
TXDx[7:0] character to generate the specific 10-bit trans-  
≠ LOW), the  
Phase-align Buffer  
Data from the Input Registers are passed either to the Encoder  
or to the associated Phase-align Buffer. When the transmit  
paths are operated synchronous to REFCLK  
= LOW and TXRATE = LOW), the Phase-align Buffers are  
bypassed and data is passed directly to the Parity Check and  
Encoder blocks to reduce latency.  
mission character. When TXMODE[0]  
≠ HIGH, an additional  
↑ (TXCKSEL  
special character select (SCSEL) input is also captured and  
interpreted. This SCSEL input is used to modify the encoding  
of the associated characters. When the transmit Input  
Registers are clocked by a common clock (TXCLKA  
REFCLK ), this SCSEL input can be changed on a  
clock-by-clock basis and affects all four channels.  
↑ or  
↑
When an Input-Register clock with an uncontrolled phase  
relationship to REFCLK is selected (TXCKSEL  
data is captured on both edges of REFCLK (TXRATE = HIGH),  
the Phase-align Buffers are enabled. These buffers are used  
≠ LOW) or if  
When operated with a separate input clock on each transmit  
channel, this SCSEL input is sampled synchronous to  
Document #: 38-02112 Rev. **  
Page 9 of 30  
PRELIMINARY  
CYP15G0401TB  
to absorb clock phase differences between the presently  
Table 2. Input Register Bits Checked for Parity [6]  
selected input clock and the internal character clock.  
Transmit Parity Check Mode (PARCTL)  
MID  
Initialization of the Phase-align Buffers takes place when the  
TXRST input is sampled LOW by two consecutive rising edges  
of REFCLK. When TXRST is returned HIGH, the present input  
clock phase relative to REFCLK is set. TXRST is an  
asynchronous input, but is sampled internally to synchronize  
it to the internal transmit path state machines.  
Signal  
Name  
TXMODE[1] TXMODE[1]  
LOW  
= LOW  
≠ LOW  
HIGH  
X
[7]  
TXDx[0]  
TXDx[1]  
TXDx[2]  
TXDx[3]  
TXDx[4]  
TXDx[5]  
TXDx[6]  
TXDx[7]  
TXCTx[0]  
TXCTx[1]  
TXOPx  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Once set, the input clocks are allowed to skew in time up to  
half a character period in either direction relative to REFCLK;  
X
i.e.,  
±180°. This time shift allows the delay paths of the  
X
character clocks (relative to REFCLK) to change due to  
operating voltage and temperature, while not affecting the  
design operation.  
X
X
X
If the phase offset, between the initialized location of the input  
clock and REFCLK↑, exceeds the skew handling capabilities  
X
of the Phase-align Buffer, an error is reported on the  
associated TXPERx output. This output indicates a continuous  
error until the Phase-align Buffer is reset. While the error  
remains active, the transmitter for the associated channel will  
output a continuous C0.7 character to indicate to the remote  
receiver that an error condition is present in the link.  
X
X
X
X
logic. This block interprets each character and any associated  
control bits, and outputs a 10-bit transmission character.  
In specific transmit modes, it is also possible to reset the  
Phase-align Buffers individually and with minimal disruption of  
the serial data stream. When the transmit interface is  
configured for generation of atomic Word Sync Sequences  
(TXMODE[1] = MID) and a Phase-align Buffer error is present,  
the transmission of a Word Sync Sequence will re-center the  
Depending on the configured operating mode, the generated  
transmission character may be  
• the 10-bit pre-encoded character accepted in the Input  
Register  
[5]  
Phase-align Buffer and clear the error condition.  
• the 10-bit equivalent of the eight-bit Data character  
accepted in the Input Register  
Parity Support  
• the 10-bit equivalent of the eight-bit Special Character code  
accepted in the Input Register  
In addition to the ten data and control bits that are captured at  
each transmit Input Register, a TXOPx input is also available  
on each channel. This allows the CYP15G0401TB to support  
ODD parity checking for each channel. Parity checking is  
available for all operating modes (including Encoder Bypass).  
The specific mode of parity checking is controlled by the  
• the 10-bit equivalent of the C0.7 SVS character if parity  
checking was enabled and a parity error was detected  
• the 10-bit equivalent of the C0.7 SVS character if a  
Phase-align Buffer overflow or underflow error is present  
PARCTL input, and operates per Table 2  
When PARCTL is MID (open) and the Encoders are enabled  
(TXMODE[1] LOW), only the TXDx[7:0] data bits are  
.
• a character that is part of the 511-character BIST sequence  
• a K28.5 character generated as an individual character or  
as part of the 16-character Word Sync Sequence.  
≠
checked for ODD parity along with the associated TXOPx bit.  
When PARCTL = HIGH with the Encoder enabled (or MID with  
the Encoder bypassed), the TXDx[7:0] and TXCTx[1:0] inputs  
are checked for ODD parity along with the associated TXOPx  
bit. When PARCTL = LOW, parity checking is disabled.  
The selection of the specific characters generated are  
controlled by the TXMODE[1:0], SCSEL, TXCTx[1:0], and  
TXDx[7:0] inputs for each character.  
Data Encoding  
When parity checking and the Encoder are both enabled  
Raw data, as received directly from the Transmit Input  
Register, is seldom in a form suitable for transmission across  
a serial link. The characters must usually be processed or  
transformed to guarantee  
(TXMODE[1]  
≠ LOW), the detection of a parity error causes a  
C0.7 character of proper disparity to be passed to the Transmit  
Shifter. When the Encoder is bypassed (TXMODE[1] = LOW,  
LOW), detection of a parity error causes a positive disparity  
version of a C0.7 transmission character to be passed to the  
Transmit Shifter.  
• a minimum transition density (to allow the remote serial  
receive PLL to extract a clock from the data stream).  
• a DC-balance in the signaling (to prevent baseline wander).  
Encoder  
• run-length limits in the serial data (to limit the bandwidth  
requirements of the serial link).  
The character, received from the Input Register or Phase-align  
Buffer and Parity Check Logic, is then passed to the Encoder  
Notes:  
4. The TXOPx inputs are also captured in the associated Input Register, but their interpretation is under the separate control of PARCTL.  
5. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a complete  
16-character Word Sync Sequence for proper Receive Elasticity Buffer alignment, it is recommend that the sequence be followed by a second Word Sync Sequence  
to ensure proper operation.  
6. Transmit path parity errors are reported on the associated TXPERx output.  
7. Bits marked as X are XORed together. Result must be a logic-1 for parity to be valid.  
Document #: 38-02112 Rev. **  
Page 10 of 30  
PRELIMINARY  
CYP15G0401TB  
• the remote receiver a way of determining the correct  
character boundaries (framing).  
The encoded modes (TX Modes 3 through 8) support multiple  
encoding tables. These encoding tables vary by the specific  
combinations of SCSEL, TXCTx[1], and TXCTx[0] that are  
used to control the generation of data and control characters.  
These multiple encoding forms allow maximum flexibility in  
interfacing to legacy applications, while also supporting  
numerous extensions in capabilities.  
When the Encoder is enabled (TXMODE[1]  
≠ LOW), the  
characters to be transmitted are converted from Data or  
Special Character codes to 10-bit transmission characters (as  
selected by their respective TXCTx[1:0] and SCSEL inputs),  
using an integrated 8B/10B Encoder. When directed to encode  
the character as a Special Character code, it is encoded using  
the Special Character encoding rules listed in Table 14. When  
directed to encode the character as a Data character, it is  
TX Mode 0—Encoder Bypass  
When the Encoder is bypassed, the character captured from  
the TXDx[7:0] and TXCTx[1:0] inputs is passed directly to the  
Transmit Shifter without modification. If parity checking is  
encoded using the Data Character encoding rules in Table 13  
.
The 8B/10B Encoder is standards compliant with ANSI/NCITS  
ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit  
enabled (PARCTL  
10-bit character is replaced with the 1001111000 pattern  
(+C0.7 character).  
≠ LOW) and a parity error is detected, the  
®
®
Ethernet), the IBM ESCON and FICON™ channels, Digital  
Video Broadcast (DVB-ASI), and ATM Forum standards for  
data transport.  
With the Encoder bypassed, the TXCTx[1:0] inputs are  
considered part of the data character and do not perform a  
control function that would otherwise modify the interpretation  
of the TXDx[7:0] bits. The bit usage and mapping of these  
Many of the Special Character codes listed in Table 14 may be  
generated by more than one input character. The  
CYP15G0401TB is designed to support two independent (but  
non-overlapping) Special Character code tables. This allows  
the CYP15G0401TB to operate in mixed environments with  
other Cypress HOTLink devices using the enhanced Cypress  
command code set, and the reduced command sets of other  
non-Cypress devices. Even when used in an environment that  
normally uses non-Cypress Special Character codes, the  
selective use of Cypress command codes can permit  
operation where running disparity and error handling must be  
managed.  
control bits when the Encoder is bypassed is shown in Table 4  
.
In Encoder Bypass mode, the SCSEL input is ignored. All  
clocking modes interpret the data the same, with no internal  
linking between channels.  
Table 4. Encoder Bypass Mode (TXMODE[1:0] = LL)  
Signal Name  
Bus Weight  
10Bit Name  
[8]  
0
TXDx[0] (LSB)  
TXDx[1]  
2
a
b
c
d
e
i
1
2
Following conversion of each input character from eight bits to  
a 10-bit transmission character, it is passed to the Transmit  
Shifter and is shifted out LSB first, as required by ANSI and  
IEEE standards for 8B/10B coded serial data streams.  
2
TXDx[2]  
2
3
TXDx[3]  
2
4
TXDx[4]  
2
Transmit Modes  
5
TXDx[5]  
2
The operating mode of the transmit path is set through the  
TXMODE[1:0] inputs. These static three-level select inputs  
allow one of nine transmit modes to be selected. The transmit  
modes are listed in Table 3  
6
TXDx[6]  
2
f
7
TXDx[7]  
2
g
h
j
8
TXCTx[0]  
TXCTx[1] (MSB)  
2
9
Table 3. Transmit Operating Modes  
2
TX Mode  
Operating Mode  
TX Modes 1 and 2—Factory Test Modes  
These modes enable specific factory test configurations. They  
are not considered normal operating modes of the device.  
Entry or configuration of the device into these modes will not  
damage the device.  
Word Sync  
Sequence  
Support  
SCSEL  
Control  
None  
TXCTx Function  
0
1
2
3
LL None  
LM None  
Encoder Bypass  
Reserved for test  
Reserved for test  
Encoder Control  
TX Mode 3— Word Sync and SCSEL Control of Special Codes  
None  
None  
When configured in TX Mode 3, the SCSEL input is captured  
along with the associated TXCTx[1:0] data control inputs.  
These bits combine to control the interpretation of the  
TXDx[7:0] bits and the characters generated by them. These  
LH None  
ML Atomic  
Special  
Character  
bits are interpreted as listed in Table 5  
.
4
5
6
MM Atomic  
MH Atomic  
Word Sync Encoder Control  
When TXCKSEL = MID, all transmit channels capture data into  
their Input Registers using independent TXCLKx clocks. In this  
mode, the SCSEL input is sampled only by TXCLKA↑. When  
the character (accepted in the Channel-A Input Register) has  
passed through the Phase-align Buffer and any selected parity  
validation, the level captured on SCSEL is passed to the  
Encoder of the remaining channels during this same cycle.  
None  
Encoder Control  
Encoder Control  
HL Interruptible Special  
Character  
7
8
HM Interruptible Word Sync Encoder Control  
HH Interruptible None Encoder Control  
Note:  
8. LSB is shifted out first.  
Document #: 38-02112 Rev. **  
Page 11 of 30  
PRELIMINARY  
CYP15G0401TB  
SVS character. Any interruption of the Word Sync Sequence  
causes the sequence to terminate.  
Table 5. TX Modes 3 and 6 Encoding  
When TXCKSEL = LOW, the Input Registers for all four  
[2]  
transmit channels are clocked by REFCLK. When  
TXCKSEL = HIGH, the Input Registers for all four transmit  
Characters Generated  
Encoded data character  
channels are clocked with TXCLKA↑. In these clock modes all  
four sets of TXCTx[1:0] inputs operate synchronous to the  
SCSEL input.  
X
0
1
X
X
0
0
1
0
1
1
1
K28.5 fill character  
TX Mode 4—Atomic Word Sync and SCSEL Control of Word  
Sync Sequence Generation  
Special character code  
16-character Word Sync Sequence  
When configured in TX Mode 4, the SCSEL input is captured  
along with the associated TXCTx[1:0] data control inputs.  
These bits combine to control the interpretation of the  
TXDx[7:0] bits and the characters generated by them. These  
To avoid the possible ambiguities that may arise due to the  
uncontrolled arrival of SCSEL relative to the characters in the  
alternate channels, SCSEL is often used as static control  
input.  
bits are interpreted as listed in Table 6  
.
When TXCKSEL = MID, all transmit channels operate  
independently. In this mode, the SCSEL input is sampled only  
by TXCLKA↑. When the character accepted in the Channel-A  
Input Register has passed any selected validation and is ready  
to be passed to the Encoder, the level captured on SCSEL is  
passed to the Encoders of the remaining channels during this  
same cycle.  
Word Sync Sequence  
When TXCTx[1:0] = 11, a 16-character sequence of K28.5  
characters, known as a Word Sync Sequence, is generated on  
the associated channel. This sequence of K28.5 characters  
may start with either a positive or negative disparity K28.5 (as  
determined by the current running disparity and the 8B/10B  
coding rules). The disparity of the second and third K28.5  
characters in this sequence are reversed from what normal  
8B/10B coding rules would generate. The remaining K28.5  
characters in the sequence follow all 8B/10B coding rules. The  
disparity of the generated K28.5 characters in this sequence  
Table 6. TX Modes 4 and 7 Encoding  
follow  
a
pattern of either ++––+–+–+–+–+–+– or  
––++–+–+–+–+–+–+.  
Characters Generated  
When TXMODE[1] = MID (open, TX modes 3, 4, and 5), the  
generation of this character sequence is an atomic (non-inter-  
ruptible) operation. Once it has been successfully started, it  
cannot be stopped until all sixteen characters have been  
generated. The content of the associated Input Registers is  
ignored for the duration of this 16-character sequence. At the  
end of this sequence, if the TXCTx[1:0] = 11 condition is  
sampled again, the sequence restarts and remains uninter-  
ruptible for the following fifteen character clocks.  
X
0
0
1
X
0
1
X
0
1
1
1
Encoded data character  
K28.5 fill character  
Special character code  
16-character Word Sync Sequence  
Changing the state of SCSEL will change the relationship of  
the characters to other channels. SCSEL should either be  
used as a static configuration input, or changed only when the  
state of TXCTx[1:0] on the alternate channels are such that  
SCSEL is ignored during the change.  
If parity checking is enabled, the character used to start the  
Word Sync Sequence must also have correct ODD parity.  
Once the sequence is started, parity is not checked on the  
following fifteen characters in the Word Sync Sequence.  
TX Mode 4 also supports an Word Sync Sequence. Unlike TX  
Mode 3, this sequence starts when SCSEL and TXCTx[0] are  
both high. With the exception of the combination of control bits  
used to initiate the sequence, the generation and operation of  
this Word Sync Sequence is the same as for TX Mode 3.  
When TXMODE[1] = HIGH (TX modes 6, 7, and 8), the gener-  
ation of the Word Sync Sequence becomes an interruptible  
operation. In TX Mode 6, this sequence is started as soon as  
the TXCTx[1:0] = 11 condition is detected on a channel. In  
order for the sequence to continue on that channel, the  
TXCTx[1:0] inputs must be sampled as 00 for the remaining  
fifteen characters of the sequence.  
TX Mode 5—Atomic Word Sync generation without SCSEL.  
When configured in TX Mode 5, the SCSEL signal is not used.  
The TXCTx[1:0] inputs for each channel control the characters  
generated by that channel. The specific characters generated  
If at any time a sample period exists where TXCTx[1:0]  
≠ 00,  
the Word Sync Sequence is terminated, and a character repre-  
senting the associated data and control bits is generated by  
the Encoder. This resets the Word Sync Sequence state  
machine such that it will start at the beginning of the sequence  
at the next occurrence of TXCTx[1:0] = 11.  
by these bits are listed in Table 7  
.
TX Mode 5 also has the capability of generating an atomic  
Word Sync Sequence. For the sequence to be started, the  
TXCTx[1:0] inputs must both be sampled HIGH. The gener-  
ation and operation of this Word Sync Sequence is the same  
as TX Mode 3.  
When parity checking is enabled and TXMODE[1] = HIGH, all  
characters (including those in the middle of a Word Sync  
Sequence) must have correct parity. The detection of a  
character with incorrect parity during a Word Sync Sequence  
will interrupt that sequence and force generation of a C0.7  
Transmit BIST  
Each transmit channel contains an internal pattern generator  
that can be used to validate both device and link operation.  
Document #: 38-02112 Rev. **  
Page 12 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 7. TX Modes 5 and 8 Encoding  
present on the BOE[7:0] inputs are latched in the Output  
Enable Latch, and remain there until OELE returns HIGH to  
enable the latch. A device reset (TRSTZ sampled LOW) clears  
this latch and disables all Serial Drivers.  
Table 8. Output Enable and BIST Enable Signal Map  
BIST  
Characters Generated  
Encoded data character  
X
X
X
X
0
0
1
1
0
1
0
1
Output  
Controlled  
(OELE)  
Channel  
Enable  
BOE  
Input  
K28.5 fill character  
(BISTLE)  
Special character code  
BOE[7]  
BOE[6]  
BOE[5]  
BOE[4]  
BOE[3]  
BOE[2]  
BOE[1]  
BOE[0]  
OUTD2  
OUTD1  
OUTC2  
OUTC1  
±
±
±
±
Transmit D  
X
16-character Word Sync Sequence  
Transmit C  
These generators are enabled by the associated BOE[x]  
signals listed in Table 8 (when the BISTLE latch enable input  
is HIGH). When enabled, a register in the associated transmit  
channel becomes a signature pattern generator by logically  
converting to a Linear Feedback Shift Register (LFSR). This  
LFSR generates a 511-character sequence that includes all  
Data and Special Character codes, including the explicit  
X
OUTB2  
±
±
Transmit B  
OUTB1  
X
Transmit A  
X
OUTA2  
OUTA1  
±
±
violation symbols. This provides  
a
predictable yet  
pseudo-random sequence that can be matched to identical  
LFSR in the attached remote Receiver(s), the  
CYP15G0401RB for example. To enable BIST for serial link  
testing, ensure that the remote HOTLink receivers are using  
the recovered clock from the associated receive CDR PLL to  
clock the receive parallel interface (for example RXCKSEL =  
MID for the CYP15G0401RB device).  
NOTE: When all transmit channels are disabled (i.e., both  
outputs disabled in all channels) and a channel is re-en-  
abled, the data on the Serial Drivers may not meet all timing  
specifications for up to 200  
µs.  
Transmit PLL Clock Multiplier  
The Transmit PLL Clock Multiplier accepts a character-rate or  
half-character-rate external clock at the REFCLK input, and  
multiples that clock by 10 or 20 (as selected by TXRATE) to  
generate a bit-rate clock for use by the Transmit Shifter. It also  
provides a character-rate clock used by the transmit paths.  
When the BISTLE signal is HIGH, any BOE[x] input that is  
LOW enables the BIST generator in the associated transmit  
channel. When BISTLE returns LOW, the values of all BOE[x]  
signals are captured in the BIST Enable Latch. These values  
remain in the BIST Enable Latch until BISTLE is returned  
HIGH to open the latch. A device reset (TRSTZ sampled  
LOW), presets the BIST Enable Latch to disable BIST on all  
channels.  
This clock multiplier PLL can accept a REFCLK input between  
20 MHz and 150 MHz, however, this clock range is limited by  
the operating mode of the CYP15G0401TB clock multiplier  
(controlled by TXRATE) and by the level on the SPDSEL input.  
All data and data-control information present at the associated  
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is  
active on that channel.  
When TXRATE = HIGH (Half-rate REFCLK), TXCKSEL =  
HIGH or MID (TXCLKx or TXCLKA selected to clock input  
register) is an invalid mode of operation.  
[3]  
SPDSEL is a static three-level select  
(ternary) input that  
Serial Output Drivers  
selects one of three operating ranges for the serial data  
outputs and inputs. The operating serial signaling-rate and  
The serial interface Output Drivers use high-performance  
differential CML (Current Mode Logic) to provide  
source-matched drivers for the transmission lines. These  
Serial Drivers accept data from the Transmit Shifters. These  
outputs have signal swings equivalent to that of standard  
PECL drivers, and are capable of driving AC-coupled optical  
modules or transmission lines. To achieve OBSAI RP3  
compliancy, the serial output drivers must be AC-coupled to  
the transmission medium.  
allowable range of REFCLK frequencies are listed in Table 9  
.
Table 9. Operating Speed Settings  
REFCLK  
Frequency  
(MHz)  
Signaling  
Rate (MBaud)  
SPDSEL  
TXRATE  
LOW  
1
0
1
0
1
0
reserved  
19.5–40  
20–40  
195–400  
Each Serial Driver can be enabled or disabled separately  
through the BOE[7:0] inputs, as controlled by the OELE  
latch-enable signal. When OELE is HIGH, the signals present  
on the BOE[7:0] inputs are passed through the Serial Output  
Enable Latch to control the Serial Driver. The BOE[7:0] input  
MID (Open)  
HIGH  
400–800  
40–80  
40–75  
800–1500  
80–150  
associated with a specific OUTxy± driver is listed in Table 8.  
When OELE is HIGH and BOE[x] is HIGH, the associated  
Serial Driver is enabled. When OELE is HIGH and BOE[x] is  
LOW, the associated Serial Driver is disabled and internally  
powered down. If both Serial Drivers for a channel are in this  
disabled state, the associated internal logic for that channel is  
also powered down. When OELE returns LOW, the values  
The REFCLK± input is a differential input with each input inter-  
nally biased to 1.4V. If the REFCLK+ input is connected to a  
TTL, LVTTL, or LVCMOS clock source, REFCLK– can be left  
floating and the input signal is recognized when it passes  
through the internally biased reference point.  
Document #: 38-02112 Rev. **  
Page 13 of 30  
PRELIMINARY  
CYP15G0401TB  
When both the REFCLK+ and REFCLK– inputs are  
Device Reset State  
connected, the clock source must be a differential clock. This  
can be either a differential LVPECL clock that is DC- or  
AC-coupled, or a differential LVTTL or LVCMOS clock.  
When the CYP15G0401TB is reset by assertion of TRSTZ, the  
Transmit Enable Latches are cleared, and the BIST Enable  
Latch is preset. In this state, all transmit channels are disabled,  
and BIST is disabled on all channels.  
By connecting the REFCLK– input to an external voltage  
source or resistive voltage divider, it is possible to adjust the  
reference point of the REFCLK+ input for alternate logic levels.  
When doing so, it is necessary to ensure that the input differ-  
ential crossing point remains within the parametric range  
supported by the input.  
Following a device reset, it is necessary to enable the transmit  
channels used for normal operation. This can be done by  
sequencing the appropriate values on the BOE[7:0] inputs  
while the OELE signal is raised and lowered. For systems that  
do not require dynamic control of power, or want the device to  
power up in a fixed configuration, it is also possible to strap the  
OELE control signal HIGH to permanently enable its  
associated latches. Connection of the associated BOE[7:0]  
signals to a stable HIGH will then enable the respective  
transmit channels as soon as the TRSTZ signal is deasserted.  
Power Control  
The CYP15G0401TB supports user control of the powered up  
or down state of each transmit channel. The transmit channels  
are controlled by the OELE signal and the values present on  
the BOE[7:0] bus. Powering down unused channels will save  
power and reduce system heat generation. Controlling system  
power dissipation will improve the system performance.  
JTAG Support  
The CYP15G0401TB contains a JTAG port to allow system  
level diagnosis of device interconnect. Of the available JTAG  
modes, only boundary scan is supported. This capability is  
present only on the LVTTL inputs, LVTTL outputs and the  
Transmit Channels  
When OELE is HIGH, the signals on the BOE[7:0] inputs  
directly control the power enables for the Serial Drivers. When  
a BOE[x] input is HIGH, the associated Serial Driver is  
enabled. When a BOE[x] input is LOW, the associated Serial  
Driver is disabled and powered down. If both Serial Drivers of  
a channel are disabled, the internal logic for that transmit  
channel is powered down. When OELE returns LOW, the  
values present on the BOE[7:0] inputs are latched in the  
Output Enable Latch.  
REFCLK  
± clock input. The high-speed serial inputs and  
outputs are not part of the JTAG test chain.  
JTAG ID  
The JTAG device ID for the CYP15G0401TB is ‘1C800069’x.  
Three-level Select Inputs  
Each Three-level select input reports as two bits in the scan  
register. These bits report the LOW, MID, and HIGH state of  
the associated input as 00, 10, and 11, respectively.  
Document #: 38-02112 Rev. **  
Page 14 of 30  
PRELIMINARY  
CYP15G0401TB  
Static Discharge Voltage..........................................> 2000 V  
(per MIL-STD-883, Method 3015)  
Maximum Ratings  
(Above which the useful life may be impaired. User guidelines  
only, not tested.)  
Latch-up Current.....................................................> 200 mA  
Power-up Requirements  
Storage Temperature ..................................–65°C to +150°C  
Ambient Temperature with Power Applied....–55°C to +125°C  
Supply Voltage to Ground Potential............... –0.5V to +3.8V  
DC Voltage Applied to LVTTL Outputs  
The CYP15G0401TB requires one power-supply. The Voltage  
on any input or I/O pin cannot exceed the power pin during  
power-up  
Operating Range  
in High-Z State .......................................–0.5V to V + 0.5V  
CC  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
Output Current into LVTTL Outputs (LOW)..................60 mA  
+3.3V  
+3.3V  
±
±
5%  
5%  
DC Input Voltage....................................–0.5V to V + 0.5V  
CC  
–40°C to +85°C  
CYP15G0401TB DC Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Test Conditions  
Min.  
Max.  
Unit  
LVTTL-compatible Outputs  
V
Output HIGH Voltage  
Output LOW Voltage  
I
I
=
−
4 mA, V = Min.  
2.4  
0
V
CC  
V
V
OHT  
OLT  
OH  
CC  
V
= 4 mA, V = Min.  
0.4  
–100  
20  
OL  
CC  
[9]  
I
I
Output Short Circuit Current  
V
= 0V  
–20  
–20  
mA  
OST  
OZL  
OUT  
High-Z Output Leakage Current  
µA  
LVTTL-compatible Inputs  
V
V
Input HIGH Voltage  
Input LOW Voltage  
Input HIGH Current  
2.0  
V
+ 0.3  
CC  
V
IHT  
ILT  
–0.5  
0.8  
1.5  
V
I
REFCLK Input, V = V  
mA  
IHT  
IN  
CC  
Other Inputs, V = V  
+40  
–1.5  
–40  
µA  
IN  
CC  
I
Input LOW Current  
REFCLK Input, V = 0.0V  
mA  
ILT  
IN  
Other Inputs, V = 0.0V  
µA  
µA  
µA  
IN  
I
I
Input HIGH Current with internal pull-down V = V  
CC  
+200  
–200  
IHPDT  
IN  
Input LOW Current with internal pull-up  
V = 0.0V  
IN  
ILPUT  
LVDIFF Inputs: REFCLK±  
[10]  
V
V
V
V
Input Differential Voltage  
Highest Input HIGH Voltage  
Lowest Input LOW voltage  
Common Mode Range  
400  
1.2  
0.0  
1.0  
V
V
mV  
V
DIFF  
CC  
IHHP  
CC  
V
V
ILLP  
CC/2  
[11]  
V
– 1.2V  
CC  
V
COMREF  
Three-level Inputs  
V
Three-level Input HIGH Voltage  
Min.  
Min.  
Min.  
≤
≤
≤
V
≤
≤
≤
Max.  
Max.  
Max.  
0.87 * V  
0.47 * V  
0.0  
V
CC  
V
V
V
IHH  
IMM  
ILL  
CC  
CC  
V
V
I
Three-level Input MID Voltage  
Three-level Input LOW Voltage  
Input HIGH Current  
V
0.53 * V  
0.13 * V  
200  
CC  
CC  
CC  
V
CC  
CC  
V
V
V
= V  
CC  
µA  
µA  
µA  
IHH  
IN  
IN  
IN  
I
I
Input MID current  
= V /2  
–50  
50  
IMM  
ILL  
CC  
Input LOW current  
= GND  
–200  
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±  
V
Output HIGH Voltage  
(V referenced)  
100  
150  
Ω
Ω
differential load  
differential load  
V
– 0.5  
– 0.5  
V
V
– 0.2  
– 0.2  
V
OHC  
CC  
CC  
CC  
CC  
V
V
CC  
Notes:  
9. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.  
10. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the  
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.  
11. The common mode range defines the allowable range of REFCLK+ and REFCLK− when REFCLK+ = REFCLK−. This marks the zero-crossing between the true  
and complement inputs as the signal switches between a logic-1 and a logic-0.  
Document #: 38-02112 Rev. **  
Page 15 of 30  
PRELIMINARY  
CYP15G0401TB  
CYP15G0401TB DC Electrical Characteristics Over the Operating Range (continued)  
Parameter  
Description  
Output LOW Voltage  
Test Conditions  
differential load  
differential load  
differential load  
differential load  
Min.  
Max.  
V – 0.7  
CC  
Unit  
V
V
V
100  
150  
100  
150  
Ω
Ω
Ω
Ω
V
V
– 1.4  
OLC  
CC  
CC  
(V referenced)  
CC  
– 1.4  
V
– 0.7  
V
CC  
Output Differential Voltage  
|(OUT+) – (OUT–)|  
450  
560  
900  
mV  
mV  
ODIF  
1000  
Power Supply  
Parameter  
Description  
Test Conditions  
Typ.[12]  
Max.[13]  
770  
Unit  
mA  
mA  
mA  
mA  
I
Power Supply Current  
REFCLK = Max.  
Commercial  
Industrial  
610  
CC  
820  
I
Power Supply Current  
REFCLK = 125 MHz  
Commercial  
Industrial  
590  
750  
CC  
800  
Test Loads and Waveforms  
3.3V  
RL = 100Ω  
R
L
R1  
R2  
R1 = 590Ω  
R2 = 435Ω  
CL ≤ 7 pF  
CL  
[14]  
(Includes fixture and  
probe capacitance)  
(b) CML Output Test Load  
[14]  
(a) LVTTL Output Test Load  
3.0V  
2.0V  
0.8V  
2.0V  
Vth = 1.4V  
GND  
Vth = 1.4V  
0.8V  
≤ 1 ns  
≤ 1 ns  
[15]  
(c) LVTTL Input Test Waveform  
CYP15G0401TB AC Characteristics Over the Operating Range  
Parameter  
Description  
Min.  
Max.  
Unit  
CYP15G0401TB Transmitter LVTTL Switching Characteristics Over the Operating Range  
f
t
t
t
t
t
t
t
f
t
TXCLKx Clock Frequency  
TXCLKx Period  
19.5  
6.66  
2.2  
150  
MHz  
ns  
TS  
51.28  
TXCLK  
TXCLKH  
TXCLKL  
TXCLKR  
TXCLKF  
TXDS  
[16]  
TXCLKx HIGH Time  
ns  
[16]  
TXCLKx LOW Time  
2.2  
ns  
[16, 17, 18]  
[16, 17, 18]  
TXCLKx Rise Time  
0.2  
1.7  
1.7  
ns  
TXCLKx Fall Time  
0.2  
ns  
Transmit Data Set-Up Time to TXCLKx  
↑
(TXCKSEL  
(TXCKSEL  
≠
≠
LOW)  
LOW)  
1.7  
ns  
Transmit Data Hold Time from TXCLKx  
↑
0.8  
ns  
TXDH  
TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency  
TXCLKO Period  
20  
150  
MHz  
ns  
TOS  
6.66  
51.28  
TXCLKO  
Notes:  
12. Maximum I is measured with V = MAX, with all TX channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern to the associated  
CC  
CC  
remote receive channel, and outputs unloaded.  
13. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C, with all TX channels enabled and one Serial Line Driver per transmit channel  
CC  
CC  
A
sending a continuous alternating 01 pattern to the associated remote receive channel. The redundant outputs on each channel are powered down and the  
parallel outputs are unloaded.  
14. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 5-pF differential load reflects tester capacitance,  
and is recommended at low data rates only.  
15. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses the threshold voltage.  
16. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.  
17. The ratio of rise time to falling time must not vary by greater than 2:1.  
18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.  
Document #: 38-02112 Rev. **  
Page 16 of 30  
PRELIMINARY  
CYP15G0401TB  
CYP15G0401TB AC Characteristics Over the Operating Range (continued)  
Parameter  
Description  
TXCLKO+ Duty Cycle with 60% HIGH time  
TXCLKO– Duty Cycle with 40% HIGH time  
Min.  
–1.0  
–0.5  
Max.  
+0.5  
+1.0  
Unit  
ns  
t
t
TXCLKOD+  
TXCLKOD–  
ns  
CYP15G0401TB REFCLK Switching Characteristics Over the Operating Range  
[19]  
f
t
t
REFCLK Clock Frequency  
19.5  
6.66  
5.9  
150  
MHz  
ns  
ns  
ns  
ns  
ns  
%
REF  
REFCLK Period  
51.28  
REFCLK  
REFH  
REFCLK HIGH Time (TXRATE = HIGH)  
REFCLK HIGH Time (TXRATE = LOW)  
REFCLK LOW Time (TXRATE = HIGH)  
REFCLK LOW Time (TXRATE = LOW)  
REFCLK Duty Cycle  
[16]  
2.9  
5.9  
t
REFL  
[16]  
2.9  
[20]  
t
t
t
t
t
30  
70  
2
REFD  
REFR  
REFF  
[16, 17, 18]  
[16, 17, 18]  
REFCLK Rise Time (20% – 80%)  
REFCLK Fall Time (20% – 80%)  
Transmit Data Setup Time to REFCLK (TXCKSEL  
ns  
ns  
ns  
ns  
2
=
LOW)  
= LOW)  
1.7  
0.8  
TREFDS  
TREFDH  
Transmit Data Hold Time from REFCLK (TXCKSEL  
CYP15G0401TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range  
Parameter  
Description  
Condition  
Min.  
5100  
60  
Max.  
649  
270  
500  
1000  
270  
500  
1000  
25  
Unit  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
us  
t
t
Bit Time  
B
[16]  
CML Output Rise Time 20% – 80% (CML Test  
Load)  
SPDSEL = HIGH  
SPDSEL = MID  
SPDSEL = LOW  
SPDSEL = HIGH  
SPDSEL = MID  
SPDSEL = LOW  
RISE  
FALL  
100  
180  
60  
[16]  
t
CML Output Fall Time 80% – 20% (CML Test  
Load)  
100  
180  
[16, 21, 23]  
[16, 22, 23]  
24  
t
t
t
Deterministic Jitter (peak-peak)  
IEEE 802.3z[ ]  
DJ  
RJ  
[24  
Random Jitter (  
σ)  
IEEE 802.3z  
]
11  
Transmit PLL lock to REFCLK  
200  
TXLOCK  
Capacitance[16]  
Parameter  
Description  
TTL Input Capacitance  
PECL input Capacitance  
Test Conditions  
Max.  
Unit  
C
C
T = 25°C, f = 1 MHz, V = 3.3V  
7
4
pF  
pF  
INTTL  
A
0
CC  
T = 25°C, f = 1 MHz, V = 3.3V  
INPECL  
A
0
CC  
Notes:  
19. While transmitting to a remote HOTLink II receiver the frequency difference between the transmitter and receiver reference clocks must be within ±1500-PPM.  
While transmitting to an unknown remote receiver compliant to a particular standard, the stability of the crystal needs to be within the limits specified by the  
appropriate standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant, the frequency stability of the crystal needs to be within ±100 PPM.  
20. The duty cycle specification is a simultaneous condition with the t  
and t  
parameters. This means that at faster character rates the REFCLK duty cycle  
REFH  
REFL  
cannot be as large as 30% – 70%.  
21. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range.  
22. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating  
range.  
23. Total jitter is calculated at an assumed BER of 1E –12. Hence: total jitter (t ) = (t * 14) + t .  
DJ  
J
RJ  
24. Also meets all Jitter Generation requirements as specified by OBSAI RP3, CPRI, ESCON, FICON, Fibre Channel and DVB-ASI.  
Document #: 38-02112 Rev. **  
Page 17 of 30  
PRELIMINARY  
CYP15G0401TB  
CYP15G0401TB HOTLink II Transmitter Switching Waveforms  
Transmit Interface Write Timing  
TXCKSEL ≠ LOW  
t
TXCLK  
t
t
TXCLKL  
TXCLKH  
TXCLKx  
t
TXDS  
TXDx[7:0],  
TXCTx[1:0],  
TXOPx,  
SCSEL  
t
TXDH  
Transmit Interface Write Timing  
TXCKSEL = LOW  
TXRATE = LOW  
t
REFCLK  
t
t
REFL  
REFH  
REFCLK  
t
TREFDS  
TXDx[7:0],  
TXCTx[1:0],  
TXOPx,  
SCSEL  
t
TREFDH  
Transmit Interface  
Write Timing  
t
REFCLK  
Note 25  
TXCKSEL = LOW  
TXRATE = HIGH  
t
t
REFL  
REFH  
Note 25  
REFCLK  
t
t
TREFDS  
TREFDS  
TXDx[7:0],  
TXCTx[1:0],  
TXOPx,  
SCSEL  
t
t
TREFDH  
TREFDH  
Transmit Interface  
TXCLKO Timing  
TXCKSEL = LOW  
TXRATE = HIGH  
t
REFCLK  
t
tREFL  
REFH  
REFCLK  
t
TXCLKO  
Note 27  
t
t
TXCLKOD+  
TXCLKOD  
–
Note 26  
TXCLKO  
Notes:  
25. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW), data  
is captured using both the rising and falling edges of REFCLK.  
26. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the duty  
cycle of REFCLK.  
27. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.  
Document #: 38-02112 Rev. **  
Page 18 of 30  
PRELIMINARY  
CYP15G0401TB  
CYP15G0401TB HOTLink II Transmitter Switching Waveforms (continued)  
Transmit Interface  
TXCLKO Timing  
TXCKSEL = LOW  
TXRATE = LOW  
t
REFCLK  
t
t
REFH  
REFL  
Note 26  
REFCLK  
TXCLKO  
t
TXCLKO  
t
Note 27  
t
TXCLKOD+  
TXCLKOD  
–
Document #: 38-02112 Rev. **  
Page 19 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 10.Package Coordinate Signal Allocation  
Ball  
ID  
Ball  
ID  
Ball  
ID  
Signal Name  
N/C  
Signal Type  
NO CONNECT  
CML OUT  
NO CONNECT  
CML OUT  
POWER  
Signal Name  
VCC  
Signal Type  
Signal Name  
Signal Type  
POWER  
A01  
A02  
A03  
A04  
A05  
A06  
A07  
A08  
A09  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
B01  
B02  
B03  
B04  
B05  
B06  
B07  
B08  
B09  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
C01  
C02  
C03  
C04  
C05  
C06  
C07  
C08  
C09  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
D01  
D02  
D03  
D04  
D05  
D06  
D07  
D08  
D09  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
E01  
E02  
E03  
E04  
E17  
E18  
POWER  
POWER  
E19  
E20  
F01  
F02  
F03  
F04  
F17  
F18  
F19  
F20  
G01  
G02  
G03  
G04  
G17  
G18  
G19  
G20  
H01  
H02  
H03  
H04  
H17  
H18  
H19  
H20  
J01  
J02  
J03  
J04  
J17  
J18  
J19  
J20  
K01  
K02  
K03  
K04  
K17  
K18  
K19  
K20  
L01  
VCC  
VCC  
OUTC1–  
N/C  
VCC  
POWER  
PARCTL  
N/C  
3-LEVEL SEL  
NO CONNECT  
GROUND  
TXPERC  
TXOPC  
TXDC[0]  
N/C  
LVTTL OUT  
LVTTL IN PU  
LVTTL IN  
OUTC2–  
VCC  
GND  
N/C  
NO CONNECT  
CML OUT  
GROUND  
GROUND  
CML OUT  
GROUND  
CML OUT  
GROUND  
NO CONNECT  
CML OUT  
POWER  
BOE[7]  
BOE[5]  
BOE[3]  
BOE[1]  
GND  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
NO CONNECT  
LVTTL IN PU  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL IN  
OUTD1–  
GND  
BISTLE  
N/C  
GND  
N/C  
OUTD2–  
GND  
N/C  
TXMODE[0]  
GND  
3-LEVEL SEL  
GROUND  
TXDC[7]  
TXCKSEL  
TXDC[4]  
TXDC[1]  
GND  
OUTA1–  
GND  
3-LEVEL SEL  
LVTTL IN  
VCC  
POWER  
N/C  
TXRATE  
GND  
LVTTL IN PD  
GROUND  
LVTTL IN  
OUTA2–  
VCC  
GROUND  
GND  
GROUND  
OELE  
N/C  
LVTTL IN PU  
NO CONNECT  
NO CONNECT  
GROUND  
N/C  
NO CONNECT  
CML OUT  
NO CONNECT  
CML OUT  
POWER  
TDO  
LVTTL 3-S OUT  
LVTTL IN PD  
LVTTL IN PU  
POWER  
OUTB1–  
N/C  
TCLK  
TRSTZ  
VCC  
N/C  
GND  
OUTB2–  
VCC  
GND  
GROUND  
VCC  
POWER  
GND  
GROUND  
OUTC1+  
VCC  
CML OUT  
POWER  
VCC  
POWER  
GND  
GROUND  
VCC  
POWER  
GND  
GROUND  
OUTC2+  
VCC  
CML OUT  
POWER  
SPDSEL  
GND  
3-LEVEL SEL  
GROUND  
GND  
GROUND  
GND  
GROUND  
VCC  
POWER  
BOE[6]  
BOE[4]  
BOE[2]  
BOE[0]  
GND  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PU  
GROUND  
GND  
GROUND  
OUTD1+  
GND  
CML OUT  
GROUND  
NO CONNECT  
CML OUT  
NO CONNECT  
CML OUT  
GROUND  
GROUND  
CML OUT  
POWER  
TXCTC[1]  
TXDC[5]  
TXDC[2]  
TXDC[3]  
N/C  
LVTTL IN  
LVTTL IN  
N/C  
LVTTL IN  
OUTD2+  
N/C  
LVTTL IN  
TXMODE[1]  
GND  
3-LEVEL SEL  
GROUND  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL IN  
OUTA1+  
GND  
N/C  
VCC  
POWER  
N/C  
GND  
VCC  
POWER  
N/C  
OUTA2+  
VCC  
GND  
GROUND  
N/C  
N/C  
NO CONNECT  
NO CONNECT  
POWER  
N/C  
VCC  
POWER  
N/C  
TXCTC[0]  
N/C  
OUTB1+  
GND  
CML OUT  
GROUND  
CML OUT  
LVTTL IN PU  
LVTTL IN PU  
POWER  
VCC  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
VCC  
POWER  
N/C  
OUTB2+  
TDI  
VCC  
POWER  
N/C  
VCC  
POWER  
N/C  
TMS  
VCC  
POWER  
N/C  
VCC  
VCC  
POWER  
N/C  
Document #: 38-02112 Rev. **  
Page 20 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 10.Package Coordinate Signal Allocation (continued)  
Ball  
ID  
Ball  
ID  
Ball  
ID  
Signal Name  
N/C  
Signal Type  
NO CONNECT  
LVTTL IN PD  
LVTTL IN  
Signal Name  
VCC  
Signal Type  
Signal Name  
Signal Type  
NO CONNECT  
LVTTL IN  
L02  
L03  
L04  
L17  
L18  
L19  
L20  
M01  
M02  
M03  
M04  
M17  
M18  
M19  
M20  
N01  
N02  
N03  
N04  
N17  
N18  
N19  
N20  
P01  
P02  
P03  
P04  
P17  
P18  
P19  
P20  
R01  
R02  
R03  
R04  
R17  
R18  
R19  
R20  
T01  
T02  
T03  
T04  
T17  
T18  
T19  
T20  
U01  
U02  
U03  
U04  
U05  
U06  
U07  
U08  
U09  
U10  
U11  
U12  
U13  
U14  
U15  
U16  
U17  
U18  
U19  
U20  
V01  
V02  
V03  
V04  
V05  
V06  
V07  
V08  
V09  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
POWER  
POWER  
V20  
W01  
W02  
W03  
W04  
W05  
W06  
W07  
W08  
W09  
W10  
W11  
W12  
W13  
W14  
W15  
W16  
W17  
W18  
W19  
W20  
Y01  
Y02  
Y03  
Y04  
Y05  
Y06  
Y07  
Y08  
Y09  
Y10  
Y11  
N/C  
TXDD[5]  
TXDD[7]  
N/C  
TXCLKC  
TXDC[6]  
N/C  
VCC  
VCC  
POWER  
LVTTL IN  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL IN  
VCC  
POWER  
NO CONNECT  
NO CONNECT  
POWER  
N/C  
TXDD[0]  
TXDD[1]  
TXDD[2]  
TXCTD[1]  
VCC  
LVTTL IN  
N/C  
N/C  
LVTTL IN  
VCC  
TXDB[6]  
N/C  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
GROUND  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL IN  
LVTTL IN  
N/C  
N/C  
POWER  
GND  
N/C  
N/C  
NO CONNECT  
NO CONNECT  
GROUND  
TXCLKO–  
TXRST  
TXOPA  
SCSEL  
GND  
LVTTL OUT  
LVTTL IN PU  
LVTTL IN PU  
LVTTL IN PD  
GROUND  
N/C  
N/C  
TXCTB[1]  
TXCTB[0]  
TXDB[7]  
TXCLKB  
GND  
GND  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
PECL IN  
LVTTL IN  
N/C  
LVTTL IN PD  
GROUND  
REFCLK–  
TXDA[1]  
GND  
TXDA[2]  
TXDA[6]  
VCC  
LVTTL IN  
LVTTL IN  
LVTTL IN  
GND  
GROUND  
GROUND  
POWER  
GND  
GROUND  
TXDA[4]  
TXCTA[0]  
VCC  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL IN  
GND  
GROUND  
LVTTL IN  
N/C  
GND  
GROUND  
POWER  
N/C  
GND  
GROUND  
N/C  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL IN  
N/C  
GND  
GROUND  
N/C  
TXDD[6]  
TXCLKD  
N/C  
GND  
GROUND  
N/C  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
NO CONNECT  
NO CONNECT  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
POWER  
N/C  
TXDD[3]  
TXDD[4]  
TXCTD[0]  
N/C  
N/C  
N/C  
LVTTL IN  
VCC  
N/C  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
GROUND  
TXDB[5]  
TXDB[4]  
TXDB[3]  
TXDB[2]  
N/C  
NO CONNECT  
POWER  
N/C  
LVTTL IN  
VCC  
GND  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
GROUND  
TXCLKO+  
N/C  
LVTTL OUT  
NO CONNECT  
LVTTL IN PD  
LVTTL OUT  
GROUND  
LVTTL IN  
N/C  
NO CONNECT  
NO CONNECT  
LVTTL OUT  
LVTTL IN PU  
LVTTL IN  
GND  
TXCLKA  
TXPERA  
GND  
N/C  
N/C  
NO CONNECT  
NO CONNECT  
PECL IN  
Y12  
Y13  
Y14  
Y15  
Y16  
Y17  
Y18  
Y19  
Y20  
TXPERD  
TXOPD  
TXDB[1]  
TXDB[0]  
TXOPB  
TXPERB  
VCC  
N/C  
REFCLK+  
N/C  
TXDA[0]  
TXDA[5]  
VCC  
LVTTL IN  
NO CONNECT  
GROUND  
LVTTL IN  
LVTTL IN  
GND  
POWER  
LVTTL IN PU  
LVTTL OUT  
POWER  
TXDA[3]  
TXDA[7]  
VCC  
LVTTL IN  
TXCTA[1]  
N/C  
LVTTL IN  
LVTTL IN  
NO CONNECT  
NO CONNECT  
NO CONNECT  
POWER  
N/C  
VCC  
POWER  
N/C  
NO CONNECT  
NO CONNECT  
NO CONNECT  
N/C  
VCC  
POWER  
N/C  
VCC  
POWER  
N/C  
Document #: 38-02112 Rev. **  
Page 21 of 30  
PRELIMINARY  
CYP15G0401TB  
composed of the bits E, D, C, B, and A in that order, and the y  
is the decimal value of the binary number composed of the bits  
H, G, and F in that order. When c is set to K, xx and y are  
derived by comparing the encoded bit patterns of the Special  
Character to those patterns derived from encoded Valid Data  
bytes and selecting the names of the patterns most similar to  
the encoded bit patterns of the Special Character.  
X3.230 Codes and Notation Conventions  
Information to be transmitted over a serial link is encoded eight  
bits at a time into a 10-bit Transmission Character and then  
sent serially, bit by bit. Information received over a serial link  
is collected ten bits at a time, and those Transmission  
Characters that are used for data characters are decoded into  
the correct eight-bit codes. The 10-bit Transmission Code  
supports all 256 eight-bit combinations. Some of the remaining  
Transmission Characters (Special Characters) are used for  
functions other than data transmission.  
Under the above conventions, the Transmission Character  
used for the examples above, is referred to by the name D5.2.  
The Special Character K29.7 is so named because the first six  
bits (abcdei) of this character make up a bit pattern similar to  
that resulting from the encoding of the unencoded 11101  
pattern (29), and because the second four bits (fghj) make up  
a bit pattern similar to that resulting from the encoding of the  
unencoded 111 pattern (7). This definition of the 10-bit Trans-  
mission Code is based on the following references.  
The primary use of a Transmission Code is to improve the  
transmission characteristics of a serial link. The encoding  
defined by the Transmission Code ensures that sufficient  
transitions are present in the serial bit stream to make clock  
recovery possible at the Receiver. Such encoding also greatly  
increases the likelihood of detecting any single or multiple bit  
errors that may occur during transmission and reception of  
information. In addition, some Special Characters of the Trans-  
mission Code selected by Fibre Channel Standard contain a  
distinct and easily recognizable bit pattern that assists the  
receiver in achieving character alignment on the incoming bit  
stream.  
A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-  
tioned-Block, 8B/10B Transmission Code” IBM Journal of  
Research and Development, 27, No. 5: 440-451 (September,  
1983).  
U.S. Patent 4,486,739. Peter A. Franaszek and Albert X.  
Widmer. “Byte-Oriented DC Balanced (0.4) 8B/10B Parti-  
tioned Block Transmission Code” (December 4, 1984).  
Notation Conventions  
Fibre Channel Physical and Signaling Interface (ANS  
X3.230-1994 ANSI FC-PH Standard).  
The documentation for the 8B/10B Transmission Code uses  
letter notation for the bits in an eight-bit byte. Fibre Channel  
Standard notation uses a bit notation of A, B, C, D, E, F, G, H  
for the eight-bit byte for the raw eight-bit data, and the letters  
a, b, c, d, e, i, f, g, h, j for encoded 10-bit data. There is a  
correspondence between bit A and bit a, B and b, C and c, D  
and d, E and e, F and f, G and g, and H and h. Bits i and j are  
derived, respectively, from (A,B,C,D,E) and (F,G,H).  
IBM Enterprise Systems Architecture/390 ESCON I/O  
Interface (document number SA22-7202).  
8B/10B Transmission Code  
The following information describes how the tables are used  
for both generating valid Transmission Characters (encoding)  
and checking the validity of received Transmission Characters  
(decoding). It also specifies the ordering rules to be followed  
when transmitting the bits within a character and the  
characters within any higher-level constructs specified by a  
standard.  
The bit labeled A in the description of the 8B/10B Transmission  
Code corresponds to bit 0 in the numbering scheme of the  
FC-2 specification, B corresponds to bit 1, as shown below.  
FC-2 bit designation—  
HOTLink D/Q designation—7  
8B/10B bit designation— H  
7
6
6
G
5
5
F
4
4
E
3
3
D
2
2
C
1
1
B
0
0
A
Transmission Order  
To clarify this correspondence, the following example shows  
the conversion from an FC-2 Valid Data Byte to a Transmission  
Character.  
Within the definition of the 8B/10B Transmission Code, the bit  
positions of the Transmission Characters are labeled a, b, c,  
d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c,  
d, e, i, f, g, h, and j in that order.  
FC-2 45H  
Bits: 7654 3210  
0100 0101  
Note that bit i is transmitted between bit e and bit f, rather than  
in alphabetical order.  
Converted to 8B/10B notation, note that the order of bits has  
been reversed):  
Valid and Invalid Transmission Characters  
The following tables define the valid Data Characters and valid  
Special Characters (K characters), respectively. The tables  
are used for both generating valid Transmission Characters  
and checking the validity of received Transmission  
Characters. In the tables, each Valid-Data-byte or  
Special-Character-code entry has two columns that represent  
two Transmission Characters. The two columns correspond to  
the current value of the running disparity. Running disparity is  
a binary parameter with either a negative (–) or positive (+)  
value.  
Data Byte Name D5.2  
Bits: ABCDE FGH  
10100 010  
Translated to a transmission Character in the 8B/10B Trans-  
mission Code:  
Bits: abcdei fghj  
101001 0101  
Each valid Transmission Character of the 8B/10B Trans-  
mission Code has been given a name using the following  
convention: cxx.y, where c is used to show whether the Trans-  
mission Character is a Data Character (c is set to D, and SC/D  
= LOW) or a Special Character (c is set to K, and SC/D = HIGH).  
When c is set to D, xx is the decimal value of the binary number  
After powering on, the Transmitter may assume either a  
positive or negative value for its initial running disparity. Upon  
transmission of any Transmission Character, the transmitter  
will select the proper version of the Transmission Character  
based on the current running disparity value, and the Trans-  
Document #: 38-02112 Rev. **  
Page 22 of 30  
PRELIMINARY  
CYP15G0401TB  
mitter calculates a new value for its running disparity based on  
the contents of the transmitted character. Special Character  
codes C1.7 and C2.7 can be used to force the transmission of  
a specific Special Character with a specific running disparity  
as required for some special sequences in X3.230.  
byte or Special Character byte to be encoded and transmitted.  
Table 11shows naming notations and examples of valid trans-  
mission characters.  
Use of the Tables for Checking the Validity of Received  
Transmission Characters  
After powering on, the Receiver may assume either a positive  
or negative value for its initial running disparity. Upon reception  
of any Transmission Character, the Receiver decides whether  
the Transmission Character is valid or invalid according to the  
following rules and tables and calculates a new value for its  
Running Disparity based on the contents of the received  
character.  
The column corresponding to the current value of the  
Receiver’s running disparity is searched for the received  
Transmission Character. If the received Transmission  
Character is found in the proper column, then the Trans-  
mission Character is valid and the associated Data byte or  
Special Character code is determined (decoded). If the  
received Transmission Character is not found in that column,  
then the Transmission Character is invalid. This is called a  
code violation. Independent of the Transmission Character’s  
validity, the received Transmission Character is used to  
calculate a new value of running disparity. The new value is  
used as the Receiver’s current running disparity for the next  
received Transmission Character.  
The following rules for running disparity are used to calculate  
the new running-disparity value for Transmission Characters  
that have been transmitted and received.  
Running disparity for a Transmission Character is calculated  
from sub-blocks, where the first six bits (abcdei) form one  
sub-block and the second four bits (fghj) form the other  
sub-block. Running disparity at the beginning of the six-bit  
sub-block is the running disparity at the end of the previous  
Transmission Character. Running disparity at the beginning of  
the four-bit sub-block is the running disparity at the end of the  
six-bit sub-block. Running disparity at the end of the Trans-  
mission Character is the running disparity at the end of the  
four-bit sub-block.  
Table 11.Valid Transmission Characters  
Data  
DIN or QOUT  
Byte Name  
765  
43210  
Hex Value  
D0.0  
000  
00000  
00  
Running disparity for the sub-blocks is calculated as follows:  
D1.0  
D2.0  
000  
000  
00001  
00010  
01  
02  
1. Running disparity at the end of any sub-block is positive if  
the sub-block contains more ones than zeros. It is also pos-  
itive at the end of the six-bit sub-block if the six-bit sub-block  
is 000111, and it is positive at the end of the four-bit  
sub-block if the four-bit sub-block is 0011.  
.
.
.
.
.
.
.
.
2. Running disparity at the end of any sub-block is negative if  
the sub-block contains more zeros than ones. It is also  
negative at the end of the six-bit sub-block if the six-bit  
sub-block is 111000, and it is negative at the end of the  
six-bit sub-block if the four-bit sub-block is 1100.  
D5.2  
010  
00101  
45  
.
.
.
.
.
.
.
.
3. Otherwise, running disparity at the end of the sub-block is  
the same as at the beginning of the sub-block.  
D30.7  
D31.7  
111  
111  
11110  
11111  
FE  
FF  
Use of the Tables for Generating Transmission Characters  
Detection of a code violation does not necessarily show that  
the Transmission Character in which the code violation was  
detected is in error. Code violations may result from a prior  
error that altered the running disparity of the bit stream which  
did not result in a detectable error at the Transmission  
Character in which the error occurred. Table 11 shows an  
example of this behavior.  
The appropriate entry in Table 13 for the Valid Data byte or  
Table 14 for Special Character byte identify which Trans-  
mission Character is to be generated. The current value of the  
Transmitter’s running disparity is used to select the Trans-  
mission Character from its corresponding column. For each  
Transmission Character transmitted, a new value of the  
running disparity is calculated. This new value is used as the  
Transmitter’s current running disparity for the next Valid Data  
Table 12.Code Violations Resulting from Prior Errors  
RD  
–
Character  
D21.1  
RD  
–
Character  
D10.2  
RD  
–
Character  
D23.5  
RD  
+
Transmitted data character  
Transmitted bit stream  
Bit stream after error  
–
101010 1001  
101010 1011  
D21.0  
–
010101 0101  
010101 0101  
D10.2  
–
111010 1010  
111010 1010  
Code Violation  
+
–
+
+
+
Decoded data character  
–
+
+
+
Document #: 38-02112 Rev. **  
Page 23 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 13.Valid Data Characters (TXCTx[0] = 0)  
Data  
Data  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Byte  
Name HGF EDCBA  
Byte  
abcdei fghj  
Name HGF EDCBA  
D0.0  
D1.0  
000 00000  
000 00001  
000 00010  
000 00011  
000 00100  
000 00101  
000 00110  
000 00111  
000 01000  
000 01001  
000 01010  
000 01011  
000 01100  
000 01101  
000 01110  
000 01111  
000 10000  
000 10001  
000 10010  
000 10011  
000 10100  
000 10101  
000 10110  
000 10111  
000 11000  
000 11001  
000 11010  
000 11011  
000 11100  
000 11101  
000 11110  
000 11111  
100111 0100 011000 1011  
011101 0100 100010 1011  
101101 0100 010010 1011  
110001 1011 110001 0100  
110101 0100 001010 1011  
101001 1011 101001 0100  
011001 1011 011001 0100  
111000 1011 000111 0100  
111001 0100 000110 1011  
100101 1011 100101 0100  
010101 1011 010101 0100  
110100 1011 110100 0100  
001101 1011 001101 0100  
101100 1011 101100 0100  
011100 1011 011100 0100  
010111 0100 101000 1011  
011011 0100 100100 1011  
100011 1011 100011 0100  
010011 1011 010011 0100  
110010 1011 110010 0100  
001011 1011 001011 0100  
101010 1011 101010 0100  
011010 1011 011010 0100  
111010 0100 000101 1011  
110011 0100 001100 1011  
100110 1011 100110 0100  
010110 1011 010110 0100  
110110 0100 001001 1011  
001110 1011 001110 0100  
101110 0100 010001 1011  
011110 0100 100001 1011  
101011 0100 010100 1011  
D0.1  
D1.1  
001 00000  
001 00001  
001 00010  
001 00011  
001 00100  
001 00101  
001 00110  
001 00111  
001 01000  
001 01001  
001 01010  
001 01011  
001 01100  
001 01101  
001 01110  
001 01111  
001 10000  
001 10001  
001 10010  
001 10011  
001 10100  
001 10101  
001 10110  
001 10111  
001 11000  
001 11001  
001 11010  
001 11011  
001 11100  
001 11101  
001 11110  
001 11111  
100111 1001 011000 1001  
011101 1001 100010 1001  
101101 1001 010010 1001  
110001 1001 110001 1001  
110101 1001 001010 1001  
101001 1001 101001 1001  
011001 1001 011001 1001  
111000 1001 000111 1001  
111001 1001 000110 1001  
100101 1001 100101 1001  
010101 1001 010101 1001  
110100 1001 110100 1001  
001101 1001 001101 1001  
101100 1001 101100 1001  
011100 1001 011100 1001  
010111 1001 101000 1001  
011011 1001 100100 1001  
100011 1001 100011 1001  
010011 1001 010011 1001  
110010 1001 110010 1001  
001011 1001 001011 1001  
101010 1001 101010 1001  
011010 1001 011010 1001  
111010 1001 000101 1001  
110011 1001 001100 1001  
100110 1001 100110 1001  
010110 1001 010110 1001  
110110 1001 001001 1001  
001110 1001 001110 1001  
101110 1001 010001 1001  
011110 1001 100001 1001  
101011 1001 010100 1001  
D2.0  
D2.1  
D3.0  
D3.1  
D4.0  
D4.1  
D5.0  
D5.1  
D6.0  
D6.1  
D7.0  
D7.1  
D8.0  
D8.1  
D9.0  
D9.1  
D10.0  
D11.0  
D12.0  
D13.0  
D14.0  
D15.0  
D16.0  
D17.0  
D18.0  
D19.0  
D20.0  
D21.0  
D22.0  
D23.0  
D24.0  
D25.0  
D26.0  
D27.0  
D28.0  
D29.0  
D30.0  
D31.0  
D10.1  
D11.1  
D12.1  
D13.1  
D14.1  
D15.1  
D16.1  
D17.1  
D18.1  
D19.1  
D20.1  
D21.1  
D22.1  
D23.1  
D24.1  
D25.1  
D26.1  
D27.1  
D28.1  
D29.1  
D30.1  
D31.1  
Document #: 38-02112 Rev. **  
Page 24 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 13.Valid Data Characters (TXCTx[0] = 0) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.2  
D1.2  
010 00000  
010 00001  
010 00010  
010 00011  
010 00100  
010 00101  
010 00110  
010 00111  
010 01000  
010 01001  
010 01010  
010 01011  
010 01100  
010 01101  
010 01110  
010 01111  
010 10000  
010 10001  
010 10010  
010 10011  
010 10100  
010 10101  
010 10110  
010 10111  
010 11000  
010 11001  
010 11010  
010 11011  
010 11100  
010 11101  
010 11110  
010 11111  
100 00000  
100111 0101 011000 0101  
011101 0101 100010 0101  
101101 0101 010010 0101  
110001 0101 110001 0101  
110101 0101 001010 0101  
101001 0101 101001 0101  
011001 0101 011001 0101  
111000 0101 000111 0101  
111001 0101 000110 0101  
100101 0101 100101 0101  
010101 0101 010101 0101  
110100 0101 110100 0101  
001101 0101 001101 0101  
101100 0101 101100 0101  
011100 0101 011100 0101  
010111 0101 101000 0101  
011011 0101 100100 0101  
100011 0101 100011 0101  
010011 0101 010011 0101  
110010 0101 110010 0101  
001011 0101 001011 0101  
101010 0101 101010 0101  
011010 0101 011010 0101  
111010 0101 000101 0101  
110011 0101 001100 0101  
100110 0101 100110 0101  
010110 0101 010110 0101  
110110 0101 001001 0101  
001110 0101 001110 0101  
101110 0101 010001 0101  
011110 0101 100001 0101  
101011 0101 010100 0101  
100111 0010 011000 1101  
D0.3  
D1.3  
011 00000  
011 00001  
011 00010  
011 00011  
011 00100  
011 00101  
011 00110  
011 00111  
011 01000  
011 01001  
011 01010  
011 01011  
011 01100  
011 01101  
011 01110  
011 01111  
011 10000  
011 10001  
011 10010  
011 10011  
011 10100  
011 10101  
011 10110  
011 10111  
011 11000  
011 11001  
011 11010  
011 11011  
011 11100  
011 11101  
011 11110  
011 11111  
101 00000  
100111 0011 011000 1100  
011101 0011 100010 1100  
101101 0011 010010 1100  
110001 1100 110001 0011  
110101 0011 001010 1100  
101001 1100 101001 0011  
011001 1100 011001 0011  
111000 1100 000111 0011  
111001 0011 000110 1100  
100101 1100 100101 0011  
010101 1100 010101 0011  
110100 1100 110100 0011  
001101 1100 001101 0011  
101100 1100 101100 0011  
011100 1100 011100 0011  
010111 0011 101000 1100  
011011 0011 100100 1100  
100011 1100 100011 0011  
010011 1100 010011 0011  
110010 1100 110010 0011  
001011 1100 001011 0011  
101010 1100 101010 0011  
011010 1100 011010 0011  
111010 0011 000101 1100  
110011 0011 001100 1100  
100110 1100 100110 0011  
010110 1100 010110 0011  
110110 0011 001001 1100  
001110 1100 001110 0011  
101110 0011 010001 1100  
011110 0011 100001 1100  
101011 0011 010100 1100  
100111 1010 011000 1010  
D2.2  
D2.3  
D3.2  
D3.3  
D4.2  
D4.3  
D5.2  
D5.3  
D6.2  
D6.3  
D7.2  
D7.3  
D8.2  
D8.3  
D9.2  
D9.3  
D10.2  
D11.2  
D12.2  
D13.2  
D14.2  
D15.2  
D16.2  
D17.2  
D18.2  
D19.2  
D20.2  
D21.2  
D22.2  
D23.2  
D24.2  
D25.2  
D26.2  
D27.2  
D28.2  
D29.2  
D30.2  
D31.2  
D0.4  
D10.3  
D11.3  
D12.3  
D13.3  
D14.3  
D15.3  
D16.3  
D17.3  
D18.3  
D19.3  
D20.3  
D21.3  
D22.3  
D23.3  
D24.3  
D25.3  
D26.3  
D27.3  
D28.3  
D29.3  
D30.3  
D31.3  
D0.5  
Document #: 38-02112 Rev. **  
Page 25 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 13.Valid Data Characters (TXCTx[0] = 0) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D1.4  
D2.4  
100 00001  
100 00010  
100 00011  
100 00100  
100 00101  
100 00110  
100 00111  
100 01000  
100 01001  
100 01010  
100 01011  
100 01100  
100 01101  
100 01110  
100 01111  
100 10000  
100 10001  
100 10010  
100 10011  
100 10100  
100 10101  
100 10110  
100 10111  
100 11000  
100 11001  
100 11010  
100 11011  
100 11100  
100 11101  
100 11110  
100 11111  
011101 0010 100010 1101  
101101 0010 010010 1101  
110001 1101 110001 0010  
110101 0010 001010 1101  
101001 1101 101001 0010  
011001 1101 011001 0010  
111000 1101 000111 0010  
111001 0010 000110 1101  
100101 1101 100101 0010  
010101 1101 010101 0010  
110100 1101 110100 0010  
001101 1101 001101 0010  
101100 1101 101100 0010  
011100 1101 011100 0010  
010111 0010 101000 1101  
011011 0010 100100 1101  
100011 1101 100011 0010  
010011 1101 010011 0010  
110010 1101 110010 0010  
001011 1101 001011 0010  
101010 1101 101010 0010  
011010 1101 011010 0010  
111010 0010 000101 1101  
110011 0010 001100 1101  
100110 1101 100110 0010  
010110 1101 010110 0010  
110110 0010 001001 1101  
001110 1101 001110 0010  
101110 0010 010001 1101  
011110 0010 100001 1101  
101011 0010 010100 1101  
D1.5  
D2.5  
101 00001  
101 00010  
101 00011  
101 00100  
101 00101  
101 00110  
101 00111  
101 01000  
101 01001  
101 01010  
101 01011  
101 01100  
101 01101  
101 01110  
101 01111  
101 10000  
101 10001  
101 10010  
101 10011  
101 10100  
101 10101  
101 10110  
101 10111  
101 11000  
101 11001  
101 11010  
101 11011  
101 11100  
101 11101  
101 11110  
101 11111  
011101 1010 100010 1010  
101101 1010 010010 1010  
110001 1010 110001 1010  
110101 1010 001010 1010  
101001 1010 101001 1010  
011001 1010 011001 1010  
111000 1010 000111 1010  
111001 1010 000110 1010  
100101 1010 100101 1010  
010101 1010 010101 1010  
110100 1010 110100 1010  
001101 1010 001101 1010  
101100 1010 101100 1010  
011100 1010 011100 1010  
010111 1010 101000 1010  
011011 1010 100100 1010  
100011 1010 100011 1010  
010011 1010 010011 1010  
110010 1010 110010 1010  
001011 1010 001011 1010  
101010 1010 101010 1010  
011010 1010 011010 1010  
111010 1010 000101 1010  
110011 1010 001100 1010  
100110 1010 100110 1010  
010110 1010 010110 1010  
110110 1010 001001 1010  
001110 1010 001110 1010  
101110 1010 010001 1010  
011110 1010 100001 1010  
101011 1010 010100 1010  
D3.4  
D3.5  
D4.4  
D4.5  
D5.4  
D5.5  
D6.4  
D6.5  
D7.4  
D7.5  
D8.4  
D8.5  
D9.4  
D9.5  
D10.4  
D11.4  
D12.4  
D13.4  
D14.4  
D15.4  
D16.4  
D17.4  
D18.4  
D19.4  
D20.4  
D21.4  
D22.4  
D23.4  
D24.4  
D25.4  
D26.4  
D27.4  
D28.4  
D29.4  
D30.4  
D31.4  
D10.5  
D11.5  
D12.5  
D13.5  
D14.5  
D15.5  
D16.5  
D17.5  
D18.5  
D19.5  
D20.5  
D21.5  
D22.5  
D23.5  
D24.5  
D25.5  
D26.5  
D27.5  
D28.5  
D29.5  
D30.5  
D31.5  
Document #: 38-02112 Rev. **  
Page 26 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 13.Valid Data Characters (TXCTx[0] = 0) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.6  
D1.6  
110 00000  
110 00001  
110 00010  
110 00011  
110 00100  
110 00101  
110 00110  
110 00111  
110 01000  
110 01001  
110 01010  
110 01011  
110 01100  
110 01101  
110 01110  
110 01111  
110 10000  
110 10001  
110 10010  
110 10011  
110 10100  
110 10101  
110 10110  
110 10111  
110 11000  
110 11001  
110 11010  
110 11011  
110 11100  
110 11101  
110 11110  
110 11111  
100111 0110 011000 0110  
011101 0110 100010 0110  
101101 0110 010010 0110  
110001 0110 110001 0110  
110101 0110 001010 0110  
101001 0110 101001 0110  
011001 0110 011001 0110  
111000 0110 000111 0110  
111001 0110 000110 0110  
100101 0110 100101 0110  
010101 0110 010101 0110  
110100 0110 110100 0110  
001101 0110 001101 0110  
101100 0110 101100 0110  
011100 0110 011100 0110  
010111 0110 101000 0110  
011011 0110 100100 0110  
100011 0110 100011 0110  
010011 0110 010011 0110  
110010 0110 110010 0110  
001011 0110 001011 0110  
101010 0110 101010 0110  
011010 0110 011010 0110  
111010 0110 000101 0110  
110011 0110 001100 0110  
100110 0110 100110 0110  
010110 0110 010110 0110  
110110 0110 001001 0110  
001110 0110 001110 0110  
101110 0110 010001 0110  
011110 0110 100001 0110  
101011 0110 010100 0110  
D0.7  
D1.7  
111 00000  
111 00001  
111 00010  
111 00011  
111 00100  
111 00101  
111 00110  
111 00111  
111 01000  
111 01001  
111 01010  
111 01011  
111 01100  
111 01101  
111 01110  
111 01111  
111 10000  
111 10001  
111 10010  
111 10011  
111 10100  
111 10101  
111 10110  
111 10111  
111 11000  
111 11001  
111 11010  
111 11011  
111 11100  
111 11101  
111 11110  
111 11111  
100111 0001 011000 1110  
011101 0001 100010 1110  
101101 0001 010010 1110  
110001 1110 110001 0001  
110101 0001 001010 1110  
101001 1110 101001 0001  
011001 1110 011001 0001  
111000 1110 000111 0001  
111001 0001 000110 1110  
100101 1110 100101 0001  
010101 1110 010101 0001  
110100 1110 110100 1000  
001101 1110 001101 0001  
101100 1110 101100 1000  
011100 1110 011100 1000  
010111 0001 101000 1110  
011011 0001 100100 1110  
100011 0111 100011 0001  
010011 0111 010011 0001  
110010 1110 110010 0001  
001011 0111 001011 0001  
101010 1110 101010 0001  
011010 1110 011010 0001  
111010 0001 000101 1110  
110011 0001 001100 1110  
100110 1110 100110 0001  
010110 1110 010110 0001  
110110 0001 001001 1110  
001110 1110 001110 0001  
101110 0001 010001 1110  
011110 0001 100001 1110  
101011 0001 010100 1110  
D2.6  
D2.7  
D3.6  
D3.7  
D4.6  
D4.7  
D5.6  
D5.7  
D6.6  
D6.7  
D7.6  
D7.7  
D8.6  
D8.7  
D9.6  
D9.7  
D10.6  
D11.6  
D12.6  
D13.6  
D14.6  
D15.6  
D16.6  
D17.6  
D18.6  
D19.6  
D20.6  
D21.6  
D22.6  
D23.6  
D24.6  
D25.6  
D26.6  
D27.6  
D28.6  
D29.6  
D30.6  
D31.6  
D10.7  
D11.7  
D12.7  
D13.7  
D14.7  
D15.7  
D16.7  
D17.7  
D18.7  
D19.7  
D20.7  
D21.7  
D22.7  
D23.7  
D24.7  
D25.7  
D26.7  
D27.7  
D28.7  
D29.7  
D30.7  
D31.7  
Document #: 38-02112 Rev. **  
Page 27 of 30  
PRELIMINARY  
CYP15G0401TB  
Table 14.Valid Special Character Codes and Sequences (TXCTx = special character code) [28, 29]  
S.C. Byte Name  
Cypress  
Alternate  
S.C. Byte  
Bits  
S.C. Byte Name  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
[30]  
S.C. Code Name  
Name [30]  
HGF EDCBA  
HGF EDCBA  
abcdei fghj  
001111 0100  
001111 1001  
001111 0101  
001111 0011  
001111 0010  
001111 1010  
001111 0110  
001111 1000  
111010 1000  
110110 1000  
101110 1000  
011110 1000  
K28.0  
C0.0  
(C00)  
(C01)  
(C02)  
(C03)  
(C04)  
(C05)  
(C06)  
(C07)  
(C08)  
(C09)  
000 00000 C28.0 (C1C)  
000 00001 C28.1 (C3C)  
000 00010 C28.2 (C5C)  
000 11100  
001 11100  
010 11100  
011 11100  
100 11100  
101 11100  
110 11100  
111 11100  
111 10111  
111 11011  
111 11101  
111 11110  
110000 1011  
110000 0110  
110000 1010  
110000 1100  
110000 1101  
110000 0101  
110000 1001  
110000 0111  
000101 0111  
001001 0111  
010001 0111  
100001 0111  
[31]  
K28.1  
C1.0  
C2.0  
C3.0  
C4.0  
C5.0  
C6.0  
C7.0  
C8.0  
C9.0  
[31]  
K28.2  
K28.3  
000 00011  
C28.3 (C7C)  
[31]  
K28.4  
000 00100 C28.4 (C9C)  
000 00101 C28.5 (CBC)  
[31, 32]  
K28.5  
[31]  
K28.6  
000 00110  
000 00111  
C28.6 (CDC)  
C28.7 (CFC)  
[31, 33]  
K28.7  
K23.7  
K27.7  
K29.7  
K30.7  
000 01000 C23.7 (CF7)  
000 01001 C27.7 (CFB)  
000 01010 C29.7 (CFD)  
C10.0 (C0A)  
C11.0 (C0B)  
000 01011  
C30.7 (CFE)  
End of Frame Sequence  
[34]  
EOFxx  
C2.1  
(C22)  
001 00010 C2.1  
(C22)  
001 00010  
–K28.5, Dn.xxx0  
+K28.5, Dn.xxx1  
Code Rule Violation and SVS Tx Pattern  
[33, 35]  
[39]  
Exception  
C0.7  
C1.7  
C2.7  
(CE0)  
(CE1)  
(CE2)  
111 00000  
111 00001  
111 00010  
C0.7  
C1.7  
C2.7  
(CE0)  
(CE1)  
(CE2)  
111 00000  
100111 1000  
001111 1010  
110000 0101  
011000 0111  
001111 1010  
110000 0101  
[36]  
[39]  
−K28.5  
111 00001  
[37]  
[39]  
+K28.5  
111 00010  
Running Disparity Violation Pattern  
[38]  
[39]  
Exception  
C4.7  
(CE4)  
111 00100  
C4.7  
(CE4)  
111 00100  
110111 0101  
001000 1010  
Notes:  
28. All codes not shown are reserved.  
29. Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to  
describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through  
C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).  
30. Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes.  
31. These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON  
protocols.  
32. The K28.5 character is used for framing operations by the remote receiver. It is also the pad or fill character transmitted to maintain the serial link when no user  
data is available.  
33. Care must be taken when using this Special Character code. When a K28.7(C7.0) or SVS(C0.7) is followed by a D11.x or D20.x, an alias K28.5 sync character  
is created. These sequences can cause erroneous framing at the remote receiver and should be avoided.  
34. C2.1 = Transmit either −K28.5+ or +K28.5− as determined by Current RD and modify the Transmission Character that follows, by setting its least significant bit  
to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus (−) the LSB becomes 1. This modification  
allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.  
For example, to send “EOFdt” the controller could issue the sequence C2.1−D21.4− D21.4−D21.4, and the HOTLink II Transmitter will send either  
K28.5−D21.4−D21.4−D21.4 or K28.5−D21.5− D21.4−D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence  
C2.1−D10.4−D21.4−D21.4, and the HOTLink II Transmitter will send either K28.5−D10.4−D21.4− D21.4 or K28.5−D10.5−D21.4− D21.4 based on Current RD.  
The remote receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.  
35. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. The remote receiver will only output  
this Special Character if the Transmission Character being decoded is not found in the tables.  
36. C1.7 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD. The remote receiver will only output this Special Character if K28.5 is received with the  
wrong running disparity. The receiver will output C1.7 if −K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.  
37. C2.7 = Transmit Positive K28.5 (+K28.5−) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong running  
disparity. The receiver will output C2.7 if +K28.5 is received with RD−, otherwise K28.5 is decoded as C5.0 or C1.7.  
38. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation. The receiver will only output this Special Character if the Transmission  
Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.  
39. Supported only for data transmission. The receive status for these conditions will be reported by specific combinations of receive status bits.  
Document #: 38-02112 Rev. **  
Page 28 of 30  
PRELIMINARY  
CYP15G0401TB  
Ordering Information  
Speed  
Standard  
Standard  
Standard  
Ordering Code  
Package Name  
Package Type  
Operating Range  
CYP15G0401TB-BGC  
CYP15G0401TB-BGI  
CYP15G0401TB-BGXC  
BL256  
BL256  
BL256  
256-ball Thermally Enhanced Ball Grid Array  
256-ball Thermally Enhanced Ball Grid Array  
Commercial  
Industrial  
Pb Free 256-ball Thermally Enhanced Ball Grid Commercial  
Array  
Standard  
CYP15G0401TB-BGXI  
BL256  
Pb Free 256-ball Thermally Enhanced Ball Grid Industrial  
Array  
Package Diagram  
256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256  
TOP VIEW  
0.20ꢀ4ꢁX  
BOTTOM VIEW ꢀBALL SIDEX  
A
27.00 0.13  
Ø0.15 M C  
Ø0.30 M C  
A
B
A1 CORNER I.D.  
A1 CORNER I.D.  
24.13  
Ø0.75 0.15ꢀ256ꢁX  
20 18  
19  
16  
14  
12  
10  
8
6
4
2
17  
15  
13  
11  
9
7
5
3
1
A
B
C
D
E
F
G
H
J
R 2.5 Max ꢀ4ꢁX  
K
L
M
N
P
R
T
A
U
V
W
Y
A
0.50 MIN.  
B
1.57 0.175  
0.97 REF.  
0.15  
C
0.15  
C
26°  
TYP.  
0.60 0.10  
C
0.20 MIN  
TOP OF MOLD COMPOUND  
TO TOP OF BALLS  
SEATING PLANE  
SIDE VIEW  
51-85123-*E  
HOTLink is a registered trademark, and HOTLink II, and MultiFrame are trademarks, of Cypress Semiconductor. IBM and ESCON  
are registered trademarks, and FICON is a trademark, of International Business Machines. All product and company names  
mentioned in this document are the trademarks of their respective holders.  
Document #: 38-02112 Rev. **  
Page 29 of 30  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
PRELIMINARY  
CYP15G0401TB  
Document History Page  
Document Title: CYP15G0401TB Quad HOTLink II™ Transmitter  
Document Number: 38-02112  
ECN  
No.  
Issue  
Date  
Orig. of  
Change  
REV.  
Description of Change  
**  
318023 See ECN  
REV  
New Data Sheet  
Document #: 38-02112 Rev. **  
Page 30 of 30  
厂商 型号 描述 页数 下载

NIDEC

 		CYP [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

 		CYP-0200MB [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

 		CYP-0200MC [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

 		CYP-0200TB [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

 		CYP-0200TC [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

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NIDEC

 		CYP-0201MC [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

 		CYP-0201TB [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

 		CYP-0201TC [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

 		CYP-0202MB [ PIANO SWITCHES (FULL PITCH) ] 5 页

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