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RX5000

型号：

RX5000

描述：

433.92兆赫混合接收机[ 433.92 MHz Hybrid Receiver ]

品牌：

RFM[ RF MONOLITHICS, INC ]

页数：

11 页

PDF大小：

105 K

下载PDF手册
®
RX5000  
· Designed for Short-Range Wireless Control and Data Communications  
· Supports RF Data Transmission Rates Up to 115.2 kbps  
· 3 V, Low Current Operation plus Sleep Mode  
433.92 MHz  
Hybrid  
Receiver  
· Stable, Easy to Use, Low External Parts Count  
The RX5000 hybrid receiver is ideal for short-range wireless control and data applications where  
robust operation, small size, low power consumption and low cost are required. The RX5000  
employs RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of  
characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding de-  
sign-in. The RX5000 is sensitive and stable. A wide dynamic range log detector, in combination  
with digital AGC and a compound data slicer, provide robust performance in the presence of  
on-channel interference or noise. Two stages of SAW filtering provide excellent receiver out-  
of-band rejection. The RX5000 generates virtually no RF emissions, facilitating compliance with  
ETSI I-ETS 300 220 and similar regulations.  
Absolute Maximum Ratings  
Rating  
Power Supply and All Input/Output Pins  
Non-Operating Case Temperature  
Soldering Temperature (10 seconds)  
Value  
-0.3 to +4.0  
-50 to +100  
250  
Units  
V
oC  
oC  
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC)  
Characteristic  
Sym  
Notes  
Minimum  
433.72  
Typical  
Maximum  
Units  
Operating Frequency  
Modulation Type  
Data Rate  
fO  
434.12  
MHz  
OOK/ASK  
115.2  
kbps  
Receiver Performance, High Sensitivity Mode  
Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method  
Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method  
Current, 2.4 kbps (RPR = 330 K)  
1
1
2
1
1
2
1
1
-109  
-103  
3.0  
dBm  
dBm  
mA  
Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method  
Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method  
Current, 19.2 kbps (RPR = 330 K)  
-105  
-99  
dBm  
dBm  
mA  
3.1  
Sensitivity, 115.2 kbps, 10-3 BER, AM Test Method  
Sensitivity, 115.2 kbps, 10-3 BER, Pulse Test Method  
Current, 115.2 kbps  
-101  
-95  
dBm  
dBm  
mA  
3.8  
Receiver Performance, Low Current Mode  
Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method  
Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method  
Current, 2.4 kbps (RPR = 1100 K)  
1
1
2
-104  
-98  
dBm  
dBm  
mA  
1.8  
1
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC)  
Characteristic  
Receiver Out-of-Band Rejection, 5ꢀ fO  
Receiver Ultimate Rejection  
Sym  
Notes  
Minimum  
Typical  
80  
Maximum  
Units  
dB  
R
3
3
5ꢀ  
RULT  
IS  
100  
dB  
Sleep Mode Current  
0.7  
µA  
Power Supply Voltage Range  
Power Supply Voltage Ripple  
Ambient Operating Temperature  
VCC  
2.2  
-40  
3.7  
10  
85  
Vdc  
mVP-P  
oC  
TA  
Notes:  
1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to  
measure OOK/ASK receiver sensitivity, the “100ꢀ AM” test method and the “Pulse” test method. Sensitivity data is given for both test meth-  
ods. See Appendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to  
3.7 V supply voltage range at five operating temperatures. The application/test circuit and component values are shown on the next page and  
in the Designer’s Guide.  
2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitiv-  
ity data and receiver current are given at 2.4 kbps for both high sensitivity operation (RPR = 330 K) and low current operation (RPR = 1100 K).  
3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page.  
4. See Table 1 on Page 8 for additional information on ASH radio event timing.  
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Receiver Set-Up, 3.0 Vdc, -40 to +85 0C  
Item  
Symbol  
OOK  
OOK  
ASK  
Units  
kbps  
µs  
µs  
pF  
µF  
µF  
K
Notes  
DRNOM  
2.4  
19.2  
115.2  
8.68  
see pages 1 & 2  
single bit  
Nominal NRZ Data Rate  
Minimum Signal Pulse  
Maximum Signal Pulse  
AGCCAP Capacitor  
PKDET Capacitor  
SPMIN  
SPMAX  
CAGC  
CPKD  
CBBO  
RBBO  
CLPF  
RLPF  
RREF  
RTH2  
RTH1  
RPR  
416.67  
52.08  
1666.68  
208.32  
34.72  
2200  
0.001  
4 bits of same value  
-
-
-
10ꢀ ceramic  
10ꢀ ceramic  
10ꢀ ceramic  
5ꢀ  
-
0.015  
0
BBOUT Capacitor  
BBOUT Resistor  
0.1  
12  
0.0027  
0
LPFAUX Capacitor  
LPFADJ Resistor  
0.0047  
300  
100  
-
-
-
µF  
K
5ꢀ  
100  
100  
-
15  
5ꢀ  
RREF Resistor  
100  
100  
10  
1ꢀ  
K
THLD2 Resistor  
1ꢀ, for 6 dB below peak  
1ꢀ, typical values  
5ꢀ  
K
THLD1 Resistor  
0
0
K
PRATE Resistor  
330  
330  
160  
K
RPW  
PWIDTH Resistor  
270 to GND  
270 to GND  
1000 to Vcc  
5ꢀ  
K
DC Bypass Capacitor  
RF Bypass Capacitor 1  
Antenna Tuning Inductor  
Shunt Tuning/ESD Inductor  
CDCB  
CRFB1  
LAT  
4.7  
100  
56  
4.7  
100  
56  
4.7  
100  
56  
µF  
pF  
nH  
nH  
tantalum  
5ꢀ NPO  
50 ohm antenna  
50 ohm antenna  
LESD  
220  
220  
220  
CAUTION: Electrostatic Sensitive Device. Observe precautions when handling.  
3
ASH Receiver Theory of Operation  
that the two amplifiers are coupled by a surface acoustic wave  
(SAW) delay line, which has a typical delay of 0.5 µs.  
An incoming RF signal is first filtered by a narrow-band SAW filter,  
and is then applied to RFA1. The pulse generator turns RFA1 ON  
for 0.5 µs. The amplified signal from RFA1 emerges from the SAW  
delay line at the input to RFA2. RFA1 is now switched OFF and  
RFA2 is switched ON for 0.55 µs, amplifying the RF signal further.  
The ON time for RFA2 is usually set at 1.1 times the ON time for  
RFA1, as the filtering effect of the SAW delay line stretches the sig-  
nal pulse from RFA1 somewhat. As shown in the timing diagram,  
RFA1 and RFA2 are never on at the same time, assuring excellent  
receiver stability. Note that the narrow-band SAW filter eliminates  
sampling sideband responses outside of the receiver passband, and  
the SAW filter and delay line act together to provide very high re-  
ceiver ultimate rejection.  
Introduction  
RFM’s RX5000 series amplifier-sequenced hybrid (ASH) receivers  
are specifically designed for short-range wireless control and data  
communication applications. The receivers provide robust operation,  
very small size, low power consumption and low implementation  
cost. All critical RF functions are contained in the hybrid, simplifying  
and speeding design-in. The ASH receiver can be readily configured  
to support a wide range of data rates and protocol requirements.  
The receiver features virtually no RF emissions, making it easy to  
certify to short-range (unlicensed) radio regulations.  
Amplifier-Sequenced Receiver Operation  
The ASH receiver’s unique feature set is made possible by its sys-  
tem architecture. The heart of the receiver is the amplifier-  
sequenced receiver section, which provides more than 100 dB of  
stable RF and detector gain without any special shielding or de-  
coupling provisions. Stability is achieved by distributing the total RF  
gain over time. This is in contrast to a superheterodyne receiver,  
which achieves stability by distributing total RF gain over multiple  
frequencies.  
Amplifier-sequenced receiver operation has several interesting char-  
acteristics that can be exploited in system design. The RF amplifiers  
in an amplifier-sequenced receiver can be turned on and off almost  
instantly, allowing for very quick power-down (sleep) and wake-up  
times. Also, both RF amplifiers can be off between ON sequences  
to trade-off receiver noise figure for lower average current consump-  
tion. The effect on noise figure can be modeled as if RFA1 is on  
continuously, with an attenuator placed in front of it with a loss  
equivalent to 10*log10(RFA1 duty factor), where the duty factor is the  
average amount of time RFA1 is ON (up to 50ꢀ). Since an  
Figure 1 shows the basic block diagram and timing cycle for an am-  
plifier-sequenced receiver. Note that the bias to RF amplifiers RFA1  
and RFA2 are independently controlled by a pulse generator, and  
amplifier-sequenced receiver is inherently a sampling receiver, the  
overall cycle time between the start of one RFA1 ON sequence and  
A
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Figure 1  
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Figure 2  
the start of the next RFA1 ON sequence should be set to sample  
range in RFA1, more than 100 dB of receiver dynamic range is  
achieved.  
the narrowest RF data pulse at least 10 times. Otherwise, significant  
edge jitter will be added to the detected data pulse.  
The detector output drives a gyrator filter. The filter provides a  
RX5000 Series ASH Receiver Block Diagram  
three-pole, 0.05 degree equiripple low-pass response with excellent  
group delay flatness and minimal pulse ringing. The 3 dB bandwidth  
of the filter can be set from 4.5 kHz to 1.8 MHz with an external re-  
sistor.  
Figure 2 is the general block diagram of the RX5000 series ASH  
receiver. Please refer to Figure 2 for the following discussions.  
Antenna Port  
The filter is followed by a base-band amplifier which boosts the de-  
tected signal to the BBOUT pin. When the receiver RF amplifiers  
are operating at a 50ꢀ-50ꢀ duty cycle, the BBOUT signal changes  
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV.  
For lower duty cycles, the mV/dB slope and peak-to-peak signal  
level are proportionately less. The detected signal is riding on a  
1.1 Vdc level that varies somewhat with supply voltage, tempera-  
ture, etc. BBOUT is coupled to the CMPIN pin or to an external data  
recovery process (DSP, etc.) by a series capacitor. The correct  
value of the series capacitor depends on data rate, data run length,  
and other factors as discussed in the ASH Transceiver Designer’s  
Guide.  
The only external RF components needed for the receiver are the  
antenna and its matching components. Antennas presenting an im-  
pedance in the range of 35 to 72 ohms resistive can be satisfactorily  
matched to the RFIO pin with a series matching coil and a shunt  
matching/ESD protection coil. Other antenna impedances can be  
matched using two or three components. For some impedances,  
two inductors and a capacitor will be required. A DC path from RFIO  
to ground is required for ESD protection.  
Receiver Chain  
The output of the SAW filter drives amplifier RFA1. This amplifier in-  
cludes provisions for detecting the onset of saturation (AGC Set),  
and for switching between 35 dB of gain and 5 dB of gain (Gain Se-  
lect). AGC Set is an input to the AGC Control function, and Gain Se-  
lect is the AGC Control function output. ON/OFF control to RFA1  
(and RFA2) is generated by the Pulse Generator & RF Amp Bias  
function. The output of RFA1 drives the SAW delay line, which has  
a nominal delay of 0.5 µs.  
When an external data recovery process is used with AGC, BBOUT  
must be coupled to the external data recovery process and CMPIN  
by separate series coupling capacitors. The AGC reset function is  
driven by the signal applied to CMPIN.  
When the receiver is placed in the power-down (sleep) mode, the  
output impedance of BBOUT becomes very high. This feature helps  
preserve the charge on the coupling capacitor to minimize data  
slicer stabilization time when the receiver switches out of the sleep  
mode.  
The second amplifier, RFA2, provides 51 dB of gain below satura-  
tion. The output of RFA2 drives a full-wave detector with 19 dB of  
threshold gain. The onset of saturation in each section of RFA2 is  
detected and summed to provide a logarithmic response. This is  
added to the output of the full-wave detector to produce an overall  
detector response that is square law for low signal levels, and tran-  
sitions into a log response for high signal levels. This combination  
provides excellent threshold sensitivity and more than 70 dB of  
detector dynamic range. In combination with the 30 dB of AGC  
Data Slicers  
The CMPIN pin drives two data slicers, which convert the analog  
signal from BBOUT back into a digital stream. The best data slicer  
choice depends on the system operating parameters. Data slicer  
DS1 is a capacitively-coupled comparator with provisions for an ad-  
justable threshold. DS1 provides the best performance at low  
5
signal-to-noise conditions. The threshold, or squelch, offsets the  
comparator’s slicing level from 0 to 90 mV, and is set with a resistor  
between the RREF and THLD1 pins. This threshold allows a trade-  
off between receiver sensitivity and output noise density in the  
no-signal condition. For best sensitivity, the threshold is set to 0. In  
this case, noise is output continuously when no signal is present.  
This, in turn, requires the circuit being driven by the RXDATA pin to  
be able to process noise (and signals) continuously.  
the PRATE and PWIDTH input pins, and the Power Down (sleep)  
Control Signal from the Bias Control function.  
In the low data rate mode, the interval between the falling edge of  
one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse  
tPRI is set by a resistor between the PRATE pin and ground. The in-  
terval can be adjusted between 0.1 and 5 µs. In the high data rate  
mode (selected at the PWIDTH pin) the receiver RF amplifiers oper-  
ate at a nominal 50ꢀ-50ꢀ duty cycle. In this case, the start-to-start  
period tPRC for ON pulses to RFA1 are controlled by the PRATE re-  
sistor over a range of 0.1 to 1.1 µs.  
This can be a problem if RXDATA is driving a circuit that must  
“sleep” when data is not present to conserve power, or when it its  
necessary to minimize false interrupts to a multitasking processor.  
In this case, noise can be greatly reduced by increasing the thresh-  
old level, but at the expense of sensitivity. The best 3 dB bandwidth  
for the low-pass filter is also affected by the threshold level setting of  
DS1. The bandwidth must be increased as the threshold is in-  
creased to minimize data pulse-width variations with signal ampli-  
tude.  
In the low data rate mode, the PWIDTH pin sets the width of the ON  
pulse tPW1 to RFA1 with a resistor to ground (the ON pulse width  
tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in the low  
data rate mode). The ON pulse width tPW1 can be adjusted between  
0.55 and 1 µs. However, when the PWIDTH pin is connected to Vcc  
through a 1 M resistor, the RF amplifiers operate at a nominal  
50ꢀ-50ꢀ duty cycle, facilitating high data rate operation. In this  
case, the RF amplifiers are controlled by the PRATE resistor as de-  
scribed above.  
Data slicer DS2 can overcome this compromise once the signal  
level is high enough to enable its operation. DS2 is a “dB-below-  
peak” slicer. The peak detector charges rapidly to the peak value of  
each data pulse, and decays slowly in between data pulses (1:1000  
ratio). The slicer trip point can be set from 0 to 120 mV below this  
peak value with a resistor between RREF and THLD2. A threshold  
of 60 mV is the most common setting, which equates to “6 dB below  
peak” when RFA1 and RFA2 are running a 50ꢀ-50ꢀ duty cycle.  
Slicing at the “6 dB-below-peak” point reduces the signal amplitude  
to data pulse-width variation, allowing a lower 3 dB filter bandwidth  
to be used for improved sensitivity.  
Both receiver RF amplifiers are turned off by the Power Down Con-  
trol Signal, which is invoked in the sleep mode.  
Receiver Mode Control  
The receiver operating modes – receive and power-down (sleep),  
are controlled by the Bias Control function, and are selected with the  
CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0  
both high place the unit in the receive mode. Setting CNTRL1 and  
CNTRL0 both low place the unit in the power-down (sleep) mode.  
CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs  
must be held at a logic level; they cannot be left unconnected.  
DS2 is best for ASK modulation where the transmitted waveform  
has been shaped to minimize signal bandwidth. However, DS2 is  
subject to being temporarily “blinded” by strong noise pulses, which  
can cause burst data errors. Note that DS1 is active when DS2 is  
used, as RXDATA is the logical AND of the DS1 and DS2 outputs.  
DS2 can be disabled by leaving THLD2 disconnected. A non-zero  
DS1 threshold is required for proper AGC operation.  
Receiver Event Timing  
Receiver event timing is summarized in Table 1. Please refer to this  
table for the following discussions.  
Turn-On Timing  
AGC Control  
The maximum time tPR required for the receive function to become  
operational at turn on is influenced by two factors. All receiver cir-  
cuitry will be operational 5 ms after the supply voltage reaches  
2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabi-  
lized in 3 time constants (3*tBBC). The total turn-on time to stable re-  
ceiver operation for a 10 ms power supply rise time is:  
The output of the Peak Detector also provides an AGC Reset signal  
to the AGC Control function through the AGC comparator. The pur-  
pose of the AGC function is to extend the dynamic range of the re-  
ceiver, so that the receiver can operate close to its transmitter when  
running ASK and/or high data rate modulation. The onset of satura-  
tion in the output stage of RFA1 is detected and generates the AGC  
Set signal to the AGC Control function. The AGC Control function  
then selects the 5 dB gain mode for RFA1. The AGC Comparator  
will send a reset signal when the Peak Detector output (multiplied by  
0.8) falls below the threshold voltage for DS1.  
tPR = 15 ms + 3*tBBC  
Sleep and Wake-Up Timing  
The maximum transition time from the receive mode to the  
power-down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0  
are both low (1 µs fall time).  
A capacitor at the AGCCAP pin avoids AGC “chattering” during the  
time it takes for the signal to propagate through the low-pass filter  
and charge the peak detector. The AGC capacitor also allows the  
hold-in time to be set longer than the peak detector decay time to  
avoid AGC chattering during runs of “0” bits in the received data  
stream. Note that AGC operation requires the peak detector to be  
functioning, even if DS2 is not being used. AGC operation can be  
defeated by connecting the AGCCAP pin to Vcc. The AGC can be  
latched on once engaged by connecting a 150 kilohm resistor be-  
tween the AGCCAP pin and ground in lieu of a capacitor.  
The maximum transition time tSR from the sleep mode to the receive  
mode is 3*tBBC, where tBBC is the BBOUT-CMPIN coupling-capacitor  
time constant. When the operating temperature is limited to 60 oC,  
the time required to switch from sleep to receive is dramatically less  
for short sleep times, as less charge leaks away from the BBOUT-  
CMPIN coupling capacitor.  
AGC Timing  
The maximum AGC engage time tAGC is 5 µs after the reception of a  
-30 dBm RF signal with a 1 µs envelope rise time.  
Receiver Pulse Generator and RF Amplifier Bias  
The minimum AGC hold-in time is set by the value of the capacitor  
at the AGCCAP pin. The hold-in time tAGH = CAGC/19.1, where tAGH is  
in µs and CAGC is in pF.  
The receiver amplifier-sequence operation is controlled by the Pulse  
Generator & RF Amplifier Bias module, which in turn is controlled by  
6
Peak Detector Timing  
In the low data rate mode, the PWIDTH pin sets the width of the ON  
pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the  
ON pulse width to the second RF amplifier tPW2 is set at 1.1 times  
the pulse width to the first RF amplifier in the low data rate mode).  
The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs  
with a resistor value in the range of 200 K to 390 K. The value of  
RPW is given by:  
The Peak Detector attack time constant is set by the value of the ca-  
pacitor at the PKDET pin. The attack time tPKA = CPKD/4167, where  
tPKA is in µs and CPKD is in pF. The Peak Detector decay time con-  
stant tPKD = 1000*tPKA  
.
Pulse Generator Timing  
In the low data rate mode, the interval tPRI between the falling edge  
of an ON pulse to the first RF amplifier and the rising edge of the  
next ON pulse to the first RF amplifier is set by a resistor RPR be-  
tween the PRATE pin and ground. The interval can be adjusted be-  
tween 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K.  
The value of the RPR is given by:  
R
PW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms  
However, when the PWIDTH pin is connected to Vcc through a 1 M  
resistor, the RF amplifiers operate at a nominal 50ꢀ-50ꢀ duty cy-  
cle, facilitating high data rate operation. In this case, the RF amplifi-  
ers are controlled by the PRATE resistor as described above.  
LPF Group Delay  
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms  
The low-pass filter group delay is a function of the filter 3 dB band-  
width, which is set by a resistor RLPF to ground at the LPFADJ pin.  
The minimum 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is in kHz,  
and RLPF is in kilohms.  
In the high data rate mode (selected at the PWIDTH pin) the re-  
ceiver RF amplifiers operate at a nominal 50ꢀ-50ꢀ duty cycle. In  
this case, the period tPRC from the start of an ON pulse to the first  
RF amplifier to the start of the next ON pulse to the first RF amplifier  
is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs us-  
ing a resistor of 11 K to 220 K. In this case RPR is given by:  
The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where tFGD  
is in µs, fLPF in kHz, and RLPF in kilohms.  
RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms  
7
Pin Descriptions  
Pin  
Name  
Description  
1
GND1  
VCC1  
GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.  
VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF  
capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.  
2
This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the  
AGC will hold-in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time tAGH  
the capacitor value CAGC is:  
,
C
AGC = 19.1* tAGH, where tAGH is in µs and CAGC is in pF  
A
10ꢀ ceramic capacitor should be used at this pin. The value of CAGC given above provides a hold-in time be-  
tween tAGH and 2.65* tAGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow  
the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in  
time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time  
should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by  
noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 µs.  
AGC operation can be defeated by connecting this pin to Vcc. Active or latched AGC operation is required for  
3
AGCCAP  
ASK modulation and/or for data pulses of less than 30 µs. The AGC can be latched on once engaged by connect-  
ing a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation depends on a functioning  
peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down (sleep) mode.  
This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector at-  
tack and decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be co-  
ordinated with the base-band time constant. For a given base-band capacitor CBBO, the capacitor value CPKD is:  
C
PKD = 0.33* CBBO , where CBBO and CPKD are in pF  
A
10ꢀ ceramic capacitor should be used at this pin. This time constant will vary between tPKA and 1.5* tPKA with  
variations in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays  
through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release  
function. The AGC hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as  
discussed above. Where low data rates and OOK modulation are used, the “dB-below-peak” data slicer and the  
AGC are optional. In this case, the PKDET pin and the THLD2 pin can be left unconnected, and the AGC pin can  
be connected to Vcc to reduce the number of external components needed. The peak detector capacitor is dis-  
charged in the receiver power-down (sleep) mode.  
4
PKDET  
BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for  
internal data slicer operation. The time constant tBBC for this connection is:  
t
BBC = 0.064*CBBO , where tBBC is in µs and CBBO is in pF  
A
10ꢀ ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC  
and 1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circum-  
stance will depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver De-  
signer’s Guide. A common criteria is to set the time constant for no more than a 20ꢀ voltage droop during SPMAX  
For this case:  
.
CBBO = 70*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in pF  
5
BBOUT  
The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal out-  
put impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50ꢀ-50ꢀ duty cycle, the  
BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles,  
the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a  
1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a ca-  
pacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recom-  
mended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external  
data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by  
the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin  
becomes very high, preserving the charge on the coupling capacitor.  
This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input  
impedance of this pin is 70 K to 100 K.  
6
CMPIN  
RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available  
from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin  
becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite  
logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be con-  
nected to a voltage no greater than Vcc + 200 mV.  
7
8
RXDATA  
NC  
This pin may be left unconnected or may be grounded.  
9
Pin  
Name  
Description  
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this  
pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from  
4.5 kHz to 1.8 MHz. The resistor value is determined by:  
RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz  
9
LPFADJ  
A
5ꢀ resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF  
and 1.3* fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree  
equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter  
bandwidth setting.  
10  
11  
GND2  
RREF  
GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.  
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground.  
1ꢀ resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and  
A
this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF  
through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and  
the total should not exceed 5 pF.  
THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor  
RTH2 between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak de-  
tector value (increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB  
below peak, or 60 mV for a 50ꢀ-50ꢀ RF amplifier duty cycle. The value of the THLD2 resistor is given by:  
12  
THLD2  
R
TH2 = 1.67*V, where RTH2 is in kilohms and the threshold V is in mV  
A 1ꢀ resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the  
dB-below-peak data slicer operation.  
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The thresh-  
old is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold.  
The value of the resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the accept-  
able range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:  
R
TH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV  
13  
THLD1  
For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a  
THLD1 range of 0 to 90 mV. The resistor value is given by:  
RTH1 = 2.22*V, where RTH1 is in kilohms and the threshold V is in mV  
A 1ꢀ resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required  
for proper AGC operation.  
The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON  
pulse to the first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be ad-  
justed between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by:  
R
PR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms  
5ꢀ resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF  
amplifiers operate at a nominal 50ꢀ-50ꢀ duty cycle, facilitating high data rate operation. In this case, the period  
PRC from start-to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1  
to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of RPR is given by:  
PR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms  
5ꢀ resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for  
A
14  
PRATE  
t
R
A
additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and  
this pin to less than 5 pF to maintain stability.  
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON  
pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON  
pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The  
value of RPW is given by:  
R
PW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms  
15  
PWIDTH  
A
5ꢀ resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifi-  
ers operate at a nominal 50ꢀ-50ꢀ duty cycle, facilitating high data rate operation. In this case, the RF amplifier  
ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance  
between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation  
with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the  
sleep mode.  
VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capaci-  
tor, which may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic ca-  
pacitor.  
16  
VCC2  
10  
Pin  
Name  
Description  
CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive  
mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a  
high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input  
voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV  
should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a  
maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected.  
17  
CNTRL1  
CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compat-  
ible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is  
interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic  
high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin  
must be held at a logic level; it cannot be left unconnected.  
18  
19  
20  
CNTRL0  
GND3  
RFIO  
GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.  
RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting  
an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series match-  
ing coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three  
components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to  
ground is required for ESD protection.  
S
M
-
2
0
L
P
C
B
P
a
d
L
a
y
o
u
t
.
4
6
0
0
.
3
8
2
5
.
3
5
7
5
.
3
1
7
5
.
.
2
2
7
3
7
7
5
5
.
1
9
7
5
.
1
5
7
5
.
.
1
1
1
0
7
2
5
5
.
0
7
7
5
0
.
0
0
0
D
i
m
e
n
s
i
o
n
s
i
n
i
n
c
h
e
s
Note: Specifications subject to change without notice.  
file: rx5000v.vp, 2003.07.17 rev  
11  
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