HYS64/72D64000/128x20GU-7/8-A
Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100 and PC2700)
512MB 512MB 1GB
x64 x72 x64
1bank 1bank 2bank 2bank 2bank 2bank
-7 -7 -6 -6 -7 -7
MAX MAX MAX MAX MAX MAX
1GB
x72
1GB
x64
1GB
x72
Notes
Symbol
Parameter/Condition
Unit
mA
4
1
: one bank; active / precharge; tRC = tRC MIN; tCK =
Operating Current
IDD0
tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle;
1360
1530
2200
2475
1920
2160
address and control inputs changing once every two clock cycles
: one bank; active/read/precharge; Burst = 4;
Operating Current
IDD1
1440
112
1620
126
2320
288
2610
324
2000
224
2250
252
mA
mA
1, 3
2
Refer to the following page for detailed test conditions.
: all banks idle; power-down
Precharge Power-Down Standby Current
IDD2P
mode; CKE <= VIL MAX; tCK = tCK MIN
: /CS >= VIH MIN, all banks idle;
Precharge Floating Standby Current
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
changing once per clock cycle, VIN = VREF for DQ, DQS and DM.
400
450
960
1080
800
900
IDD2F
IDD2Q
mA
2
: /CS >= VIH MIN, all banks idle;
Precharge Quiet Standby Current
CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs
stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
224
144
252
162
640
368
720
414
448
288
504
324
mA
mA
2
2
: one bank active; power-down
Active Power-Down Standby Current
IDD3P mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and
DM.
: one bank active; active / precharge;CS >= VIH
Active Standby Current
MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
IDD3N
IDD4R
IDD4W
560
630
1200
2560
2480
1350
2880
2790
1120
2160
2120
1260
2430
2385
mA
mA
mA
2
: one bank active; Burst = 2; reads; continuous burst;
Operating Current
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA
1600
1560
1800
1755
1, 3
: one bank active; Burst = 2; writes; continuous burst;
Operating Current
address and control inputs changing once per clock cycle; 50% of data
outputs changing on every clock edge; CL = 2 for DDR200, and
DDR266A, CL=3 for DDR333; tCK = tCK MIN
1
1
: tRC = tRFC MIN, distributed refresh
Auto-Refresh Current
2480
40
2790
45
3280
80
3690
90
3040
80
3420
90
IDD5
IDD6
mA
mA
: CKE <= 0.2V; external clock on; tCK = tCK MIN
Self-Refresh Current
: four bank; four bank interleaving with BL=4;
Refer to the following page for detailed test conditions.
Operating Current
IDD7
3040
3420
3840
4320
3600
4050
mA
1, 3
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
for two bank modules (n: number of components per module bank)
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
2 * n * IDDx[component]
for single bank modules (n: number of components per module bank)
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
INFINEON Technologies
12
2002-09-10 (rev.0.81)
