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HYS64V8200GDL-8

型号：

HYS64V8200GDL-8

描述：

144针SO-DIMM SDRAM模块[ 144 pin SO-DIMM SDRAM Modules ]

品牌：

INFINEON[ Infineon ]

页数：

15 页

PDF大小：

234 K

下载PDF手册
144 pin SO-DIMM SDRAM Modules  
64MB & 128 MB PC100 / PC133  
HYS64V8200GDL  
HYS64V16220GDL  
•
144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules  
for PC 100 and PC133 notebook applications  
one bank 8M x 64 and two bank 16M x 64 non-parity module organisation  
Performance:  
•
•
-7  
-7.5  
-8  
PC133  
2-2-2  
PC133  
3-3-3  
PC100  
2-2-2  
Units  
fCK  
tAC  
Clock frequency (max.)  
Clock access time  
133  
5.4  
133  
5.4  
100  
6
MHz  
ns  
•
•
Single +3.3V(± 0.3V ) power supply  
Programmable CAS Latency, Burst Length and Wrap Sequence  
(Sequential & Interleave)  
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh  
Decoupling capacitors mounted on substrate  
All inputs, outputs are LVTTL compatible  
Serial Presence Detect with E2PROM  
Uses 8M x 16 128Mbit SDRAM components  
4096 refresh cycles every 64 ms  
Gold contact pad, JEDEC MO-190 outline dimensions  
This module family is fully compliant with the latest INTEL SO-DIMM layout and electrical  
specification  
•
All PC133 modules are fully backward compatible for PC100 applications.  
INFINEON Technologies  
1
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
These INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM)  
Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as 8Mx64 (64MByte)  
and 16x64 (128MByte) high speed memory arrays designed for use in non-parity applications.  
These SO-DIMMs use SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the  
board.  
The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C  
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are  
available to the end user.  
All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6  
mm long footprint.  
Product Spectrum:  
Organisa-  
tion  
Partnumber  
Speed  
SDRAMs  
used  
Row  
Addr.  
Bank  
Select  
Column Refresh  
Addr.  
Period  
HYS64V8200GDL-7  
HYS64V8200GDL-7.5  
HYS64V8200GDL-8  
HYS64V16220GDL-7  
PC133-222  
PC133-333  
PC100-222  
PC133-222  
8M x 64  
4 8Mx16  
4k  
12  
BA0, BA1  
9
64ms  
16M x 64  
8 8Mx16  
HYS64V16220GDL-7.5 PC133-333  
HYS64V16220GDL-8 PC100-222  
Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current  
revision. Example: HYS64V16220GDL-8-C2, indicating Rev.C2 dies are used for SDRAM components.  
Card Dimensions:  
Organisation  
8M x 64  
Partnumber  
PCB-Board Layout  
INTEL Rev. 1.0/1.2  
INTEL Rev. 1.0/1.2  
L x H x T [mm]  
67.60 x 25.40 x 3.80  
67.60 x 31.75 x 3.80  
HYS64V8200GDL  
HYS64V16220GDL  
16M x 64  
Pin Names  
A0-A11  
BA0,BA1  
DQ0 - DQ63  
RAS  
Address Inputs  
DQMB0 - DQMB7  
Data Mask  
Chip Select  
Power (+3.3 Volt)  
Ground  
Bank Selects  
CS0, CS1 *)  
Vcc  
Data Input/Output  
Row Address Strobe  
Vss  
CAS  
Column Address  
Strobe  
SCL  
Clock for Presence  
Detect  
WE  
Read / Write Input  
SDA  
N.C.  
Serial Data Out for  
Presence Detect  
CKE0, CKE1 *)  
CLK0, CLK1  
Clock Enable  
Clock Input  
No Connection  
*) CS1 and CKE1 on two bank modules only  
INFINEON Technologies  
2
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Pin Configuration  
Front  
Side  
Back  
Side  
Front  
Side  
Back  
Side  
PIN #  
PIN #  
PIN #  
PIN #  
1
VSS  
2
VSS  
73  
NC  
Vss  
NC  
NC  
Vcc  
74  
CLK1  
3
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
Vss  
4
DQ32  
DQ33  
DQ34  
DQ35  
Vcc  
75  
76  
Vss  
5
6
77  
78  
NC  
7
8
79  
80  
NC  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
81  
82  
Vcc  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
83  
DQ16  
DQ17  
DQ18  
DQ19  
Vss  
84  
DQ48  
DQ49  
DQ50  
DQ51  
Vss  
DQ36  
DQ37  
DQ38  
DQ39  
Vss  
85  
86  
87  
88  
89  
90  
91  
92  
93  
DQ20  
DQ21  
DQ22  
DQ23  
Vcc  
94  
DQ52  
DQ53  
DQ54  
DQ55  
Vcc  
DQMB0  
DQMB1  
Vcc  
DQMB4  
DQMB5  
Vcc  
95  
96  
97  
98  
99  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
A0  
A3  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
A1  
A4  
A6  
A7  
A2  
A5  
A8  
BA0  
Vss  
Vss  
Vss  
Vss  
DQ8  
DQ9  
DQ10  
DQ11  
Vcc  
DQ40  
DQ41  
DQ42  
DQ43  
Vcc  
A9  
BA1  
A10  
A11  
Vcc  
Vcc  
DQMB2  
DQMB3  
Vss  
DQMB6  
DQMB7  
Vss  
DQ12  
DQ13  
DQ14  
DQ15  
Vss  
DQ44  
DQ45  
DQ46  
DQ47  
Vss  
DQ24  
DQ25  
DQ26  
DQ27  
Vcc  
DQ56  
DQ57  
DQ58  
DQ59  
Vcc  
NC  
NC  
NC  
NC  
DQ28  
DQ29  
DQ30  
DQ31  
Vss  
DQ60  
DQ61  
DQ62  
DQ63  
Vss  
CLK0  
Vcc  
CKE0  
Vcc  
RAS  
WE  
CAS  
CKE1  
N.C.(A12)  
N.C.(A13)  
CS0  
CS1  
SDA  
SCL  
Vcc  
Vcc  
INFINEON Technologies  
3
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
WE  
CS0  
CS WE  
LDQM  
CS WE  
LDQM  
DQMB0  
DQMB4  
DQ0-DQ7  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
DQMB1  
DQMB5  
UDQM  
UDQM  
DQ8-DQ15  
DQ40-DQ47  
DQ8-DQ15  
DQ8-DQ15  
D0  
D2  
CS WE  
LDQM  
CS WE  
LDQM  
DQMB2  
DQMB6  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQMB7  
UDQM  
UDQM  
DQ24-DQ31  
DQ56-DQ63  
DQ8-DQ15  
DQ8-DQ15  
D1  
D3  
A0-A11, BA0, BA1  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
4 SDRAM  
E2PROM  
(256 word x 8 Bit)  
VCC  
C1-C4  
SA0  
SCL  
SA1  
SDA  
SA2  
VSS  
RAS  
CAS  
CKE0  
CLK0  
CLK1  
Note: All resistors are 10 Ω  
10 pF  
SPB04133  
Block Diagram for one bank 8M x 64 SDRAM DIMM - Module  
INFINEON Technologies  
4
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
WE  
CS0  
CS1  
CS  
WE  
CS  
WE  
CS  
WE  
CS  
WE  
DQMB0  
DQMB4  
LDQM  
LDQM  
LDQM  
LDQM  
DQ0-DQ7  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQMB1  
DQMB5  
UDQM  
UDQM  
UDQM  
UDQM  
DQ8-DQ15  
DQ40-DQ47  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
D0  
D4  
D2  
D6  
CS  
WE  
CS  
WE  
CS  
WE  
CS  
WE  
DQMB2  
DQMB6  
LDQM  
LDQM  
LDQM  
LDQM  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQMB7  
UDQM  
UDQM  
UDQM  
UDQM  
DQ24-DQ31  
DQ56-DQ63  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
D3  
DQ8-DQ15  
D1  
D5  
D7  
A0-A11, BA0, BA1  
D0-D7  
D0-D7  
D0-D7  
D0-D7  
D0-D7  
E2PROM  
(256 word x 8 Bit)  
VCC  
C
SA0  
SCL  
SA1  
SDA  
SA2  
VSS  
RAS  
CAS  
Ω
Note: All resistors are 10  
CKE0  
CKE1  
D0-D3  
D4-D7  
CLK0  
CLK1  
4 SDRAM  
4 SDRAM  
Block Diagram for two bank 16M x 64 SDRAM DIMM - Module  
INFINEON Technologies  
5
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
– 1.0  
– 1.0  
-55  
–
max.  
4.6  
Input / Output voltage relative to VSS  
Power supply voltage on VDD  
VIN, VOUT  
VDD  
TSTG  
PD  
V
4.6  
+150  
1
V
Storage temperature range  
oC  
W
mA  
Power dissipation (per SDRAM component)  
Data out current (short circuit)  
IOS  
–
50  
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
2.0  
max.  
Input high voltage  
VIH  
VIL  
Vcc+0.3  
V
Input low voltage  
– 0.5  
2.4  
0.8  
–
V
Output high voltage (IOUT = – 4.0 mA)  
Output low voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
–
0.4  
20  
V
Input leakage current, any input  
– 20  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output leakage current  
IO(L)  
– 20  
20  
µA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
8M x 64  
16M x 64  
max.  
max.  
28  
25  
35  
25  
10  
12  
8
Input capacitance (A0 to A11, BA0, BA1)  
Input capacitance (RAS, CAS, WE, CKE0)  
Input Capacitance (CLK0, CLK1)  
Input capacitance (CS0)  
CI1  
CI2  
CI3  
CI4  
CI5  
CIO  
Csc  
Csd  
52  
46  
35  
30  
15  
18  
8
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input capacitance (DQMB0-DQMB7)  
Input / Output capacitance (DQ0-DQ63)  
Input Capacitance (SCL,SA0-2)  
Input/Output Capacitance  
0
10  
INFINEON Technologies  
6
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Operating Currents per memory bank  
(TA = 0 to 70oC, VDD = 3.3V ± 0.3V)  
(Recommended Operating Conditions unless otherwise noted)  
Symb.  
Note  
Parameter & Test Condition  
-7/-7.5  
-8  
OPERATING CURRENT  
trc=trcmin., tck=tckmin.  
ICC1  
600  
6
560  
6
mA  
mA  
mA  
1
1
Ouputs open, Burst Length = 4, CL=3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
PRECHARGE STANDBY CURRENT in tck = min.  
Power Down Mode  
ICC2P  
mA  
tck = Infinity  
ICC2PS  
ICC2N  
4
4
mA  
mA  
1
1
CS =VIH (min.), CKE<=Vil(max)  
PRECHARGE STANDBY CURRENT in tck = min.  
160  
140  
Non-Power Down Mode  
tck = Infinity  
ICC2NS  
ICC3N  
ICC3P  
20  
200  
40  
20  
180  
40  
mA  
mA  
mA  
1
1
1
CS = VIH (min.), CKE>=Vih(min)  
NO OPERATING CURRENT  
CKE>=VIH(min.)  
CKE<=VIL(max.)  
tck = min., CS = VIH(min),  
active state ( max. 4 banks)  
BURST OPERATING CURRENT  
tck = min.,  
Read command cycling  
ICC4  
600  
560  
mA 1,2  
AUTO REFRESH CURRENT  
tck = min.,  
Auto Refresh command cycling  
1
mA  
mA  
ICC5  
ICC6  
720  
3.2  
680  
3.2  
SELF REFRESH CURRENT  
Self Refresh Mode, CKE=0.2V  
1
Notes:  
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for-7/ -7.5 and  
100 MHz for -8 modules. Input signals are changed once during tck, excepts for ICC6 and for standby  
currents when tck=infinity.  
2. These parameters are measured with continuous data stream during read access and all DQ toggling.  
CL=3 and BL=4 is assumed and the data-out current is excluded.  
INFINEON Technologies  
7
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
AC Characteristics 1)2)  
TA = 0 to 70 °C; VSS = 0 V; V  
= 3.3 V ± 0.3 V, tT = 1 ns  
DD  
Symbol  
Unit  
Parameter  
Limit Values  
-7.5  
-7  
-8  
PC133-222 PC133-333 PC100-222  
min. max. min. max. min. max.  
Clock and Access Time  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
7.5  
7.5  
–
–
7.5  
10  
–
–
10  
10  
–
–
ns  
ns  
tCK  
tCK  
tAC  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
–
133  
133  
–
–
133  
100  
–
–
100 MHz  
100 MHz  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
2,  
3
–
–
5.4  
5.4  
–
–
5.4  
6
–
–
6
6
ns  
ns  
Clock High Pulse Width  
tCH  
tCL  
tT  
2.5  
2.5  
0.3  
–
–
2.5  
2.5  
0.3  
–
–
3
3
–
–
2
ns  
ns  
ns  
Clock Low Pulse Width  
Transition time  
1.2  
1.2  
0.5  
Setup and Hold Parameters  
Input Setup Time  
4
4
4
4
tIS  
1.5  
0.8  
–
–
–
1
–
–
1.5  
0.8  
–
–
–
1
–
–
2
1
–
1
2
–
–
1
–
–
ns  
Input Hold Time  
tIH  
tSB  
ns  
Power Down Mode Entry time  
CLK  
CLK  
CLK  
Power Down Mode Exit Setup Time tPDE  
1
1
Mode Register Set-up time  
tRSC  
2
2
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
5
5
5
5
5
tRCD  
tRP  
tRAS  
tRC  
15  
15  
42  
60  
14  
–
–
20  
20  
45  
67  
15  
–
–
20  
20  
50  
70  
16  
–
–
ns  
ns  
ns  
ns  
ns  
100k  
–
100k  
–
100k  
–
Row Cycle Time  
Activate(a) to Activate(b) Command tRRD  
–
–
–
period  
CAS(a) to CAS(b) Command period tCCD  
1
8
–
1
–
1
–
CLK  
INFINEON Technologies  
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Symbol  
Unit  
Parameter  
Limit Values  
-7.5  
-7  
-8  
PC133-222 PC133-333 PC100-222  
min. max. min. max. min. max.  
Refresh Cycle  
Refresh Period  
(4096 cycles)  
tREF  
–
64  
–
64  
–
64 ms  
6
7
Self Refresh Exit Time  
tSREX  
1
–
1
–
1
–
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
7
2
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns  
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
ns  
tHZ  
tDQZ  
ns  
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
2
0
–
–
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
9
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Notes:  
1. All AC characteristics shown are for SDRAM components.  
An initial pause of 100µs is required after power-up, then a Precharge All Banks command must  
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can  
begin.  
2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns  
with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50  
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between  
0.8V and 2.0 V  
..  
tCH  
2.4 V  
0.4 V  
1.4 V  
CLOCK  
tT  
tCL  
tIH  
tIS  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
OUTPUT  
1.4 V  
50 pF  
tHZ  
Measurement conditions for  
tac and toh  
IO.vsd  
3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter.  
4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter.  
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh  
commands must be given to “wake-up“ the device.  
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
once the Self Refresh Exit command is registered.  
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage  
levels.  
INFINEON Technologies  
10  
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Serial Presence Detects  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information  
about the module configuration, speed, etc. is written into the E2PROM device during module  
production using a serial presence detect protocol ( I2C synchronous 2-wire bus)  
SPD-Table:  
Byte#  
Description  
SPD Entry Value  
HEX  
8M x 64  
-7.5  
16M x 64  
-7.5  
-7  
-8  
-7  
-8  
0
1
Number of SPD bytes  
128  
256  
80  
08  
04  
0C  
09  
Total bytes in Serial PD  
Memory Type  
2
SDRAM  
12  
3
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
4
9
5
1 / 2  
01  
02  
6
64  
40  
00  
01  
7
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
SDRAM Access time from Clock at CL=3  
Dimm Config (Error Det/Corr.)  
Refresh Rate/Type  
0
8
LVTTL  
7.5 / 10.0 ns  
5.4 / 6.0 ns  
none  
9
75  
54  
75  
54  
A0  
60  
75  
54  
75  
54  
A0  
60  
10  
11  
12  
00  
80  
Self-Refresh,  
15.6µs  
13  
14  
15  
SDRAM width, Primary  
10  
00  
01  
Error Checking SDRAM data width  
n/a  
Minimum clock delay for back-to-back  
random column address  
tccd = 1 CLK  
16  
17  
18  
19  
20  
21  
Burst Length supported  
Number of SDRAM banks  
Supported CAS Latencies  
CS Latencies  
1, 2, 4 & 8  
2
0F  
04  
06  
01  
01  
00  
2, & 3  
CS latency = 0  
Write latency = 0  
WE Latencies  
SDRAM DIMM module attributes  
non buffered/non  
reg.  
22  
23  
24  
SDRAM Device Attributes :General  
SDRAM Cycle Time at CL = 2  
Vcc tol +/- 10%  
7.5 / 10.0 ns  
5.4 / 6.0 ns  
0E  
75  
54  
A0  
60  
A0  
60  
75  
54  
A0  
60  
A0  
60  
SDRAM Access Time from Clock at  
CL=2  
25  
26  
SDRAM Cycle Time at CL = 1  
not supported  
not supported  
00  
00  
FF  
FF  
FF  
FF  
00  
00  
FF  
FF  
FF  
FF  
SDRAM Access Time from Clock at  
CL=1  
27  
Minimum Row Precharge Time  
15/ 20 ns  
0F  
14  
14  
0F  
14  
14  
INFINEON Technologies  
11  
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
SPD-Table (cont’d):  
Byte#  
Description  
SPD Entry Value  
Hex  
8Mx64  
-7.5  
16Mx64  
-7.5  
-7  
-8  
-7  
-8  
28  
Minimum Row Active to Row Active  
delay  
14 / 15 / 16 ns  
0E  
0F  
10  
0E  
0F  
10  
29  
30  
31  
32  
33  
34  
35  
Minimum RAS to CAS delay  
Minimum Ras pulse width  
Module Bank Density (per bank)  
SDRAM input setup time  
15 / 20 ns  
42 / 45 ns  
64MB  
0F  
2A  
14  
14  
0F  
2A  
14  
14  
2D  
2D  
2D  
2D  
10  
1.5 / 2 ns  
0.8 / 1 ns  
1.5 / 2 ns  
0.8 / 1 ns  
15  
08  
15  
08  
15  
08  
15  
08  
20  
10  
20  
10  
15  
08  
15  
08  
15  
08  
15  
08  
20  
10  
20  
10  
SDRAM input hold time  
SDRAM data input setup time  
SDRAM data input hold time  
36-61 Superset information  
FF  
12  
62  
63  
SPD Revision  
Revision 1.2  
Checksum for bytes 0 - 62  
E1  
0A  
87  
68  
E2  
0B  
C7  
69  
64- Manufactures’s information (optional)  
125  
126 Frequency Specification  
127 Details  
PC100  
64  
128+ Unused storage locations  
FF  
INFINEON Technologies  
12  
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Package Outlines  
64 MByte SO-DIMM Module package (JEDEC MO-190)  
HYS64V8200GDL  
(144 pin, dual read-out, single in-line memory module)  
67,6±  
0.15  
3.8 max.  
63,6  
1
59  
61  
62  
143  
144  
1±  
0.1  
3.3  
23.2  
32.8  
2.6  
4.6  
1.5  
60  
1.8  
3.7  
2
4
Detail of Contacts  
Detail of Chamfer  
0.6  
0.2 -0.15  
0.8  
L-DIM-144-10  
Note: All tol eran ces accord ing to JEDEC stan dard  
INFINEON Technologies  
13  
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
128 MByte SO-DIMM Module package  
HYS64V16220GDL  
(144 pin, dual read-out, single in-line memory module)  
67.6 ±  
0.15  
3.8 max.  
63.6  
1
59  
61  
143  
144  
±
0.1  
3.3  
1
23.2  
24.5  
32.8  
2.5  
4.6  
1.5  
60  
1.8  
3.7  
2
62  
4
Detail of Contacts  
Detail of Chamfer  
0.6  
0.2 -0.15  
0.8  
L-DIM-144-9  
Note: All tolerances according to JEDEC standard  
INFINEON Technologies  
14  
9.01  
HYS64V8200GDL/HYS64V16220GDL  
144 pin SO-DIMM SDRAM Modules  
Update Information:  
5.6.99  
29.9.99  
First and preliminary edition  
Checksum added  
3.12.99  
PC133 timing changed according to INTELs PC133 specification  
HYS64V8200GDL-7.5/-8 added  
17.1.2000  
10.5.2000  
HYS64V162221GDL-7.5/-8 version with reduced height of  
1060 mil = 29,92 mm (L-DIM-144-11) added  
19.7.2000  
8.8.2000  
CKE1 in two bank block diagram added  
128Mbyte version HYS64V16221GDL removed (no plans for production)  
8Mx64 module height on page 2 corrected  
25.9.2000  
7.03.2001  
5.09.2001  
-7 speed sort added  
SCR: Table for Absolute Maximum Ratings added  
INFINEON Technologies  
15  
9.01  
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