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HYS64V32220GDL-75

型号:

HYS64V32220GDL-75

描述:

144针SO-DIMM SDRAM模块[ 144 pin SO-DIMM SDRAM Modules ]

品牌:

INFINEON[ Infineon ]

页数:

16 页

PDF大小:

248 K

144 pin SO-DIMM SDRAM Modules  
128MB & 256 MB PC100 / PC133  
HYS64V16200GDL  
HYS64V32220GDL  
144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules  
for PC100 and PC133 notebook applications  
One bank 16M x 64 (128MByte) and two banks 32M x 64 (256 MByte)  
non-parity module organisation  
Performance:  
-7  
-7.5  
-8  
PC133  
2-2-2  
PC133  
3-3-3  
PC100  
2-2-2  
Units  
fCK  
tAC  
Clock frequency (max.)  
Clock access time  
133  
5.4  
133  
5.4  
100  
6
MHz  
ns  
Single +3.3V(± 0.3V ) power supply  
Programmable CAS Latency, Burst Length and Wrap Sequence  
(Sequential & Interleave)  
Auto Refresh (CBR) and Self Refresh  
Decoupling capacitors mounted on substrate  
All inputs, outputs are LVTTL compatible  
Serial Presence Detect with E2PROM  
256Mbit SDRAM low power components in TSOP54 packages with 16M x 16 organisation  
8192 refresh cycles every 64 ms  
Gold contact pad, JEDEC MO-190 outline dimensions  
This module family is fully compliant with the latest INTEL SO-DIMM layout and electrical  
specifications  
All PC133 modules are fully backward compatible to PC100-222 operation  
Importante Notice:  
These SO-DIMM modules are based on 256Mbit SDRAM technology and can be  
used in applications only, where 256Mbit addressing is supported.  
INFINEON Technologies  
1
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
This INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small  
Outline Dual In-line Memory Modules (SO-DIMM) which are organised as x64 high speed memory  
arrays designed for use in non-parity applications. These SO-DIMMs use 256Mbit SDRAMs in  
TSOPII packages. Decoupling capacitors are mounted on the board.  
The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C  
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are  
available to the end user.  
All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6  
mm long footprint.  
Product Spectrum:  
Speed  
SDRAMs RowAddr.  
used  
Bank  
Select  
Column Refresh  
Addr.  
Period  
HYS64V16200GDL-7  
HYS64V16200GDL-7.5  
HYS64V16200GDL-8  
HYS64V32220GDL-7  
HYS64V32220GDL-7.5  
HYS64V32220GDL-8  
PC133-222  
PC133-333  
PC100-222  
PC133-222  
PC133-333  
PC100-222  
16M x 64  
4 16Mx16  
8k  
13  
BA0, BA1  
9
7,8 µs  
8 16Mx16  
32M x 64  
Note: All partnumbers end with a place code, designating the die revision. Example: HYS64V32220GDL-8-C2,  
indicating Rev.C2 dies are used for SDRAM components.  
Card Dimensions:  
Organisation  
16M x 64  
PCB-Board  
L x H x T [mm]  
67.60 x 25.40 x 3.80  
67.60 x 31.75 x 3.80  
INTEL Rev. 1.0/1.2  
32M x 64  
Pin Names  
A0-A12  
Address Inputs  
DQMB0 -DQMB7  
Data Mask  
BA0,BA1  
DQ0 - DQ63  
RAS  
Bank Selects  
CS0, CS1 *)  
Vcc  
Chip Select  
Data Input/Output  
Row Address Strobe  
Column Address Strobe  
Read / Write Input  
Clock Enable  
Power (+3.3 Volt)  
Ground  
Vss  
CAS  
SCL  
Clock for Presence Detect  
Serial Data Out for Presence Detect  
No Connection  
WE  
SDA  
CKE0, CKE1  
CLK0, CLK1 *)  
N.C.  
Clock Input  
*) CS1 and CKE1 on two bank modules only  
INFINEON Technologies  
2
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
Pin Configuration  
Front  
Back  
Side  
Front  
Side  
Back  
Side  
PIN #  
PIN #  
PIN #  
PIN #  
Side  
1
VSS  
2
VSS  
73  
NC  
Vss  
NC  
NC  
Vcc  
74  
CLK1  
3
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
Vss  
4
DQ32  
DQ33  
DQ34  
DQ35  
Vcc  
75  
76  
Vss  
5
6
77  
78  
NC  
7
8
79  
80  
NC  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
81  
82  
Vcc  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
83  
DQ16  
DQ17  
DQ18  
DQ19  
Vss  
84  
DQ48  
DQ49  
DQ50  
DQ51  
Vss  
DQ36  
DQ37  
DQ38  
DQ39  
Vss  
85  
86  
87  
88  
89  
90  
91  
92  
93  
DQ20  
DQ21  
DQ22  
DQ23  
Vcc  
94  
DQ52  
DQ53  
DQ54  
DQ55  
Vcc  
DQMB0  
DQMB1  
Vcc  
DQMB4  
DQMB5  
Vcc  
95  
96  
97  
98  
99  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
A0  
A3  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
A1  
A4  
A6  
A7  
A2  
A5  
A8  
BA0  
Vss  
Vss  
Vss  
Vss  
DQ8  
DQ9  
DQ10  
DQ11  
Vcc  
DQ40  
DQ41  
DQ42  
DQ43  
Vcc  
A9  
BA1  
A10  
A11  
Vcc  
Vcc  
DQMB2  
DQMB3  
Vss  
DQMB6  
DQMB7  
Vss  
DQ12  
DQ13  
DQ14  
DQ15  
Vss  
DQ44  
DQ45  
DQ46  
DQ47  
Vss  
DQ24  
DQ25  
DQ26  
DQ27  
Vcc  
DQ56  
DQ57  
DQ58  
DQ59  
Vcc  
NC  
NC  
NC  
NC  
DQ28  
DQ29  
DQ30  
DQ31  
Vss  
DQ60  
DQ61  
DQ62  
DQ63  
Vss  
CLK0  
Vcc  
CKE0  
Vcc  
RAS  
WE  
CAS  
CKE1  
A12  
CS0  
CS1  
SDA  
SCL  
N.C  
Vcc  
Vcc  
INFINEON Technologies  
3
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
WE  
CS0  
CS  
WE  
CS  
WE  
DQMB0  
DQMB4  
LDQM  
LDQM  
DQ0-DQ7  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
DQMB1  
DQMB5  
UDQM  
UDQM  
DQ8-DQ15  
DQ40-DQ47  
DQ8-DQ15  
DQ8-DQ15  
D0  
D2  
CS  
WE  
CS  
WE  
DQMB2  
DQMB6  
LDQM  
LDQM  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQMB7  
UDQM  
UDQM  
DQ24-DQ31  
DQ56-DQ63  
DQ8-DQ15  
D1  
DQ8-DQ15  
D3  
A0-A12, BA0, BA1  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
4 SDRAM  
E2PROM  
(256 word x 8 Bit)  
VCC  
VSS  
C1  
C
4
-
SA0  
SCL  
SA1  
SDA  
SA2  
RAS  
CAS  
CKE0  
CLK0  
CLK1  
Note: All resistors are 10  
10 pF  
SPB04133_256Mb  
Block Diagram for one bank 16M x 64 (128MByte) SDRAM SO- DIMM - Module  
INFINEON Technologies  
4
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
WE  
CS0  
CS1  
CS  
WE  
CS  
WE  
CS  
WE  
CS  
WE  
DQMB0  
DQMB4  
LDQM  
LDQM  
LDQM  
LDQM  
DQ0-DQ7  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQMB1  
DQMB5  
UDQM  
UDQM  
UDQM  
UDQM  
DQ8-DQ15  
DQ40-DQ47  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
D0  
D4  
D2  
D6  
CS  
WE  
CS  
WE  
CS  
WE  
CS  
WE  
DQMB2  
DQMB6  
LDQM  
LDQM  
LDQM  
LDQM  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQMB7  
UDQM  
UDQM  
UDQM  
UDQM  
DQ24-DQ31  
DQ56-DQ63  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
D3  
DQ8-DQ15  
D1  
D5  
D7  
A0-A12, BA0, BA1  
D0-D7  
D0-D7  
D0-D7  
D0-D7  
D0-D7  
E2PROM  
(256 word x 8 Bit)  
VCC  
VSS  
C
SA0  
SCL  
SA1  
SDA  
SA2  
RAS  
CAS  
CKE0  
CKE1  
CLK0  
D0-D3  
D4-D7  
D0-D3  
D4-D7  
CLK1  
Note: All resistors are 10  
SPB04134_256M  
Block Diagram for two bank 32M x 64 (256MByte) SDRAM SO- DIMM - Module  
INFINEON Technologies  
5
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
– 1.0  
– 1.0  
-55  
max.  
4.6  
Input / Output voltage relative to VSS  
Power supply voltage on VDD  
VIN, VOUT  
VDD  
TSTG  
PD  
V
4.6  
+150  
1
V
Storage temperature range  
oC  
W
mA  
Power dissipation (per SDRAM component)  
Data out current (short circuit)  
IOS  
50  
Permanent device damage may occur if Absolute Maximum Ratingsare exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
Unit  
min.  
2.0  
max.  
Input high voltage  
VIH  
VIL  
Vcc+0.3  
V
Input low voltage  
0.5  
2.4  
0.8  
V
Output high voltage (IOUT = 4.0 mA)  
Output low voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
0.4  
20  
V
Input leakage current, any input  
20  
mA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output leakage current  
IO(L)  
20  
20  
mA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 oC; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
16M x 64  
max.  
32M x 64  
max.  
Input capacitance (A0 to A11, BA0, BA1)  
Input capacitance (RAS, CAS, WE, CKE0)  
Input Capacitance (CLK0, CLK1)  
Input capacitance (CS0)  
CI1  
CI2  
CI3  
CI4  
CI5  
CIO  
Csc  
Csd  
28  
25  
35  
25  
10  
12  
8
52  
46  
35  
30  
15  
18  
8
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input capacitance (DQMB0-DQMB7)  
Input / Output capacitance (DQ0-DQ63)  
Input Capacitance (SCL,SA0-2)  
Input/Output Capacitance  
10  
10  
INFINEON Technologies  
6
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
Operating Currents per memory bank  
(TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V ± 0.3 V)  
(Recommended Operating Conditions unless otherwise noted)  
Symb.  
Note  
Parameter & Test Condition  
-7/-7.5  
-8  
OPERATING CURRENT  
trc=trcmin.,  
All banks operated in random access,  
all banks operated in ping-pong manner  
ICC1  
920  
680 mA 1, 2  
PRECHARGE STANDBY CURRENT in tck = min.  
Power Down Mode  
CS =VIH (min.), CKE<=Vil(max)  
ICC2P  
8
mA  
1
1
PRECHARGE STANDBY CURRENT in tck = min.  
Non-Power Down Mode  
CS = VIH (min.), CKE>=Vih(min)  
ICC2N  
160  
200  
120 mA  
NO OPERATING CURRENT  
CKE>=VIH(min.)  
CKE<=VIL(max.)  
ICC3N  
ICC3P  
ICC4  
180 mA  
mA  
1
1
tck = min., CS = VIH(min),  
active state ( max. 4 banks)  
40  
BURST OPERATING CURRENT  
tck = min.,  
Read command cycling  
600  
960  
400  
mA 1,2  
AUTO REFRESH CURRENT  
tck = min.,  
Auto Refresh command cycling  
ICC5  
ICC6  
1
880 mA  
mA  
SELF REFRESH CURRENT  
Self Refresh Mode, CKE=0.2V,  
tck = infinity.  
7.2  
1
Notes:  
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 & -7.5  
and at 100 MHz for -8 modules. Input signals are changed once during tck.  
2. These parameters are measured with continuous data stream during read access and all DQ toggling.  
CL=3 and BL=4 is assumed and the data-out current is excluded.  
INFINEON Technologies  
7
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
AC Characteristics 1)2)  
(TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns)  
Symbol  
Unit  
Parameter  
Limit Values  
-7.5  
-7  
-8  
PC133-222 PC133-333 PC100-222  
min. max. min. max. min. max.  
Clock and Access Time  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
7.5  
7.5  
7.5  
10  
10  
10  
ns  
ns  
tCK  
tCK  
tAC  
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
133  
133  
133  
100  
100 MHz  
100 MHz  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
2,  
3
5.4  
5.4  
5.4  
6
6
6
ns  
ns  
Clock High Pulse Width  
tCH  
tCL  
tT  
2.5  
2.5  
0.3  
2.5  
2.5  
0.3  
3
3
2
ns  
ns  
ns  
Clock Low Pulse Width  
Transition time  
1.2  
1.2  
0.5  
Setup and Hold Paramters  
Input Setup Time  
4
4
4
4
tIS  
1.5  
0.8  
1
1.5  
0.8  
1
2
1
1
2
1
ns  
Input Hold Time  
tIH  
tSB  
ns  
Power Down Mode Entry time  
CLK  
CLK  
CLK  
Power Down Mode Exit Setup Time tPDE  
1
1
Mode Register Set-up time  
tRSC  
2
2
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
5
5
5
5
5
tRCD  
tRP  
tRAS  
tRC  
15  
15  
42  
60  
14  
20  
20  
45  
67  
15  
20  
20  
50  
70  
16  
ns  
ns  
ns  
ns  
ns  
100k  
100k  
100k  
Row Cycle Time  
Activate(a) to Activate(b) Command tRRD  
period  
CAS(a) to CAS(b) Command period tCCD  
1
8
1
1
CLK  
INFINEON Technologies  
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
Symbol  
Unit  
Parameter  
Limit Values  
-7.5  
-7  
-8  
PC133-222 PC133-333 PC100-222  
min. max. min. max. min. max.  
Refresh Cycle  
Refresh Period  
(4096 cycles)  
tREF  
64  
64  
64 ms  
6
7
Self Refresh Exit Time  
tSREX  
1
1
1
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
7
2
3
0
3
7
2
3
0
3
8
2
ns  
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
ns  
tHZ  
tDQZ  
ns  
CLK  
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
2
0
2
0
CLK  
CLK  
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
9
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
Notes:  
1. All AC characteristics shown are for SDRAM components.  
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must  
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can  
begin.  
2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns  
with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50  
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between  
0.8V and 2.0 V.  
.
tCH  
2.4 V  
0.4 V  
1.4 V  
CLOCK  
tT  
tCL  
tIH  
tIS  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
OUTPUT  
1.4 V  
50 pF  
tHZ  
Measurement conditions for  
tac and toh  
IO.vsd  
3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter.  
4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter.  
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh  
commands must be given to wake-upthe device.  
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
once the Self Refresh Exit command is registered.  
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage  
levels.  
Serial Presence Detects:  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information  
about the module configuration, speed, etc. is written into the E2PROM device during module  
production using a serial presence detect protocol ( I2C synchronous 2-wire bus)  
INFINEON Technologies  
10  
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
SPD-Table HYS64V16200GDL:  
Byte#  
Description  
SPD Entry Value  
Hex  
16Mx64 16Mx64 16Mx64  
-7  
-7.5  
80  
08  
04  
0D  
09  
01  
40  
00  
01  
75  
-8  
0
1
2
3
4
5
6
7
8
9
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
SDRAM  
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
13  
9
1
64  
0
Module Data Width (contd)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
LVTTL  
7.5 / 10.0 ns  
75  
54  
A0  
60  
10  
SDRAM Access time from Clock at CL=3  
5.4 / 6.0 ns  
54  
11  
12  
13  
14  
15  
Dimm Config (Error Det/Corr.)  
Refresh Rate/Type  
none  
Self-Refresh, 7.8 µs  
x16  
00  
82  
10  
00  
01  
SDRAM width, Primary  
Error Checking SDRAM data width  
n/a  
Minimum clock delay for back-to-back random  
column address  
tccd = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Burst Length supported  
1, 2, 4 & 8  
2
0F  
04  
06  
01  
01  
00  
0E  
Number of SDRAM banks  
Supported CAS Latencies  
2, & 3  
CS Latencies  
CS latency = 0  
Write latency = 0  
unbuffered  
Vcc tol +/- 10%  
7.5 / 10 ns  
5.4 / 6.0 ns  
not supported  
not supported  
20 ns  
WE Latencies  
SDRAM DIMM module attributes  
SDRAM Device Attributes :General  
SDRAM Cycle Time at CL = 2  
SDRAM Access Time from Clock at CL=2  
SDRAM Cycle Time at CL = 1  
SDRAM Access Time from Clock at CL=1  
Minimum Row Precharge Time  
Minimum Row Active to Row Active delay  
Minimum RAS to CAS delay  
Minimum Ras pulse width  
75  
54  
00  
00  
0F  
0E  
0F  
2A  
A0  
60  
FF  
FF  
14  
15 / 16 ns  
20 ns  
0F  
10  
32  
14  
42 / 45 / 60 ns  
128MB  
2D  
20  
15  
08  
15  
08  
Module Bank Density (per bank)  
SDRAM input setup time  
1.5 / 2 ns  
15  
08  
15  
08  
00  
20  
10  
20  
10  
SDRAM input hold time  
0.8 / 1 ns  
SDRAM data input setup time  
SDRAM data input hold time  
1.5 / 2 ns  
0.8 / 1 ns  
36-61 Superset information  
FF  
62  
63  
SPD Revision  
Revision 1.2  
12  
39  
Checksum for bytes 0 - 62  
F4  
9C  
64-125 Manufacturess information  
126  
127  
Frequency Specification  
Details  
64  
87  
FF  
128+ Unused storage locations  
INFINEON Technologies  
11  
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
SPD-Table HYS64V32220GDL:  
Byte#  
Description  
SPD Entry Value  
Hex  
32Mx64 32Mx64 32Mx64  
-7  
-7.5  
80  
08  
04  
0D  
09  
02  
40  
00  
01  
75  
-8  
0
1
2
3
4
5
6
7
8
9
Number of SPD bytes  
Total bytes in Serial PD  
Memory Type  
128  
256  
SDRAM  
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
13  
9
2
64  
0
Module Data Width (contd)  
Module Interface Levels  
SDRAM Cycle Time at CL=3  
LVTTL  
7.5 / 10.0 ns  
75  
54  
A0  
60  
10  
SDRAM Access time from Clock at CL=3  
5.4 / 6.0 ns  
54  
11  
12  
13  
14  
15  
Dimm Config (Error Det/Corr.)  
Refresh Rate/Type  
none  
Self-Refresh, 7.8 µs  
x16  
00  
82  
10  
00  
01  
SDRAM width, Primary  
Error Checking SDRAM data width  
n/a  
Minimum clock delay for back-to-back random  
column address  
tccd = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Burst Length supported  
1, 2, 4 & 8  
2
0F  
04  
06  
01  
01  
00  
0E  
Number of SDRAM banks  
Supported CAS Latencies  
2, & 3  
CS Latencies  
CS latency = 0  
Write latency = 0  
unbuffered  
Vcc tol +/- 10%  
7.5 / 10 ns  
5.4 / 6.0 ns  
not supported  
not supported  
20 ns  
WE Latencies  
SDRAM DIMM module attributes  
SDRAM Device Attributes :General  
SDRAM Cycle Time at CL = 2  
SDRAM Access Time from Clock at CL=2  
SDRAM Cycle Time at CL = 1  
SDRAM Access Time from Clock at CL=1  
Minimum Row Precharge Time  
Minimum Row Active to Row Active delay  
Minimum RAS to CAS delay  
Minimum Ras pulse width  
75  
54  
00  
00  
0F  
0E  
0F  
2A  
A0  
60  
FF  
FF  
14  
15 / 16 ns  
20 ns  
0F  
10  
32  
14  
42 / 45 / 60 ns  
128MB  
2D  
20  
15  
08  
15  
08  
Module Bank Density (per bank)  
SDRAM input setup time  
1.5 / 2 ns  
15  
08  
15  
08  
00  
20  
10  
20  
10  
SDRAM input hold time  
0.8 / 1 ns  
SDRAM data input setup time  
SDRAM data input hold time  
1.5 / 2 ns  
0.8 / 1 ns  
36-61 Superset information  
FF  
62  
63  
SPD Revision  
Revision 1.2  
12  
1E  
Checksum for bytes 0 - 62  
F5  
81  
64-125 Manufacturess information  
126  
127  
Frequency Specification  
Details  
64  
C7  
FF  
128+ Unused storage locations  
INFINEON Technologies  
12  
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
Package Outlines  
128 MByte SO-DIMM Module package (JEDEC MO-190)  
(144 pin, dual read-out, single in-line memory module)  
67,6±  
0.15  
3.8 max.  
63,6  
1
59  
61  
62  
143  
144  
1±  
0.1  
3.3  
23.2  
32.8  
2.6  
4.6  
1.5  
60  
1.8  
3.7  
2
4
Detail of Contacts  
Detail of Chamfer  
0.6  
0.2 -0.15  
0.8  
L-DIM-144-10  
note: all tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
13  
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
256 MByte SO-DIMM Module package (JEDEC MO-190)  
(144 pin, dual read-out, single in-line memory module)  
67.6 ±  
0.15  
3.8 max.  
63.6  
1
59  
61  
143  
144  
±
0.1  
3.3  
1
23.2  
24.5  
32.8  
2.5  
4.6  
1.5  
60  
1.8  
3.7  
2
62  
4
Detail of Contacts  
Detail of Chamfer  
0.6  
0.2 -0.15  
0.8  
L-DIM-144-9  
note: all tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
14  
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
Change List  
6.99  
First and preliminary version, -8A only  
-7.5 and -8 speed sorts added  
19.1.2000  
19.7.2000  
24.7.2000  
CKE1 added to the block diagram  
GDL versions added for 256Mbit S17-C2 with 1.5mA ICC6 per  
component  
25.7.2000  
5.9.2000  
-8A speed sort removed  
backward compatibility for C2base modules clarifed  
ICC6 changed from 6mA to 6.8 mA per memory bank after  
the component datasheet for 256M S17 changed from 1.5 to  
1.7 mA  
ICC2PS changed from 16 to 8 mA  
24.11.2000  
ICC6 changed from 6.8 to 7.2 mA  
(Request from Axel Hahn and Uwe Fritsch)  
Component datasheet unchanged at ICC6=1.7mA  
Preliminary Capacitance Values added  
15.12.2000  
5.3.2001  
All reference to older versions based on 256M S20 removed  
ICC currents, where wrong and have been corrected according  
to the latest 256M S17 datasheet  
9.07.2001  
6.09.2001  
HYS64V16200GL-7/-7.5 and -8 added  
HYS64V1632220GDL-7 added  
SCR : Absolute Maximum Ratings Table added  
INFINEON Technologies  
15  
9.01  
HYS64V16200GDL/HYS64V32220GDL  
144 pin SO-DIMM SDRAM Modules  
INFINEON Technologies  
16  
9.01  
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HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

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