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8N3D085LC-0036CDI

型号：

8N3D085LC-0036CDI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

537 K

下载PDF手册
IDT8N3D085  
LVPECL Dual Frequency  
Programmable Crystal Oscillator  
DATA SHEET  
General Description  
Features  
The IDT8N3D085 is a LVPECL Dual Frequency-Programmable  
Crystal Oscillator with very flexible frequency programming  
capabilities. The device uses IDT’s fourth generation FemtoClock®  
NG technology for an optimum of high clock frequency and low phase  
noise performance. The device accepts 2.5V or 3.3V supply and is  
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm  
x 1.55mm package.  
• Fourth generation FemtoClock® NG technology  
• Factory-programmable clock output frequency from  
15.476MHz to 866.67MHz and from 975MHz to 1,300MHz  
• Frequency programming resolution is 218Hz and better  
• One 2.5V or 3.3V LVPECL clock output  
• Output enable control (positive polarity),   
LVCMOS/LVTTL compatible  
The device can be programmed to any frequency in the range from  
15.476MHz to 866.67MHz and from 975MHz to 1,300 MHz and  
supports a very high degree of frequency precision of 218Hz or  
better. One of two pre-set output frequencies is selected by the  
FSEL pin.The extended temperature range supports wireless  
infrastructure, telecommunication and networking end equipment  
requirements.  
• LVCMOS compatible control inputs  
• RMS phase jitter @ 156.25MHz (12kHz - 20MHz):   
0.24ps (typical), integer PLL feedback configuration  
• RMS phase jitter @ 156.25MHz (1kHz - 40MHz):  
0.27ps (typical), integer PLL feedback configurationally  
• 2.5V or 3.3V supply  
• -40°C to 85°C ambient operating temperature  
• Available in a lead-free (RoHS 6) 6-pin ceramic package  
Block Diagram  
Pin Assignment  
OE 1  
FSEL 2  
VEE 3  
6 VCC  
5 nQ  
4 Q  
FemtoClock® NG  
VCO  
1950-2600MHz  
PFD  
&  
LPF  
Q  
nQ  
÷P  
OSC  
÷N  
fREF  
IDT8N3D085  
÷MINT, MFRAC  
6-lead ceramic 5mm x 7mm x 1.55mm  
package body  
2
CD Package  
Top View  
7
25  
Configuration Register (ROM)  
Pulldown  
Pullup  
FSEL  
OE  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
1
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Pin Description and Characteristic Tables  
Table 1. Pin Descriptions  
Number  
Name  
OE  
Type  
Pullup  
Pulldown  
Description  
1
2
Input  
Input  
Output enable pin. See table 3A for function. LVCMOS/LVTTL interface levels.  
FSEL  
VEE  
Frequency select pin. See table 3B for function. LVCMOS/LVTTL interface levels.  
Negative supply pin.  
3
Power  
Output  
Power  
4, 5  
6
Differential clock output pair. LVPECL interface levels.  
Q, nQ  
VCC  
Power supply pin.  
NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
5.5  
Maximum  
Units  
pF  
CIN  
Input Capacitance  
RPULLDOWN Input Pulldown Resistor  
RPULLUP Input Pullup Resistor  
50  
k  
50  
k  
Function Tables  
Table 3A. OE Configuration  
Input  
OE  
0
Output Enable  
Output Q, nQ is in high-impedance state.  
Output Q, nQ is enabled.  
1 (default)  
NOTE: OE is an asynchronous control.  
Table 3B. Frequency Selection  
Input  
FSEL  
0 (default)  
1
Operation  
Frequency 0  
Frequency 1  
NOTE: Frequency 0 and 1 are factory-programmed by IDT. Any frequency combination within the available  
frequency range (see table 3C) can be ordered. For order information, see FemtoClock NG Ceramic-Package  
XO and VCXO Ordering Product Information document.  
Table 3C. Output Frequency Range  
15.476MHz to 866.67MHz  
975 MHz to 1,300MHz  
NOTE: Supported output frequency range. The output frequency can be programmed to any  
frequency in this range and to a precision of 218 Hz or better.  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
2
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Principles of Operation  
The block diagram consists of the internal 3rd overtone crystal and  
oscillator which provide the reference clock fXTAL of either  
114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO  
along with the Pre-divider (P), the feedback divider (M) and the post  
divider (N). The P, M, and N dividers determine the output frequency  
based on the fXTAL reference. The configuration of the feedback  
divider to integer-only values results in an improved output phase  
noise characteristics at the expense of the range of output  
frequencies. Internal registers are used to hold up to two different  
factory pre-set configuration settings. The configuration is selected  
via the FSEL pin. Changing the FSEL control results in an immediate  
change of the output frequency to the selected register values. The  
P, M, and N frequency configurations support an output frequency  
range from 15.476MHz to 866.67MHz and from 975MHz to  
1,300MHz.  
Table 3D. Frequency Selection  
Input  
FSEL  
0 (default)  
1
Selects  
Frequency 0  
Frequency 1  
Frequency Configuration  
An order code is assigned to each frequency configuration and the  
VCXO pull-range programmed by the factory (default frequencies).  
For more information on the available default frequencies and order  
codes, please see the Ordering Information Section in this document.  
For available order codes, see the FemtoClock NG Ceramic-Package  
XO and VCXO Ordering Product Information document.  
The devices use the fractional feedback divider with a delta-sigma  
modulator for noise shaping and robust frequency synthesis  
capability. The relatively high reference frequency minimizes phase  
noise generated by frequency multiplication and allows more efficient  
shaping of noise by the delta-sigma modulator. The output frequency  
is determined by the 2-bit pre-divider (P), the feedback divider (M)  
and the 7-bit post divider (N). The feedback divider (M) consists of  
both a 7-bit integer portion (MINT) and an 18-bit fractional portion  
(MFRAC) and provides the means for high-resolution frequency  
generation. The output frequency fOUT is calculated by:  
For more information on programming capabilities of the device for  
custom frequency and pull-range configurations, see the FemtoClock  
NG Ceramic 5x7 Module Programming Guide.  
1
P N  
MFRAC + 0.5  
------------  
f
= f  
MINT + ------------------------------------- (1)  
OUT  
XTAL  
18  
2
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
3
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum  
Ratings may cause permanent damage to the device. These ratings  
are stress specifications only. Functional operation of product at  
these conditions or any conditions beyond those listed in the DC  
Characteristics or AC Characteristics is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect  
product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
3.63V  
-0.5V to VCC + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
Package Thermal Impedance, JA  
49.4C/W (0 mps)  
-65C to 150C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
Units  
V
Power Supply Voltage  
Power Supply Current  
3.135  
IEE  
123  
148  
mA  
Table 4B. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
2.625  
Units  
V
Power Supply Voltage  
Power Supply Current  
2.375  
IEE  
119  
143  
mA  
Table 4C. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
VCC = 3.3V  
Minimum  
2
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
V
VIH Input High Voltage  
VCC = 2.5V  
1.7  
V
OE  
-0.3  
-0.3  
-0.3  
-0.3  
V
VCC = 3.3V  
VCC = 2.5V  
FSEL  
OE  
0.5  
V
VIL  
Input Low Voltage  
0.7  
V
FSEL  
OE  
0.5  
V
VCC = VIN = 3.465V or 2.625V  
VCC = VIN = 3.465V or 2.625V  
CC = 3.465V or 2.625V, VIN = 0V  
CC = 3.465V or 2.625V, VIN = 0V  
10  
µA  
µA  
µA  
µA  
IIH  
Input High Current  
Input Low Current  
FSEL  
OE  
150  
V
V
-150  
-5  
IIL  
FSEL  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
4
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Table 4D. LVPECL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC – 1.4  
VCC – 2.0  
0.6  
Typical  
Maximum  
VCC – 0.8  
VCC – 1.6  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Peak-to-Peak Output Voltage Swing  
V
V
V
VOL  
VSWING  
NOTE 1: Outputs terminated with 50to VCC – 2V  
Table 4E. LVPECL DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCC – 1.4  
VCC – 2.0  
0.4  
Typical  
Maximum  
VCC – 0.8  
VCC – 1.5  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Peak-to-Peak Output Voltage Swing  
V
V
V
VOL  
VSWING  
NOTE 1: Outputs terminated with 50to VCC – 2V  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
5
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
AC Electrical Characteristics  
Table 5. AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
fOUT  
fI  
Parameter  
Test Conditions  
Minimum  
15.476  
975  
Typical  
Maximum  
Units  
MHz  
MHz  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
ps  
866.67  
1,300  
10  
Output Frequency  
Initial Accuracy  
Measured at 25°C  
Option code = A or B  
100  
50  
fS  
fA  
fT  
Temperature Stability  
Aging  
Option code = E or F  
Option code = K or L  
20  
Frequency drift over 10 year life  
Frequency drift over 15 year life  
Option code A or B (10 year life)  
Option code E or F (10 year life)  
Option code K or L (10 year life)  
3
5
113  
63  
Total Stability  
33  
tjit(cc)  
Cycle-to-Cycle Jitter; NOTE 1  
RMS Period Jitter, NOTE 1  
30  
tjit(per)  
1.9  
2.8  
ps  
RMS Phase Jitter (Random);  
Fractional PLL feedback and  
fXTAL=100.000MHz (2xxx  
order codes)  
17MHz fOUT 1300MHz,  
0.497  
0.882  
ps  
NOTE 2, 3, 4  
500MHz fOUT 1300MHz, NOTE  
0.232  
0.250  
0.275  
0.322  
0.384  
0.405  
ps  
ps  
ps  
2, 3, 4  
125MHz fOUT 500MHz,  
RMS Phase Jitter (Random);  
Integer PLL feedback and  
fXTAL=100.00MHz (1xxx order  
codes)  
NOTE 2, 3, 4  
tjit(Ø)  
17MHz fOUT 125MHz,  
NOTE 2, 3, 4  
fOUT 156.25MHz, NOTE 2, 3, 4  
fOUT 156.25MHz, NOTE 2, 3, 5  
0.242  
0.275  
0.311  
0.359  
ps  
ps  
RMS Phase Jitter (Random)  
Fractional PLL feedback and  
fXTAL=114.285MHz (0xxx  
order codes)  
17MHz fOUT 1300MHz,  
0.474  
0.986  
ps  
NOTE 2, 3, 4  
Single-side band phase noise,   
100Hz from Carrier  
N(100)  
N(1k)  
f
OUT = 156.25MHz  
-92  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Single-side band phase noise,   
1kHz from Carrier  
fOUT = 156.25MHz  
fOUT = 156.25MHz  
fOUT = 156.25MHz  
fOUT = 156.25MHz  
-120  
-131  
-138  
-139  
-154  
Single-side band phase noise,   
10kHz from Carrier  
N(10k)  
N(100k)  
N(1M)  
Single-side band phase noise,   
100kHz from Carrier  
Single-side band phase noise,   
1MHz from Carrier  
Single-side band phase noise,   
10MHz from Carrier  
N(10M)  
fOUT = 156.25MHz  
20% to 80%  
dBc/Hz  
ps  
tR / tF  
Output Rise/Fall Time  
50  
450  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
6
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
AC Electrical Characteristics, continued  
Table 5. AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
%
odc  
Output Duty Cycle  
47  
53  
20  
tSTARTUP Oscillator Start-Up Time  
ms  
Output Frequency Settling  
tSET  
1
ms  
Time After FSEL Changed  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.  
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.  
NOTE 2: Refer to the phase noise plots.  
NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the  
optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes.  
NOTE 4: Integration range: 12kHz - 20MHz.  
NOTE 5: Integration range: 1kHz - 40MHz.  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
7
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)  
Offset Frequency (Hz)  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
8
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
V
V
Qx  
CC  
CC  
Qx  
nQx  
nQx  
VEE  
VEE  
-1.3V 0.165V  
-0.5V 0.125V  
3.3V Output Load Test Circuit  
2.5V Output Load Test Circuit  
Phase Noise Plot  
VOH  
VREF  
VOL  
1σ contains 68.26% of all measurements  
2σ contains 95.4% of all measurements  
3σ contains 99.73% of all measurements  
4σ contains 99.99366% of all measurements  
6σ contains (100-1.973x10-7)% of all measurements  
Offset Frequency  
Histogram  
f1  
f2  
Reference Point  
(Trigger Edge)  
RMS Phase Jitter =  
Mean Period  
(First edge after trigger)  
1
*
Area Under Curve Defined by the Offset Frequency Markers  
2 * * ƒ  
RMS Phase Jitter  
RMS Period Jitter  
nQ  
Q
nQ  
80%  
tF  
80%  
tR  
VSWING  
20%  
➤
➤
tcycle n  
tcycle n+1  
➤
➤
20%  
Q
tjit(cc) = tcycle n – tcycle n+1  
|
|
1000 Cycles  
Output Rise/Fall Time  
Cycle-to-Cycle Jitter  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
9
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Parameter Measurement Information, continued  
nQ  
Q
tPW  
tPERIOD  
tPW  
odc =  
x 100%  
tPERIOD  
Output Duty Cycle/Pulse Width/Period  
Applications Information  
Recommendations for Unused Input Pins  
Inputs:  
LVCMOS Control Pins  
All control pins have internal pullups or pulldowns; additional  
resistance is not required but can be added for additional protection.  
A 1kresistor can be used.  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 1A and 1B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50  
3.3V  
R3  
125Ω  
R4  
125Ω  
3.3V  
3.3V  
3.3V  
Z
o = 50Ω  
3.3V  
+
_
Z
Z
o = 50Ω  
+
_
Input  
LVPECL  
Zo = 50Ω  
LVPECL  
Input  
o = 50Ω  
R1  
R2  
50Ω  
50Ω  
R1  
84Ω  
R2  
84Ω  
VCC - 2V  
1
RTT =  
* Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
Figure 1A. 3.3V LVPECL Output Termination  
Figure 1B. 3.3V LVPECL Output Termination  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
10  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Termination for 2.5V LVPECL Outputs  
Figure 2A and Figure 2B show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating 50  
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground  
level. The R3 in Figure 2B can be eliminated and the termination is  
shown in Figure 2C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
R1  
R3  
50Ω  
250Ω  
250Ω  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
2.5V LVPECL Driver  
50Ω  
50Ω  
R2  
R4  
62.5Ω  
62.5Ω  
R3  
18Ω  
Figure 2A. 2.5V LVPECL Driver Termination Example  
Figure 2B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
R2  
50Ω  
50Ω  
Figure 2C. 2.5V LVPECL Driver Termination Example  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
11  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Schematic Layout  
Figure 3 shows an example IDT8N3D085 application schematic.  
The schematic example focuses on functional connections and is  
intended as an example only and may not represent the exact user  
configuration. Refer to the pin description and functional tables in  
the datasheet to ensure the logic control inputs are properly set. For  
example OE and FSEL can be configured from an FPGA instead of  
set with pull up and pull down resistors as shown.  
PCB as close to the power pins as possible. If space is limited, the  
0.1uF capacitor on the VCC pin must be placed on the device side  
with direct return to the ground plane though vias. The remaining  
filter components can be on the opposite side of the PCB.  
Power supply filter component recommendations are a general  
guideline to be used for reducing external noise from coupling into  
the devices. The filter performance is designed for a wide range of  
noise frequencies. This low-pass filter starts to attenuate noise at  
approximately 10kHz. If a specific frequency noise component is  
known, such as switching power supplies frequencies, it is  
recommended that component values be adjusted and if required,  
additional filtering be added. Additionally, good general design  
practices for power plane voltage stability suggests adding bulk  
capacitance in the local area of all devices.  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise, so to achieve optimum jitter  
performance isolation of the VCC pin from power supply is required.  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
Logic Control Input Examples  
Set Logic  
Input to '1'  
Set Logic  
Input to '0'  
VCC  
VCC  
RU1  
1K  
RU2  
Not Install  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
RD1  
Not Install  
RD2  
1K  
3.3V  
FB1  
2
1
VCC  
C4  
10uF  
BLM18BB221SN1  
C5  
0.1uF  
Place 0.1uF bypass cap  
directly adjacent to  
the VCC pin.  
U1  
1
2
3
6
4
5
OE  
C3  
0.1uF  
OE  
VCC  
Zo = 50 Ohm  
FSEL  
FSEL  
VEE  
Q
+
Zo = 50 Ohm  
nQ  
-
R2  
50  
R1  
50  
+3.3V PECL Receiver  
R3  
50  
For other AC and DC termination options consult  
the IDT Applications Note  
"Termination - LVPECL"  
Figure 3. IDT8N3D085 Application Schematic  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
12  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8N3D085.   
Equations and example calculations are also provided.  
1. Power Dissipation  
The total power dissipation for the IDT8N3D085 is the sum of the core power plus the output power dissipated due to the loading.   
The following is the power dissipation for VCC = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating output power dissipated due to the loading.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 148mA = 512.82mW  
Power (outputs)MAX = 32mW/Loaded Output pair  
Total Power_MAX (3.465V, with all outputs switching) = 512.82mW + 32mW = 544.82mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.545W * 49.4°C/W = 111.9°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 6 Lead Ceramic 5mm x 7mm Package, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
13  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
LVPECL output driver circuit and termination are shown in Figure 4.  
VCC  
Q1  
VOUT  
RL  
VCC - 2V  
Figure 4. LVPECL Driver Circuit and Termination  
To calculate output power dissipation due to the loading, use the following equations which assume a 50load, and a termination voltage of  
VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V  
(VCC_MAX – VOH_MAX) = 0.8V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V  
(VCC_MAX – VOL_MAX) = 1.6V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX– VOH_MAX) =  
[(2V – 0.8V)/50] * 0.8V = 19.2mW  
Pd_L = [(VOL_MAX – (VCC_MAX– 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX– VOL_MAX) =  
[(2V – 1.6V)/50] * 1.6V = 12.8mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
14  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Reliability Information  
Table 7. JA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package  
JA vs. Air Flow  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
Transistor Count  
The transistor count for IDT8N3D085 is: 47,511  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
15  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Package Outline and Package Dimensions  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
16  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products  
The programmable VCXO and XO devices support a variety of  
devices options such as the output type, number of default frequen-  
cies, internal crystal frequency, power supply voltage, ambient  
temperature range and the frequency accuracy. The device options,  
default frequencies and default VCXO pull range must be specified at  
the time of order and are programmed by IDT before the shipment.  
The table below specifies the available order codes, including the  
device options and default frequency configurations. Example part  
number: the order code 8N3QV01FG-0001CDI specifies a  
contains a 114.285MHz internal crystal as frequency source,  
industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic  
5mm x 7mm x 1.55mm package and is factory-programmed to the  
default frequencies of 100, 122.88, 125 and 156.25MHz and to the  
VCXO pull range of min. 100 ppm.  
Other default frequencies and order codes are available from IDT on  
request. For more information on available default frequencies, see  
the FemtoClock NG Ceramic-Package XO and VCXO Ordering  
Product Information document.  
programmable, quad default-frequency VCXO with a voltage supply  
of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy,  
Part/Order Numbers  
8N X X XXX X X - dddd XX X X  
Shipping Package  
8: Tape & Reel  
(no letter): Tray  
FemtoClock NG  
I/O Identifier  
Ambient Temperature Range  
“I”: Industrial: (TA = -40°C to 85°C)  
(no letter) : (TA = 0°C to 70°C)  
0: LVCMOS  
3: LVPECL  
4: LVDS  
Package Code  
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm  
Number of Default Frequencies  
S: 1: Single  
D: 2: Dual  
Q: 4: Quad  
Default-Frequency and VCXO Pull Range  
See document FemtoClock NG Ceramic-Package XO and VCXO  
Ordering Product Information.  
dddd  
fXTAL (MHz) PLL feedback  
Use for  
VCXO, XO  
XO  
Part Number  
0000 to 0999  
1000 to 1999  
2000 to 2999  
114.285  
Fractional  
Integer  
OEfct. at  
Function #pins  
pin  
100.000  
Fractional  
XO  
001  
003  
V01  
V03  
V75  
V76  
V85  
085  
270  
271  
272  
273  
XO  
XO  
10  
10  
10  
10  
6
OE@2  
OE@1  
OE@2  
OE@1  
OE@2  
nOE@2  
—
Last digit = L: configuration pre-programmed and not changeable  
VCXO  
VCXO  
VCXO  
VCXO  
VCXO  
XO  
Die Revision  
C
6
6
Option Code (Supply Voltage and Frequency-Stability)  
6
OE@1  
OE@1  
OE@2  
nOE@2  
nOE@1  
A: VCC = 3.3V 5%, 100ppm  
B: VCC = 2.5V 5%, 100ppm  
XO  
6
XO  
6
E: VCC = 3.3V 5%,  
F: VCC = 2.5V 5%,  
K: VCC = 3.3V 5%,  
L: VCC = 2.5V 5%,  
50ppm  
50ppm  
20ppm  
20ppm  
XO  
6
XO  
6
NOTE: For order information, also see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document.  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
17  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
Device Marking  
Table 8. Device Marking  
Industrial Temperature Range (TA = -40°C to 85°C)  
N3D085yCddddI  
Commercial Temperature Range (TA = 0°C to 70°C)  
Marking  
8N3D085yCdddd  
y = Option Code, dddd=Default-Frequency and VCXO Pull Range  
IDT8N3D085CCD REVISION A DECEMBER 14, 2012  
18  
©2012 Integrated Device Technology, Inc.  
IDT8N3D085 Data Sheet  
LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road  
Sales  
Technical Support  
netcom@idt.com  
800-345-7015 (inside USA)  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-  
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2012. All rights reserved.  
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