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CYM1841BPMX-45C

型号：

CYM1841BPMX-45C

品牌：

CYPRESS[ CYPRESS ]

页数：

9 页

PDF大小：

91 K

下载PDF手册
CYM1841B  
256K x 32 Static RAM Module  
selects (CS1, CS2, CS3, CS4) are used to independently  
enable the four bytes. Reading or writing can be executed on  
individual bytes or any combination of multiple bytes through  
proper use of selects.  
Features  
• High-density 8-megabit SRAM module  
• 32-bit standard footprint supports densities from  
16K x 32 through 1M x 32  
Writing to each byte is accomplished when the appropriate  
Chip Select (CS) and Write Enable (WE) inputs are both LOW.  
Data on the Input/Output pins (I/O) is written into the memory  
location specified on the address pins (A0 through A17).  
• High-speed CMOS SRAMs  
— Access time of 12 ns  
• Low active power  
Reading the device is accomplished by taking the Chip Select  
(CS) LOW while Write Enable (WE) remains HIGH. Under  
these conditions, the contents of the memory location  
specified on the address pins will appear on the data  
Input/Output pins (I/O).  
— 5.3W (max.) at 25 ns  
• SMD technology  
• TTL-compatible inputs and outputs  
• Low profile  
The data input/output pins stay at the high-impedance state  
when write enable is LOW or the appropriate chip selects are  
HIGH.  
— Max. height of 0.58 in.  
• Available in ZIP, SIMM, and angled SIMM footprint  
Two pins (PD0 and PD1) are used to identify module memory  
density in applications where alternate versions of the  
JEDEC-standard modules can be interchanged.  
• 72-pin SIMM version compatible with 1M x 32  
(CYM1851)  
Functional Description  
A 72-pin SIMM is offered for compatibility with the 1M x 32  
CYM1851. This version is socket upgradable to the CYM1851.  
The CYM1841B is a high-performance 8-megabit static RAM  
module organized as 256K words by 32 bits. This module is  
constructed from two 256K x 16 SRAMs in SOJ packages  
mounted on an epoxy laminate board with pins. Four chip  
Both the 64-pin and 72-pin SIMM modules are available with  
either tin-lead or 10 micro-inches of gold flash on the edge  
contacts.  
PD – GND  
0
Logic Block Diagram (1841B)  
PD – GND  
1
A –A  
PD – OPEN (72-pin only)  
2
0
17  
18  
PD – OPEN (72-pin only)  
3
OE  
WE  
CS  
1
CS  
2
3
CS  
CS  
4
I/O –I/O  
16  
23  
8
8
256K x 16  
SRAM  
I/O –I/O  
24  
31  
I/O –I/O  
0
7
8
8
256K x 16  
SRAM  
I/O –I/O  
8
15  
Cypress Semiconductor Corporation  
Document #: 38-05261 Rev. *A  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised April 24, 2003  
CYM1841B  
Selection Guide  
1841B-15  
1841B-20  
1841B-25  
1841B-35  
1841B-45  
Unit  
ns  
Maximum Access Time  
15  
400  
80  
20  
380  
80  
25  
380  
80  
35  
340  
80  
45  
340  
80  
Maximum Operating Current  
Maximum Standby Current  
mA  
mA  
Pin Configurations  
72-Pin  
SIMM  
Top View  
64-Pin  
ZIP/SIMM  
Top View  
NC  
PD  
1
NC  
PD  
2
3
2
3
4
5
GND  
1
I/O  
8
1
3
GND  
PD  
PD  
2
6
0
0
PD  
7
PD  
1
I/O  
I/O  
I/O  
I/O  
V
4
5
I/O  
I/O  
I/O  
8
9
0
1
2
3
0
1
2
I/O  
8
6
10  
7
I/O  
11  
12  
13  
I/O  
9
9
8
9
I/O  
10  
I/O  
10  
10  
14  
I/O  
V
3
CC  
A
11  
12  
13  
15  
16  
17  
I/O  
I/O  
15  
16  
17  
19  
20  
21  
11  
11  
CC  
A
0
A
0
14  
A
18  
7
A
1
7
A
1
A
8
A
8
9
A
2
A
2
A
18  
A
22  
9
19  
20  
21  
23  
24  
25  
27  
28  
29  
I/O  
23  
24  
25  
27  
28  
29  
31  
32  
33  
I/O  
12  
12  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
4
5
6
I/O  
13  
I/O  
13  
I/O  
I/O  
I/O  
22  
26  
I/O  
I/O  
14  
14  
I/O  
15  
I/O  
15  
26  
I/O  
30  
7
GND  
GND  
WE  
WE  
A
15  
2
A
15  
A
14  
A
14  
30  
32  
34  
31  
CS  
35  
CS  
CS  
1
CS  
2
1
36  
37  
CS  
A
CS  
4
4
17  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
CS  
3
CS  
3
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
38  
39  
A
17  
A
16  
A
40  
41  
16  
OE  
OE  
GND  
GND  
42  
I/O  
43  
I/O  
24  
24  
I/O  
I/O  
16  
44  
45  
16  
I/O  
I/O  
I/O  
I/O  
25  
25  
26  
27  
I/O  
17  
I/O  
46  
17  
I/O  
47  
26  
I/O  
I/O  
18  
48  
49  
18  
I/O  
27  
I/O  
19  
I/O  
50  
19  
A
A
51  
3
3
A
A
10  
52  
53  
10  
A
4
A
5
A
4
A
5
A
A
54  
55  
11  
A
11  
A
56  
12  
A
12  
V
V
57  
CC  
CC  
58  
59  
13  
A
13  
A
A
6
6
I/O  
60  
61  
I/O  
I/O  
I/O  
I/O  
20  
20  
21  
22  
23  
I/O  
I/O  
I/O  
I/O  
I/O  
28  
28  
29  
30  
31  
I/O  
21  
62  
63  
I/O  
29  
I/O  
64  
65  
22  
I/O  
30  
I/O  
23  
66  
67  
I/O  
31  
GND  
68  
69  
GND  
A
18  
A
19  
70  
71  
NC  
NC  
72  
Document #: 38-05261 Rev. *A  
Page 2 of 9  
CYM1841B  
DC Voltage Applied to Outputs  
in High Z State ..................................................... –0.5V to +7.0V  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
DC Input Voltage ................................................. –0.5V to +7.0V  
Operating Range  
Storage Temperature ..................................... –55°C to +125°C  
Ambient Temperature with  
Power Applied .................................................... –10°C to +85°C  
Range  
Ambient Temperature  
VCC  
Commercial  
0°C to +70°C  
5V ± 10%  
Supply Voltage to Ground Potential .................–0.5V to +7.0V  
Electrical Characteristics Over the Operating Range  
1841B  
-25, 35, 45  
1841B-15  
1841B-20  
Min. Max.  
2.4  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Leakage Current  
Test Conditions  
VCC = Min., IOH = –4.0 mA  
VCC = Min., IOL = 8.0 mA  
Min.  
Max.  
Min. Max. Unit  
VOH  
VOL  
VIH  
VIL  
2.4  
2.4  
V
V
0.4  
VCC  
0.8  
+3  
0.4  
0.4  
VCC  
0.8  
+3  
2.2  
–0.5  
–3  
2.2  
–0.5  
–3  
VCC  
0.8  
+3  
2.2  
–0.5  
–3  
V
V
IIX  
GND < VI < VCC  
uA  
uA  
IOZ  
Output Leakage Current GND < VO < VCC  
,
–2  
+2  
–2  
+2  
–2  
+2  
Output Disabled  
ICC  
VCC Operating  
Supply Current  
VCC = Max., IOUT = 0 mA,  
CS < VIL  
400  
80  
6
380  
80  
6
340  
80  
6
mA  
mA  
mA  
ISB1  
ISB2  
Automatic CS  
Max. VCC, CS > VIH,  
Min. Duty Cycle = 100%  
Power-down Current[1]  
Automatic CS  
Max. VCC, CS > VCC – 0.2V,  
VIN > VCC – 0.2V,  
Power-down Current[1]  
or VIN < 0.2V  
Capacitance[2]  
Parameter  
CIN  
Description  
Input Capacitance[3]  
Output Capacitance  
Test Conditions  
Max.  
Unit  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
16  
16  
pF  
pF  
COUT  
AC Test Loads and Waveforms  
R1 481Ω  
R1 481Ω  
ALL INPUT PULSES  
90%  
5V  
5V  
OUTPUT  
3.0V  
GND  
90%  
OUTPUT  
R2  
255Ω  
R2  
255Ω  
10%  
10%  
30 pF  
5 pF  
< 5ns  
< 5ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
167Ω  
OUTPUT  
1.73V  
Notes:  
1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.  
2. Tested on a sample basis.  
3. 20 pF on CS, 70 pF all others.  
Document #: 38-05261 Rev. *A  
Page 3 of 9  
CYM1841B  
Switching Characteristics Over the Operating Range[4]  
1841B-15  
1841B-20  
1841B-25  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
15  
3
20  
3
25  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Output Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
15  
20  
25  
tOHA  
tACS  
15  
7
20  
8
25  
8
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
3
0
4
0
4
OE HIGH to High Z  
CS LOW to Low Z[5]  
CS HIGH to High Z[5, 6]  
7
8
8
7
8
8
CS HIGH to Power-Down  
15  
18  
18  
Write Cycle[7]  
tWC  
Write Cycle Time  
15  
10  
10  
0
20  
15  
18  
0
25  
20  
20  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCS  
CS LOW to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
tAW  
tHA  
tSA  
2
2
2
tPWE  
tSD  
12  
7
15  
8
15  
8
Data Set-up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
1
2
2
tLZWE  
tHZWE  
0
0
0
WE LOW to High Z[6]  
0
6
0
8
0
8
[4]  
Switching Characteristics Over the Operating Range  
1841B-35  
1841B-45  
Parameter  
Description  
Min.  
35  
3
Max.  
Min.  
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
45  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CS LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
35  
45  
tOHA  
tACS  
35  
25  
45  
30  
tDOE  
tLZOE  
tHZOE  
tLZCS  
tHZCS  
tPD  
0
0
OE LOW to High Z  
CS LOW to Low Z[5]  
CS HIGH to High Z[5, 6]  
15  
15  
10  
10  
20  
35  
20  
45  
CS HIGH to Power-Down  
Write Cycle[7]  
tWC  
Write Cycle Time  
35  
45  
ns  
Notes:  
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
I
5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.  
6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.  
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-05261 Rev. *A  
Page 4 of 9  
CYM1841B  
Switching Characteristics Over the Operating Range (continued)[4]  
1841B-35  
1841B-45  
Min. Max.  
Parameter  
tSCS  
Description  
CS LOW to Write End  
Min.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
30  
30  
2
40  
40  
2
tAW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tHA  
tSA  
2
2
tPWE  
tSD  
30  
20  
2
35  
25  
2
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z  
tHD  
tLZWE  
tHZWE  
0
0
WE LOW to High Z[6]  
0
15  
0
15  
Switching Waveforms  
Read Cycle No. 1[8, 9]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2[8, 10]  
t
CS  
RC  
t
ACS  
OE  
t
HZOE  
t
DOE  
t
HZCS  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCS  
Notes:  
8. WE is HIGH for read cycle.  
9. Device is continuously selected, CS = VIL and OE= VIL.  
10. Address valid prior to or coincident with CS transition LOW.  
Document #: 38-05261 Rev. *A  
Page 5 of 9  
CYM1841B  
Switching Waveforms (continued)  
Write Cycle No. 1 (WE Controlled)[7]  
t
WC  
ADDRESS  
CS  
t
SCS  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Write Cycle No. 2 (CS Controlled)[7, 11]  
t
WC  
ADDRESS  
t
SA  
t
SCS  
CS  
t
t
HA  
AW  
t
PWE  
WE  
DATA IN  
t
t
HD  
SD  
DATA VALID  
t
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Truth Table  
CS  
H
WE  
X
OE  
X
Input/Output  
Mode  
High Z  
Deselect/Power-Down  
L
H
L
Data Out  
Data In  
High Z  
Read  
L
L
X
Write  
L
H
H
Deselect  
Note:  
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05261 Rev. *A  
Page 6 of 9  
CYM1841B  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CYM1841BPM-15C  
CYM1841BPZ-15C  
CYM1841BP7-15C  
CYM1841BPM-20C  
CYM1841BPZ-20C  
CYM1841BP7-20C  
CYM1841BPM-25C  
CYM1841BPZ-25C  
CYM1841BP7-25C  
CYM1841BPM-35C  
CYM1841BPZ-35C  
CYM1841BP7-35C  
CYM1841BPM-45C  
CYM1841BPZ-45C  
CYM1841BP7-45C  
Package Type  
64-Pin Plastic SIMM Module  
15  
PM03  
PZ08  
PM50  
PM03  
PZ08  
PM50  
PM03  
PZ08  
PM50  
PM03  
PZ08  
PM50  
PM03  
PZ08  
PM50  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
64-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
64-Pin Plastic SIMM Module  
64-Pin Plastic ZIP Module  
72-Pin Plastic SIMM Module  
20  
25  
35  
45  
Document #: 38-05261 Rev. *A  
Page 7 of 9  
CYM1841B  
Package Diagrams  
64-Pin ZIP Module – PZ08  
51-41310-**  
64-Pin Plastic SIMM Module – PM03  
51-41368-**  
72-Pin Plastic SIMM Module – PM50  
51-41375-**  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05261 Rev. *A  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM1841B  
Document History Page  
Document Title: CYM1841B 256K x 32 Static RAM Module  
Document Number: 38-05261  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
114352  
Description of Change  
3/22/02  
DSG  
CS  
Change from Spec number: 38-M-00031 to 38-05261  
*A  
125739  
04/28/03  
Changed Iix and Ioz unit to uA from mA and amended incorrected values  
shown on pages 2, 3 and 4.  
Document #: 38-05261 Rev. *A  
Page 9 of 9  
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