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HYS72T64020HP-3.7-A

型号：

HYS72T64020HP-3.7-A

品牌：

INFINEON[ Infineon ]

页数：

47 页

PDF大小：

1865 K

下载PDF手册
Data Sheet, Rev. 1.0, Mar 2006  
HYS72T32000HP–[3S/3.7]–A  
HYS72T64001HP–[3S/3.7]–A  
HYS72T64020HP–[3S/3.7]–A  
240-Pin Registered DDR2 SDRAM Modules  
DDR2 SDRAM  
RDIMM SDRAM  
RoHs Compliant  
Memory Products  
Edition 2006-03  
Published by Infineon Technologies AG,  
St.-Martin-Strasse 53,  
81669 München, Germany  
© Infineon Technologies AG 2006.  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as a guarantee of  
characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding  
circuits, descriptions and charts stated herein.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in  
question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
HYS72T32000HP–[3S/3.7]–A, HYS72T64001HP–[3S/3.7]–A, HYS72T64020HP–[3S/3.7]–A  
Revision History: 2006-03, Rev. 1.0  
Page  
Subjects (major changes since last revision)  
First Public Release  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send us your proposal (including a reference to this document) to:  
techdoc.mp@infineon.com  
Template: mp_a4_s_rev321 / 3 / 2005-10-05  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
2
2.1  
2.2  
Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
3
3.1  
3.2  
3.3  
3.3.1  
3.3.2  
3.3.3  
3.4  
3.4.1  
3.4.2  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Currents Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Data Sheet  
4
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
240-Pin Registered DDR2 SDRAM Modules  
DDR2 SDRAM  
HYS72T32000HP–[3S/3.7]–A  
HYS72T64001HP–[3S/3.7]–A  
HYS72T64020HP–[3S/3.7]–A  
1
Overview  
This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules with parity bit product family  
and describes its main characteristics.  
1.1  
Features  
•
•
240-pin PC2–5300 and PC2–4200 DDR2 SDRAM  
memory modules.  
One rank in 32M × 72, 64M x 72 and two rank in  
64M × 72 module organization and 32M × 8,  
64M × 4 chip organization  
256M, 512 MByte modules are built with 256-Mbit  
DDR2 SDRAMs in P-TFBGA-60 chipsize  
packages.  
Standard Double-Data-Rate-Two Synchronous  
DRAMs (DDR2 SDRAM) with a single + 1.8 V  
(± 0.1 V) power supply  
•
Programmable CAS Latencies (3, 4 and 5), Burst  
Length (4 & 8) and Burst Type  
•
•
Auto Refresh (CBR) and Self Refresh  
Average Refresh Period 7.8 µs at a TCASE lower  
than 85 °C, 3.9 µs between 85 °C and 95 °C  
Programmable self refresh rate via EMRS2 setting  
All inputs and outputs SSTL_18 compatible  
Off-Chip Driver Impedance Adjustment (OCD) and  
On-Die Termination (ODT)  
Serial Presence Detect with E2PROM  
Based on standard reference layouts Raw Cards  
“F”, “G” and “H”  
•
•
•
•
•
•
•
•
•
All speed grades faster than DDR2-400 comply with  
DDR2-400 timing specifications as well.  
Registered DIMM with Parity bit for address and  
control bus  
•
•
RDIMM with parity bit Dimensions (nominal):  
30.00 mm high, 133.35 mm wide  
RoHS compliant products1)  
Table 1  
Performance for PC2–5300–555  
Product Type Speed Code  
Speed Grade  
–3S  
Unit  
PC2–5300 5–5–5  
—
Max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
333  
266  
200  
15  
MHz  
MHz  
MHz  
ns  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
15  
ns  
tRAS  
tRC  
45  
ns  
60  
ns  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic  
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January  
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and  
polybrominated biphenyl ethers.  
Data Sheet  
5
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
OverviewFeatures  
Table 2  
Performance for PC2–4200–444  
Product Type Speed Code  
Speed Grade  
–3.7  
Unit  
PC2–4200 4–4–4  
—
Max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
266  
266  
200  
15  
MHz  
MHz  
MHz  
ns  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
15  
ns  
tRAS  
tRC  
45  
ns  
60  
ns  
Table 3  
Performance for PC2–3200–333  
Product Type Speed Code  
Speed Grade  
–5  
Units  
PC2–3200 3–3–3  
200  
—
Max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
MHz  
MHz  
MHz  
ns  
200  
200  
15  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
15  
ns  
tRAS  
tRC  
40  
ns  
55  
ns  
Data Sheet  
6
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
OverviewDescription  
1.2  
Description  
The INFINEON HYS72T[32/64]xxxHP–[3S/3.7]–A module family are Registered DIMM (RDIMM with parity) with  
30.00 mm height based on DDR2 technology. DIMMs are available as ECC modules in 32M × 72 (256 Mbyte) and  
64M x 72 (512 MByte) organization and density, intended for mounting into 240-Pin connector sockets.  
The memory array is designed with 256-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control  
and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This  
reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors  
are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device  
using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes  
are available to the customer.  
Table 4  
Ordering Information for RoHS Compliant Products  
Product Type1)  
Compliance Code2)  
Description SDRAM Technology  
PC2-5300  
HYS72T32000HP–3S–A  
HYS72T64001HP–3S–A  
HYS72T64020HP–3S–A  
PC2-4200  
256MB 1R×8 PC2–5300P–555–12–F0  
512MB 1R×4 PC2–5300P–555–12–H0  
512MB 2R×8 PC2–5300P–555–12–G0  
1 Rank, ECC 256 Mbit (×8)  
1 Rank, ECC 256 Mbit (×4)  
2 Rank, ECC 256 Mbit (×8)  
HYS72T32000HP–3.7–A  
HYS72T64001HP–3.7–A  
HYS72T64020HP–3.7–A  
256MB 1R×8 PC2–4200P–444–12–F0  
512MB 1R×4 PC2–4200P–444–12–H0  
512MB 2R×8 PC2–4200P–444–12–G0  
1 Rank, ECC 256 Mbit (×8)  
1 Rank, ECC 256 Mbit (×4)  
2 Rank, ECC 256 Mbit (×8)  
1) All Product Types end with a place code, designating the silicon die revision. Example: HYS72T64020HP–3.7–A, indicating  
Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see  
Chapter 6 of this data sheet.  
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–  
12–G0”, where 4200P means Very Low Profile Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-  
12” means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP)  
latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card “G”  
Table 5  
Address Format  
DIMM  
Module  
Memory ECC/  
# of  
# of row/bank/columns bits Raw Card  
Density  
Organization  
Ranks  
Non-ECC  
SDRAMs  
256 MB  
512 MB  
512 MB  
32M × 72  
64M × 72  
64M × 72  
1
1
2
ECC  
ECC  
ECC  
9
13/2/10  
13/2/11  
13/2/10  
F
18  
18  
H
G
Table 6  
Components on Modules 1)  
Product Type2)  
DRAM Components2)  
HYB18T256800AF  
HYB18T256400AF  
HYB18T256800AF  
DRAM Density  
256 Mbit  
DRAM Organization  
32M × 8  
HYS72T32000HP  
HYS72T64001HP  
HYS72T64020HP  
256 Mbit  
64M × 4  
256Mbit  
32M × 8  
1) For a detailed description of all available functions of the DRAM components on these modules see the component data  
sheet.  
2) Green Product  
Data Sheet  
7
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
2
Pin Configuration and Block Diagrams  
2.1  
Pin Configuration  
The pin configuration of the Registered DDR2 SDRAM explained in Table 8 and Table 9 respectively. The pin  
DIMM is listed by function in Table 7 (240 pins). The numbering is depicted in Figure 1.  
abbreviations used in columns Pin and Buffer Type are  
Table 7  
Pin Configuration of RDIMM  
Pin or Ball No.  
Name  
Pin  
Buffer Function  
Type Type  
Clock Signals  
185  
186  
CK0  
CK0  
I
I
SSTL  
SSTL  
Clock Signal CK0, Complementary Clock Signal CK0  
The system clock inputs. All address and command lines are  
sampled on the cross point of the rising edge of CK and the  
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven  
from the clock inputs and output timing for read operations is  
synchronized to the input clock.  
52  
CKE0  
CKE1  
I
I
SSTL  
SSTL  
Clock Enables 1:0  
Activates the DDR2 SDRAM CK signal when HIGH and  
deactivates the CK signal when LOW. By deactivating the  
clocks, CKE0 initiates the Power Down Mode or the Self  
Refresh Mode.  
171  
Note: 2-Ranks module  
Not Connected  
NC  
NC  
—
Note: 1-Rank module  
Control Signals  
193  
76  
S0  
S1  
I
I
SSTL  
SSTL  
Chip Select Rank 1:0  
Enables the associated DDR2 SDRAM command decoder  
when LOW and disables the command decoder when HIGH.  
When the command decoder is disabled, new commands are  
ignored but previous operations continue. Rank 0 is selected by  
S0; Rank 1 is selected by S1. The input signals also disable all  
outputs (except CKE and ODT) of the register(s) on the DIMM  
when both inputs are high. When S is HIGH, all register outputs  
(except CK, ODT and Chip select) remain in the previous state.  
Note: 2-Ranks module  
Not Connected  
NC  
NC  
—
Note: 1-Rank module  
192  
74  
RAS  
CAS  
WE  
I
I
I
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe  
(CAS), Write Enable (WE)  
When sampled at the cross point of the rising edge of CK, and  
falling edge of CK, RAS, CAS and WE define the operation to  
be executed by the SDRAM.  
73  
Data Sheet  
8
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
Table 7  
Pin Configuration of RDIMM (cont’d)  
Pin or Ball No.  
Name  
Pin  
Buffer Function  
Type Type  
18  
RESET  
I
CMOS Register Reset  
The RESET pin is connected to the RST pin on the register and  
to the OE pin on the PLL. When LOW, all register outputs will  
be driven LOW and the PLL clocks to the DRAMs and the  
register(s) will be set to low-level. The PLL will remain  
synchronized with the input clock.  
Address Signals  
71  
BA0  
BA1  
BA2  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus 1:0  
Selects internal SDRAM memory bank  
190  
54  
Bank Address Bus 2  
Greater than 512Mb DDR2 SDRAMS  
NC  
I
SSTL  
Not Connected  
Less than 1Gb DDR2 SDRAMS  
188  
183  
63  
A0  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Address Bus 12:0, Address Signal 10/AutoPrecharge  
During a Bank Activate command cycle, defines the row  
address when sampled at the crosspoint of the rising edge of  
CK and falling edge of CK. During a Read or Write command  
cycle, defines the column address when sampled at the cross  
point of the rising edge of CK and falling edge of CK. In addition  
to the column address, AP is used to invoke autoprecharge  
operation at the end of the burst read or write cycle. If AP is  
HIGH, autoprecharge is selected and BA[1:0] defines the bank  
to be precharged. If AP is LOW, autoprecharge is disabled.  
During a Precharge command cycle, AP is used in conjunction  
with BA[1:0] to control which bank(s) to precharge. If AP is  
HIGH, all banks will be precharged regardless of the state of  
BA[1:0] inputs. If AP is LOW, then BA[1:0] are used to define  
which bank to precharge.  
A1  
A2  
182  
61  
A3  
A4  
60  
A5  
180  
58  
A6  
A7  
179  
177  
70  
A8  
A9  
A10  
AP  
A11  
A12  
A13  
57  
176  
196  
Address Signal 13  
Note: modules based on ×4, ×8  
Not Connected  
NC  
A14  
NC  
NC  
I
—
Note: modules based on ×16  
Address Signal 14  
174  
SSTL  
—
Note: 2 Gbit based module  
Not Connected  
NC  
Note: 1 Gbit based module or smaller  
Data Sheet  
9
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
Table 7  
Pin Configuration of RDIMM (cont’d)  
Pin or Ball No.  
Name  
Pin  
Buffer Function  
Type Type  
Data Signals  
3
DQ0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Data Input/Output pins  
4
DQ1  
9
DQ2  
10  
DQ3  
122  
123  
128  
129  
12  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
13  
DQ9  
21  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
22  
131  
132  
140  
141  
24  
25  
30  
31  
143  
144  
149  
150  
33  
34  
39  
40  
152  
153  
158  
159  
80  
81  
86  
87  
199  
200  
205  
Data Sheet  
10  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
Table 7  
Pin Configuration of RDIMM (cont’d)  
Pin or Ball No.  
Name  
Pin  
Buffer Function  
Type Type  
206  
89  
DQ39  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
90  
95  
96  
208  
209  
214  
215  
98  
99  
107  
108  
217  
218  
226  
227  
110  
111  
116  
117  
229  
230  
235  
236  
Check Bits  
42  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bits 7:0  
Check Bit Input / Output pins  
43  
Note: NC on Non-ECC module  
48  
49  
161  
162  
167  
168  
Data Sheet  
11  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
Table 7  
Pin Configuration of RDIMM (cont’d)  
Pin or Ball No.  
Name  
Pin  
Buffer Function  
Type Type  
Data Strobe Bus  
7
DQS0  
DQS0  
DQS1  
DQS1  
DQS2  
DQS2  
DQS3  
DQS3  
DQS4  
DQS4  
DQS5  
DQS5  
DQS6  
DQS6  
DQS7  
DQS7  
DQS8  
DQS8  
DQS9  
DQS9  
DQS10  
DQS10  
DQS11  
DQS11  
DQS12  
DQS12  
DQS13  
DQS13  
DQS14  
DQS14  
DQS15  
DQS15  
DQS16  
DQS16  
DQS17  
DQS17  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobes 17:0  
The data strobes, associated with one data byte, sourced with  
data transfers. In Write mode, the data strobe is sourced by the  
controller and is centered in the data window. In Read mode the  
data strobe is sourced by the DDR2 SDRAM and is sent at the  
leading edge of the data window. DQS signals are  
complements, and timing is relative to the crosspoint of  
respective DQS and DQS. If the module is to be operated in  
single ended strobe mode, all DQS signals must be tied on the  
system board to VSS through a 20 ohm to 10 Kohm resistor and  
DDR2 SDRAM mode registers programmed appropriately.  
6
16  
15  
28  
27  
37  
36  
84  
83  
Note: See block diagram for corresponding DQ signals  
93  
92  
105  
104  
114  
113  
46  
45  
125  
126  
134  
135  
146  
147  
155  
156  
202  
203  
211  
212  
223  
224  
232  
233  
164  
165  
Data Sheet  
12  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
Table 7  
Pin Configuration of RDIMM (cont’d)  
Pin or Ball No.  
Name  
Pin  
Buffer Function  
Type Type  
Data Mask  
125  
DM0  
DM1  
DM2  
DM3  
DM4  
DM5  
DM6  
DM7  
DM8  
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Masks 7:0  
The data write masks, associated with one data byte. In Write  
mode, DM operates as a byte mask by allowing input data to be  
written if it is LOW but blocks the write operation if it is HIGH. In  
Read mode, DM lines have no effect.  
134  
146  
155  
202  
Note: ×8 based module  
211  
223  
232  
164  
EEPROM  
120  
SCL  
SDA  
I
CMOS Serial Bus Clock  
This signal is used to clock data into and out of the SPD  
EEPROM.  
119  
I/O  
OD  
Serial Bus Data  
This is a bidirectional pin used to transfer data into or out of the  
SPD EEPROM. A resistor must be connected from SDA to  
V
DDSPD on the motherboard to act as a pull-up.  
239  
240  
101  
Parity  
55  
SA0  
SA1  
SA2  
I
I
I
CMOS Serial Address Select Bus 2:0  
These signals are tied at the system planar to either VSS or  
DDSPD to configure the serial SPD EEPROM address range  
CMOS  
CMOS  
V
ERR_OUT  
PAR_IN  
O
I
CMOS Parity bits  
CMOS  
Note: Only for modules with parity bit for address and control  
bus. Not connected on non-parity registered modules.  
Power Supplies  
1
VREF  
AI  
—
I/O Reference Voltage  
Reference voltage for the SSTL-18 inputs.  
238  
VDDSPD  
PWR —  
EEPROM Power Supply  
Serial EEPROM positive power supply, wired to a separated  
power pin at the connector which supports from 1.7 Volt to 3.6  
Volt.  
51, 56, 62, 72, 75, VDDQ  
78, 170, 175,,  
181, 191, 194  
PWR —  
PWR —  
I/O Driver Power Supply  
Power and ground for the DDR SDRAM  
53, 59, 64, 67, 69, VDD  
172, 178, 184,,  
Power Supply  
Power and ground for the DDR SDRAM  
187, 189, 197  
Data Sheet  
13  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
Table 7  
Pin Configuration of RDIMM (cont’d)  
Name Pin Buffer Function  
Pin or Ball No.  
Type Type  
2, 5, 8, 11, 14, 17, VSS  
20, 23, 26, 29, 32,  
35, 38, 41, 44, 47,  
50, 65, 66, 79, 82,  
85, 88, 91, 94, 97,  
100, 103, 106,  
109, 112, 115,  
118, 121, 124,  
127, 130, 133,  
136, 139, 142,  
145, 148, 151,  
154, 157, 160,  
163, 166, 169,  
198, 201, 204,  
207, 210, 213,  
216, 219, 222,  
225, 228, 231,  
234, 237  
GND —  
Ground Plane  
Power and ground for the DDR SDRAM  
Other Pins  
19, 55, 68, 102,  
137, 138, 173,  
220, 221  
NC  
NC  
—
Not connected  
Pins not connected on Infineon RDIMM’s  
195  
77  
ODT0  
ODT1  
I
I
SSTL  
SSTL  
On-Die Termination Control 1:0  
Asserts on-die termination for DQ, DM, DQS, and DQS signals  
if enabled via the DDR2 SDRAM mode register.  
Note: 2-Ranks module  
NC  
NC  
—
Note: 1-Rank modules  
Table 8  
Abbreviations for Buffer Type  
Description  
Abbreviation  
SSTL  
Serial Stub Terminated Logic (SSTL_18)  
CMOS Levels  
CMOS  
OD  
Open Drain. The corresponding pin has 2 operational states, active low and  
tristate, and allows multiple devices to share as a wire-OR.  
Data Sheet  
14  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
Table 9  
Abbreviations for Pin Type  
Abbreviation  
Description  
I
Standard input-only pin. Digital levels.  
Output. Digital levels.  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
O
I/O  
AI  
PWR  
GND  
NU  
NC  
Ground  
Not Usable  
Not Connected  
Data Sheet  
15  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
ꢃ
                                        
                                         
                                          
                                                                                                                    
                                                                                                                     
                                                                                                                      
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsPin Configuration  
95() ꢃ 3LQꢄꢀꢀꢁ  
'4ꢀ ꢃ 3LQꢄꢀꢀꢅ  
966 ꢃ 3LQꢄꢀꢀꢆ  
'46ꢀ ꢃ 3LQꢄꢀꢀꢂ  
'4ꢈ ꢃ 3LQꢄꢀꢀꢇ  
966 ꢃ 3LQꢄꢀꢁꢁ  
'4ꢇ ꢃ 3LQꢄꢀꢁꢅ  
'46ꢁ ꢃ 3LQꢄꢀꢁꢆ  
966 ꢃ 3LQꢄꢀꢁꢂ  
1& ꢃ 3LQꢄꢀꢁꢇ  
3LQꢄꢁꢈꢁ ꢃ 966  
3LQꢄꢁꢈꢈ ꢃ '4ꢉ  
966 ꢃ 3LQꢄꢀꢀꢈ  
'4ꢁ ꢃ 3LQꢄꢀꢀꢉ  
'46ꢀ ꢃ 3LQꢄꢀꢀꢊ  
966 ꢃ 3LQꢄꢀꢀꢋ  
'4ꢅ ꢃ 3LQꢄꢀꢁꢀ  
'4ꢋ ꢃ 3LQꢄꢀꢁꢈ  
966 ꢃ 3LQꢄꢀꢁꢉ  
3LQꢄꢁꢈꢅ ꢃ '4ꢆ  
3LQꢄꢁꢈꢉ ꢃ 966  
3LQꢄꢁꢈꢆ ꢃ '0ꢀꢌ'46ꢇ  
3LQꢄꢁꢈꢊ ꢃ 1&ꢌ'46ꢇ  
3LQꢄꢁꢈꢂ ꢃ 966  
3LQꢄꢁꢈꢋ ꢃ '4ꢊ  
3LQꢄꢁꢈꢇ ꢃ '4ꢂ  
3LQꢄꢁꢅꢀ ꢃ 966  
3LQꢄꢁꢅꢁ ꢃ '4ꢁꢈ  
3LQꢄꢁꢅꢈ ꢃ '4ꢁꢅ  
3LQꢄꢁꢅꢅ ꢃ 966  
3LQꢄꢁꢅꢉ ꢃ '0ꢁꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢆ ꢃ 1&ꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢊ ꢃ 966  
'46ꢁ ꢃ 3LQꢄꢀꢁꢊ  
5(6(7 ꢃ 3LQꢄꢀꢁꢋ  
966 ꢃ 3LQꢄꢀꢈꢀ  
3LQꢄꢁꢅꢂ ꢃ 1&  
3LQꢄꢁꢅꢇ ꢃ 966  
3LQꢄꢁꢉꢁ ꢃ '4ꢁꢆ  
3LQꢄꢁꢉꢅ ꢃ '4ꢈꢀ  
3LQꢄꢁꢉꢆ ꢃ 966  
3ꢄLQꢄꢁꢉꢂ ꢃ 1&ꢌ'46ꢁꢁ  
3LQꢄꢁꢉꢇ ꢃ '4ꢈꢈ  
3LQꢄꢁꢆꢁ ꢃ 966  
3LQꢄꢁꢆꢅ ꢃ '4ꢈꢇ  
3LQꢄꢁꢆꢆ ꢃ '0ꢅꢌ'46ꢁꢈ  
3LQꢄꢁꢆꢂ ꢃ 966  
3LQꢄꢁꢆꢇ ꢃ '4ꢅꢁ  
3LQꢄꢁꢊꢁ ꢃ &%ꢉ  
3LQꢄꢁꢊꢅ ꢃ 966  
3LQꢄꢁꢊꢆ ꢃ 1&ꢌ'46ꢁꢂ  
3LQꢄꢁꢊꢂ ꢃ &%ꢊ  
3LQꢄꢁꢊꢇ ꢃ 966  
3LQꢄꢁꢂꢁ ꢃ 1&ꢌ&.(ꢁ  
3LQꢄꢁꢂꢅ ꢃ 1&  
3LQꢄꢁꢂꢆ ꢃ 9''4  
3LQꢄꢁꢂꢂ ꢃ $ꢇ  
3LQꢄꢁꢂꢇ ꢃ $ꢋ  
3LQꢄꢁꢅꢋ ꢃ 1&  
3LQꢄꢁꢉꢀ ꢃ '4ꢁꢉ  
ꢃ
3LQꢄꢁꢉꢈ 966  
ꢃ
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966  
3LQꢄꢀꢈꢁ  
3LQꢄꢀꢈꢅ  
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'4ꢁꢁ 3LQꢄꢀꢈꢈ  
ꢃ
ꢃ
'4ꢁꢊ 3LQꢄꢀꢈꢉ  
3LQꢄꢁꢉꢉ '4ꢈꢁ  
'4ꢁꢂ ꢃ 3LQꢄꢀꢈꢆ  
'46ꢈ 3ꢄLQꢄꢀꢈꢂ  
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'46ꢈ 3LQꢄꢀꢈꢋ  
3LQꢄꢁꢉꢋ 966  
966 ꢃ 3LQꢄꢀꢈꢇ  
'4ꢁꢇ ꢃ 3LQꢄꢀꢅꢁ  
'4ꢈꢉ ꢃ 3LQꢄꢀꢅꢅ  
966 ꢃ 3LQꢄꢀꢅꢆ  
'46ꢅ ꢃ 3LQꢄꢀꢅꢂ  
'4ꢈꢊ ꢃ 3LQꢄꢀꢅꢇ  
966 ꢃ 3LQꢄꢀꢉꢁ  
&%ꢁ ꢃ 3LQꢄꢀꢉꢅ  
'46ꢋ ꢃ 3LQꢄꢀꢉꢆ  
966 ꢃ 3LQꢄꢀꢉꢂ  
&%ꢅ ꢃ 3LQꢄꢀꢉꢇ  
9''4 ꢃ 3LQꢄꢀꢆꢁ  
9'' ꢃ 3LQꢄꢀꢆꢅ  
ꢃ
ꢃ
3LQꢄꢁꢆꢀ '4ꢈꢅ  
'4ꢁꢋ 3LQꢄꢀꢅꢀ  
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966 3LQꢄꢀꢅꢈ  
3LQꢄꢁꢆꢈ '4ꢈꢋ  
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ꢃ
3LQꢄꢁꢆꢉ 966  
'4ꢈꢆ 3LQꢄꢀꢅꢉ  
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'46ꢅ 3LQꢄꢀꢅꢊ  
3LQꢄꢁꢆꢊ 1&ꢌ'46ꢁꢈ  
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966 3LQꢄꢀꢅꢋ  
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3LQꢄꢁꢊꢀ 966  
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3LQꢄꢁꢊꢈ &%ꢆ  
&%ꢀ 3LQꢄꢀꢉꢈ  
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966 3LQꢄꢀꢉꢉ  
3LQꢄꢁꢊꢉ '0ꢋꢌ'46ꢁꢂ  
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3LQꢄꢁꢊꢊ 966  
'46ꢋ 3LQꢄꢀꢉꢊ  
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&%ꢈ 3LQꢄꢀꢉꢋ  
3LQꢄꢁꢊꢋ &%ꢂ  
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3LQꢄꢁꢂꢀ 9''4  
966 3LQꢄꢀꢆꢀ  
ꢃ
ꢃ
&.(ꢀ 3LQꢄꢀꢆꢈ  
3LQꢄꢁꢂꢈ 9''  
ꢃ
ꢃ
3LQꢄꢁꢂꢉ 1&ꢌ$ꢁꢉ  
1&ꢌ%$ꢈ 3LQꢄꢀꢆꢉ  
ꢃ 3LQꢄꢀꢆꢆ  
1&ꢌ(55B287  
ꢃ
ꢃ
9''4 3LQꢄꢀꢆꢊ  
3LQꢄꢁꢂꢊ $ꢁꢈ  
$ꢁꢁ ꢃ 3LQꢄꢀꢆꢂ  
9'' ꢃ 3LQꢄꢀꢆꢇ  
$ꢉ ꢃ 3LQꢄꢀꢊꢁ  
$ꢈ ꢃ 3LQꢄꢀꢊꢅ  
ꢃ
ꢃ
3LQꢄꢁꢂꢋ 9''  
$ꢂ 3LQꢄꢀꢆꢋ  
ꢃ
ꢃ
$ꢆ 3LQꢄꢀꢊꢀ  
3LQꢄꢁꢋꢀ $ꢊ  
3LQꢄꢁꢋꢁ ꢃ 9''4  
3LQꢄꢁꢋꢅ ꢃ $ꢁ  
ꢃ
ꢃ
3LQꢄꢁꢋꢈ $ꢅ  
9''4 3LQꢄꢀꢊꢈ  
ꢃ
ꢃ
9'' 3LQꢄꢀꢊꢉ  
3LQꢄꢁꢋꢉ 9''  
966 ꢃ 3LQꢄꢀꢊꢆ  
9'' ꢃ 3LQꢄꢀꢊꢂ  
9'' ꢃ 3LQꢄꢀꢊꢇ  
%$ꢀ ꢃ 3LQꢄꢀꢂꢁ  
:( ꢃ 3LQꢄꢀꢂꢅ  
9''4 ꢃ 3LQꢄꢀꢂꢆ  
3LQꢄꢁꢋꢆ ꢃ &.ꢀ  
3LQꢄꢁꢋꢂ ꢃ 9''  
3LQꢄꢁꢋꢇ ꢃ 9''  
3LQꢄꢁꢇꢁ ꢃ 9''4  
3LQꢄꢁꢇꢅ ꢃ 6ꢀ  
3LQꢄꢁꢇꢆ ꢃ 2'7ꢀ  
3LQꢄꢁꢇꢂ ꢃ 9''  
3LQꢄꢁꢇꢇ ꢃ '4ꢅꢊ  
3LQꢄꢈꢀꢁ ꢃ 966  
3LQꢄꢈꢀꢅ ꢃ 1&ꢌ'46ꢁꢅ  
3LQꢄꢈꢀꢆ ꢃ '4ꢅꢋ  
3LQꢄꢈꢀꢂ ꢃ 966  
3LQꢄꢈꢀꢇ ꢃ '4ꢉꢆ  
3LQꢄꢈꢁꢁ ꢃ '0ꢆꢌ'46ꢁꢉ  
3LQꢄꢈꢁꢅ ꢃ 966  
3LQꢄꢈꢁꢆ ꢃ '4ꢉꢂ  
3LQꢄꢈꢁꢂ ꢃ '4ꢆꢈ  
3LQꢄꢈꢁꢇ ꢃ 966  
3LQꢄꢈꢈꢁ ꢃ 1&  
3LQꢄꢈꢈꢅ ꢃ '0ꢊꢌ'46ꢁꢆ  
3LQꢄꢈꢈꢆ ꢃ 966  
3LQꢄꢈꢈꢂ ꢃ '4ꢆꢆ  
3LQꢄꢈꢈꢇ ꢃ '4ꢊꢀ  
3LQꢄꢈꢅꢁ ꢃ 966  
3LQꢄꢈꢅꢅ ꢃ 1&ꢌ'46ꢁꢊ  
3LQꢄꢈꢅꢆ ꢃ '4ꢊꢈ  
3LQꢄꢈꢅꢂ 966  
ꢃ
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3LQꢄꢁꢋꢊ &.ꢀ  
966 3LQꢄꢀꢊꢊ  
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ꢃ
1&ꢌ3$5B,1 3LQꢄꢀꢊꢋ  
3LQꢄꢁꢋꢋ $ꢀ  
ꢃ
ꢃ
3LQꢄꢁꢇꢀ %$ꢁ  
$ꢁꢀꢌ$3 3LQꢄꢀꢂꢀ  
ꢃ
ꢃ
9''4 3LQꢄꢀꢂꢈ  
3LQꢄꢁꢇꢈ 5$6  
ꢃ
ꢃ
3LQꢄꢁꢇꢉ 9''4  
&$6 3LQꢄꢀꢂꢉ  
ꢃ
ꢃ
1&ꢌ6ꢁ 3LQꢄꢀꢂꢊ  
3LQꢄꢁꢇꢊ 1&ꢌ$ꢁꢅ  
ꢃ 3LQꢄꢀꢂꢂ  
1&ꢌ2'7ꢁ  
ꢃ
ꢃ
3LQꢄꢁꢇꢋ 966  
9''4 3LQꢄꢀꢂꢋ  
966 ꢃ 3LQꢄꢀꢂꢇ  
'4ꢅꢅ ꢃ 3LQꢄꢀꢋꢁ  
'46ꢉ ꢃ 3LQꢄꢀꢋꢅ  
966 ꢃ 3LQꢄꢀꢋꢆ  
ꢃ
ꢃ
'4ꢅꢈ 3LQꢄꢀꢋꢀ  
3LQꢄꢈꢀꢀ '4ꢅꢂ  
ꢃ
ꢃ
3LQꢄꢈꢀꢈ '0ꢉꢌ'46ꢁꢅ  
966 3LQꢄꢀꢋꢈ  
ꢃ
ꢃ
'46ꢉ 3LQꢄꢀꢋꢉ  
3LQꢄꢈꢀꢉ 966  
ꢃ
ꢃ
3LQꢄꢈꢀꢊ '4ꢅꢇ  
'4ꢅꢉ 3LQꢄꢀꢋꢊ  
'4ꢅꢆ ꢃ 3LQꢄꢀꢋꢂ  
'4ꢉꢀ ꢃ 3LQꢄꢀꢋꢇ  
966 ꢃ 3LQꢄꢀꢇꢁ  
'46ꢆ ꢃ 3LQꢄꢀꢇꢅ  
'4ꢉꢈ ꢃ 3LQꢄꢀꢇꢆ  
966 ꢃ 3LQꢄꢀꢇꢂ  
'4ꢉꢇ ꢃ 3LQꢄꢀꢇꢇ  
6$ꢈ ꢃ 3LQꢄꢁꢀꢁ  
966 ꢃ 3LQꢄꢁꢀꢅ  
'46ꢊ ꢃ 3LQꢄꢁꢀꢆ  
'4ꢆꢀ ꢃ 3LQꢄꢁꢀꢂ  
966 ꢃ 3LQꢄꢁꢀꢇ  
'4ꢆꢂ ꢃ 3LQꢄꢁꢁꢁ  
'46ꢂ ꢃ 3LQꢄꢁꢁꢅ  
966 ꢃ 3LQꢄꢁꢁꢆ  
'4ꢆꢇ ꢃ 3LQꢄꢁꢁꢂ  
6'$ ꢃ 3LQꢄꢁꢁꢇ  
ꢃ
ꢃ
966 3LQꢄꢀꢋꢋ  
3LQꢄꢈꢀꢋ '4ꢉꢉ  
ꢃ
ꢃ
3LQꢄꢈꢁꢀ 966  
'4ꢉꢁ 3LQꢄꢀꢇꢀ  
ꢃ
ꢃ
'46ꢆ 3LQꢄꢀꢇꢈ  
3LQꢄꢈꢁꢈ 1&ꢌ'46ꢁꢉ  
ꢃ
ꢃ
3LQꢄꢈꢁꢉ '4ꢉꢊ  
966 3LQꢄꢀꢇꢉ  
ꢃ
ꢃ
'4ꢉꢅ 3LQꢄꢀꢇꢊ  
3LQꢄꢈꢁꢊ 966  
ꢃ
ꢃ
3LQꢄꢈꢁꢋ '4ꢆꢅ  
'4ꢉꢋ 3LQꢄꢀꢇꢋ  
ꢃ
ꢃ
966 3LQꢄꢁꢀꢀ  
3LQꢄꢈꢈꢀ 1&  
ꢃ
ꢃ
3LQꢄꢈꢈꢈ 966  
1& 3LQꢄꢁꢀꢈ  
ꢃ
ꢃ
'46ꢊ 3LQꢄꢁꢀꢉ  
3LQꢄꢈꢈꢉ 1&ꢌ'46ꢁꢆ  
ꢃ
ꢃ
3LQꢄꢈꢈꢊ '4ꢆꢉ  
966 3LQꢄꢁꢀꢊ  
ꢃ
ꢃ
'4ꢆꢁ 3LQꢄꢁꢀꢋ  
3LQꢄꢈꢈꢋ 966  
ꢃ
ꢃ
3LQꢄꢈꢅꢀ '4ꢊꢁ  
'4ꢆꢊ 3LQꢄꢁꢁꢀ  
ꢃ
ꢃ
966 3LQꢄꢁꢁꢈ  
3LQꢄꢈꢅꢈ '0ꢂꢌ'46ꢁꢊ  
ꢃ
ꢃ
3LQꢄꢈꢅꢉ 966  
'46ꢂ 3LQꢄꢁꢁꢉ  
ꢃ
ꢃ
'4ꢆꢋ 3LQꢄꢁꢁꢊ  
3LQꢄꢈꢅꢊ '4ꢊꢅ  
ꢃ
966 3LQꢄꢁꢁꢋ  
3LQꢄꢈꢅꢋ 9''63'  
3LQꢄꢈꢉꢀ 6$ꢁ  
3LQꢄꢈꢅꢇ 6$ꢀ  
ꢃ
6&/ 3LQꢄꢁꢈꢀ  
0337ꢀꢁꢂꢀ  
Figure 1  
Pin Configuration for RDIMM (240 pins)  
Data Sheet  
16  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsBlock Diagram  
2.2  
Block Diagram  
6$$ꢋ30$  
6$$ꢉ6$$1  
62%&  
6$$ꢍ 30$ %%02/- %ꢀ  
6$$ꢉ6$$1ꢍ 3$2!-S $ꢀ ꢊ $ꢂ  
62%&ꢍ 3$2!-S $ꢀ ꢊ $ꢂ  
633ꢍ 3$2!-S $ꢀ ꢊ $ꢂ  
#+ꢀ  
#+ꢀ  
0,,  
0#+ꢀꢊ0#+ꢅꢋ 0#+ꢂꢋ 0#+ꢌ  
#+ꢍ 3$2!-S $ꢀꢊ$ꢂ  
#+ꢍ 3$2!-S $ꢀꢊ$ꢂ  
#+ꢍ 2EGISTER  
0#+ꢀꢊ0#+ꢅꢋ 0#+ꢂꢋ 0#+ꢌ  
0#+ꢆ  
0#+ꢆ  
2%3%4  
/%  
#+ꢍ 2EGISTER  
633  
3ꢀ  
23ꢀ  
#3ꢍ 3$2!-S $ꢀꢊ$ꢂ  
"!ꢀꢊ"!Nꢍ 3$2!-S $ꢀꢊ$ꢂ  
ꢁꢍꢁ  
"!ꢀ ꢊ "!N  
!ꢀ ꢊ !N  
2!3  
2"!ꢀꢊ2"!N  
2!ꢀꢊ2!N  
22!3  
2
%
'
)
3
4
%
2
!ꢀꢊ!Nꢍ 3$2!-S $ꢀꢊ$ꢂ  
2!3ꢍ 3$2!-S $ꢀꢊ$ꢂ  
#!3ꢍ 3$2!-S $ꢀꢊ$ꢂ  
7%ꢍ 3$2!-S $ꢀꢊ$ꢂ  
#+%ꢍ 3$2!-S $ꢀꢊ$ꢂ  
/$4ꢍ 3$2!-S $ꢀꢊ$ꢂ  
#!3  
7%  
#+%ꢀ  
/$4ꢀ  
2#!3  
27%  
2#+%ꢀ  
2/$4ꢀ  
2EGISTER  
%ꢀ  
633  
633  
3#,  
3$!  
!ꢀ  
3#,  
3$!  
3!ꢀ  
3!ꢁ  
3!ꢃ  
633  
#ꢀ  
#ꢁ  
0!2?).  
0!2?).  
!ꢁ  
0#+ꢆ  
0#+ꢆ  
2%3%4  
ꢁꢀꢀ+ OHMS  
00/  
1%22  
!ꢃ  
%RR?/UT  
70  
23ꢀ  
$ꢀ  
$ꢄ  
$ꢇ  
$ꢈ  
$ꢅ  
$ꢆ  
$ꢂ  
#3  
#3  
#3  
$13ꢀ  
$13ꢀ  
$-ꢀꢉ$13ꢌ  
$13ꢌ  
$1ꢀ  
$13  
$13  
$13ꢄ  
$13ꢄ  
$13  
$13ꢅ  
$13ꢅ  
$13  
$13  
$13  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$-ꢄꢉ$13ꢁꢃ  
$13ꢁꢃ  
$1ꢃꢇ  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$-ꢅꢉ$13ꢁꢈ  
$13ꢁꢈ  
$1ꢇꢂ  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$1ꢁ  
)ꢉ/ ꢁ  
$1ꢃꢈ  
)ꢉ/ ꢁ  
$1ꢇꢌ  
)ꢉ/ ꢁ  
$1ꢃ  
)ꢉ/ ꢃ  
$1ꢃꢅ  
)ꢉ/ ꢃ  
$1ꢈꢀ  
)ꢉ/ ꢃ  
$1ꢄ  
)ꢉ/ ꢄ  
$1ꢃꢆ  
)ꢉ/ ꢄ  
$1ꢈꢁ  
)ꢉ/ ꢄ  
$1ꢇ  
)ꢉ/ ꢇ  
$1ꢃꢂ  
)ꢉ/ ꢇ  
$1ꢈꢃ  
)ꢉ/ ꢇ  
$1ꢈ  
)ꢉ/ ꢈ  
$1ꢃꢌ  
)ꢉ/ ꢈ  
$1ꢈꢄ  
)ꢉ/ ꢈ  
$1ꢅ  
)ꢉ/ ꢅ  
$1ꢄꢀ  
)ꢉ/ ꢅ  
$1ꢈꢇ  
)ꢉ/ ꢅ  
$1ꢆ  
)ꢉ/ ꢆ  
$1ꢄꢁ  
)ꢉ/ ꢆ  
$1ꢈꢈ  
)ꢉ/ ꢆ  
$ꢁ  
#3  
#3  
$13  
#3  
$13  
$13ꢁ  
$13ꢁ  
$13  
$13  
$13ꢇ  
$13ꢇ  
$13ꢆ  
$13ꢆ  
$13  
$13  
$-ꢁꢉ$13ꢁꢀ  
$13ꢁꢀ  
$1ꢂ  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$-ꢇꢉ$13ꢁꢄ  
$13ꢁꢄ  
$1ꢄꢃ  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$-ꢆꢉ$13ꢁꢅ  
$13ꢁꢅ  
$1ꢈꢅ  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$1ꢌ  
)ꢉ/ ꢁ  
$1ꢄꢄ  
)ꢉ/ ꢁ  
$1ꢈꢆ  
)ꢉ/ ꢁ  
$1ꢁꢀ  
)ꢉ/ ꢃ  
$1ꢄꢇ  
)ꢉ/ ꢃ  
$1ꢈꢂ  
)ꢉ/ ꢃ  
$1ꢁꢁ  
)ꢉ/ ꢄ  
$1ꢄꢈ  
)ꢉ/ ꢄ  
$1ꢈꢌ  
)ꢉ/ ꢄ  
$1ꢁꢃ  
)ꢉ/ ꢇ  
$1ꢄꢅ  
)ꢉ/ ꢇ  
$1ꢅꢀ  
)ꢉ/ ꢇ  
$1ꢁꢄ  
)ꢉ/ ꢈ  
$1ꢄꢆ  
)ꢉ/ ꢈ  
$1ꢅꢁ  
)ꢉ/ ꢈ  
$1ꢁꢇ  
)ꢉ/ ꢅ  
$1ꢄꢂ  
)ꢉ/ ꢅ  
$1ꢅꢃ  
)ꢉ/ ꢅ  
$1ꢁꢈ  
)ꢉ/ ꢆ  
$1ꢄꢌ  
)ꢉ/ ꢆ  
$1ꢅꢄ  
)ꢉ/ ꢆ  
$ꢃ  
#3  
$13  
#3  
$13  
#3  
$13  
$13ꢈ  
$13ꢈ  
$13ꢂ  
$13ꢂ  
$-ꢂꢉ$13ꢁꢆ  
$13ꢁꢆ  
#"ꢀ  
$13ꢃ  
$13ꢃ  
$13  
$13  
$13  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$-ꢈꢉ$13ꢁꢇ  
$13ꢁꢇ  
$1ꢇꢀ  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$-ꢉ2$13  
.5ꢉ2$13  
)ꢉ/ ꢀ  
$-ꢃꢉ$13ꢁꢁ  
$13ꢁꢁ  
$1ꢁꢅ  
)ꢉ/ ꢁ  
$1ꢇꢁ  
)ꢉ/ ꢁ  
#"ꢁ  
)ꢉ/ ꢁ  
$1ꢁꢆ  
)ꢉ/ ꢃ  
$1ꢇꢃ  
)ꢉ/ ꢃ  
#"ꢃ  
)ꢉ/ ꢃ  
$1ꢁꢂ  
)ꢉ/ ꢄ  
$1ꢇꢄ  
)ꢉ/ ꢄ  
#"ꢄ  
)ꢉ/ ꢄ  
$1ꢁꢌ  
)ꢉ/ ꢇ  
$1ꢇꢇ  
)ꢉ/ ꢇ  
#"ꢇ  
)ꢉ/ ꢇ  
$1ꢃꢀ  
)ꢉ/ ꢈ  
$1ꢇꢈ  
)ꢉ/ ꢈ  
#"ꢈ  
)ꢉ/ ꢈ  
$1ꢃꢁ  
)ꢉ/ ꢅ  
$1ꢇꢅ  
)ꢉ/ ꢅ  
#"ꢅ  
)ꢉ/ ꢅ  
$1ꢃꢃ  
)ꢉ/ ꢆ  
$1ꢇꢆ  
)ꢉ/ ꢆ  
#"ꢆ  
)ꢉ/ ꢆ  
$1ꢃꢄ  
-0"4ꢀꢁꢂꢀ  
Figure 2  
Notes  
Block Diagram RDIMM (x72, 1Rank, x8)  
1. Unless otherwise noted, resistors are 22 Ω ± 5 %  
2. S0 connects to DCS and VDD connects to CSR on the register.  
Data Sheet  
17  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
'46ꢁꢊ  
'4ꢆꢊ  
'4ꢆꢂ  
'4ꢆꢋ  
'4ꢆꢇ  
'4ꢊꢀ  
'4ꢊꢁ  
'4ꢊꢈ  
'4ꢊꢅ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ18ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ1  
8ꢌ5'46ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsBlock Diagram  
9''ꢎ63'  
''ꢌ9''4  
95()  
9
9
9
9
''ꢍꢄ63'ꢄ((3520ꢄ(ꢀ  
''ꢌ9''4ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
5()ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
66ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
&.ꢀ  
&.ꢀ  
ꢄꢄꢄ3//ꢄ  
3&.ꢀꢃ3&.ꢊꢎꢄ3&.ꢋꢎꢄ3&.ꢇ  
3&.ꢀꢃ3&.ꢊꢎꢄ3&.ꢋꢎꢄ3&.ꢇ  
3&.ꢂ  
&.ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
&.ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
&.ꢍꢄ5HJLVWHU  
9
ꢄ
5(6(7  
ꢄ2(  
3&.ꢂ  
&.ꢍꢄ5HJLVWHU  
966  
6ꢀ  
6ꢁ  
56ꢀ  
&6ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢋ  
&6ꢍꢄ6'5$0Vꢄ'ꢇꢃ'ꢁꢂ  
ꢁꢍꢈ  
56ꢁ  
%$ꢀꢄꢃꢄ%$Q  
$ꢀꢄꢃꢄ$Q  
5$6  
5
(
*
,
5%$ꢀꢃ5%$Q  
5$ꢀꢃ5$Q  
55$6  
%$ꢀꢃ%$Qꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
$ꢀꢃ$Qꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
5$6ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
&$6ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
:(ꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢁꢂ  
&.(ꢀꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢋ  
&.(ꢁꢍꢄ6'5$0Vꢄ'ꢇꢃ'ꢁꢂ  
2'7ꢀꢍꢄ6'5$0Vꢄ'ꢀꢃ'ꢋ  
2'7ꢁꢍꢄ6'5$0Vꢄ'ꢇꢃ'ꢁꢂ  
'ꢉ  
'ꢁꢅ  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
'46ꢉ  
'46ꢉ  
ꢄ'46  
&$6  
5&$6  
6
7
(
5
ꢄ'46ꢄ  
ꢄ'46ꢄ  
:(  
5:(  
'0ꢉꢌ'46ꢁꢅ  
'46ꢁꢅ  
'4ꢅꢈ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
&.(ꢀ  
&.(ꢁ  
2'7ꢀ  
2'7ꢁ  
3&.ꢂ  
3&.ꢂ  
5(6(7  
5&.(ꢀ  
5&.(ꢁ  
52'7ꢀ  
52'7ꢁ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
'4ꢅꢅ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
'4ꢅꢉ  
'4ꢅꢆ  
ꢄ,ꢌ2ꢄꢅ  
'4ꢅꢊ  
ꢄ,ꢌ2ꢄꢉ  
'4ꢅꢂ  
ꢄ,ꢌ2ꢄꢆ  
'4ꢅꢋ  
ꢄ,ꢌ2ꢄꢊ  
56ꢀ  
56ꢀ  
'4ꢅꢇ  
ꢄ,ꢌ2ꢄꢂ  
'ꢀ  
'ꢇ  
'ꢆ  
'ꢁꢉ  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄ'46  
'46ꢆ  
'46ꢆ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
'0ꢆꢌ'46ꢁꢉ  
'46ꢁꢉ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
'4ꢉꢀ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
'4ꢉꢁ  
'4ꢉꢈ  
'4ꢉꢅ  
'4ꢉꢉ  
'4ꢉꢆ  
'4ꢉꢊ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
(ꢀ  
ꢄ,ꢌ2ꢄꢈ  
6&/  
ꢄ6&/ꢄꢄꢄꢄꢄ  
ꢄ6'$ꢄ  
ꢄ$ꢀꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ$ꢁ  
ꢄ,ꢌ2ꢄꢅ  
6'$  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
6$ꢀ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
6$ꢁ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
6$ꢈ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ$ꢈꢄꢄ  
ꢄ,ꢌ2ꢄꢂ  
ꢉꢂ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ:3ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
966  
'ꢁ  
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ꢄ'46  
'ꢊ  
'ꢁꢆ  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
'46ꢊ  
'46ꢊ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
'0ꢊꢌ'46ꢁꢆ  
'46ꢁꢆ  
'4ꢉꢋ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
5HJLVWHUꢄ$  
3$5B,1  
966  
9''  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ&ꢀꢄꢄꢄꢄꢄ  
ꢄ&ꢁ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
'4ꢉꢇ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
'4ꢆꢀ  
ꢄ3$5B,1  
ꢄ,ꢌ2ꢄꢅ  
'4ꢆꢁ  
ꢄ,ꢌ2ꢄꢅ  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢉ  
'4ꢆꢈ  
'4ꢆꢅ  
'4ꢆꢉ  
'4ꢆꢆ  
ꢄ,ꢌ2ꢄꢉ  
332  
4(55  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢂ  
'ꢈ  
'ꢁꢁ  
'ꢂ  
'ꢁꢊ  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
5HJLVWHUꢄ%  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
9''  
9''  
ꢄ&ꢀꢄꢄꢄꢄꢄ  
ꢄ&ꢁ  
'46ꢂ  
'46ꢂ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ3$5B,1  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
'0ꢂꢌ'46ꢁꢊ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ  
332  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
4(55  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
(UUB2XW  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢂ  
'ꢅ  
'ꢁꢈ  
'ꢋ  
'ꢁꢂ  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
ꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄꢄ&6ꢄꢄꢄꢄꢄ  
ꢄ'46  
'46ꢋ  
'46ꢋ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'46ꢄ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
'0ꢋꢌ'46ꢁꢂ  
'46ꢁꢂ  
&%ꢀ  
ꢄ'0ꢌ5'46  
ꢄ'0ꢌ5'46  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
ꢄ,ꢌ2ꢄꢀ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
&%ꢁ  
ꢄ,ꢌ2ꢄꢁꢄꢄꢄꢄꢄꢄꢄ  
ꢄ,ꢌ2ꢄꢈ  
&%ꢈ  
ꢄ,ꢌ2ꢄꢅ  
&%ꢅ  
ꢄ,ꢌ2ꢄꢅ  
ꢄ,ꢌ2ꢄꢉ  
&%ꢉ  
ꢄ,ꢌ2ꢄꢉ  
ꢄ,ꢌ2ꢄꢆ  
&%ꢆ  
ꢄ,ꢌ2ꢄꢆ  
ꢄ,ꢌ2ꢄꢊ  
&%ꢊ  
ꢄ,ꢌ2ꢄꢊ  
ꢄ,ꢌ2ꢄꢂ  
&%ꢂ  
ꢄ,ꢌ2ꢄꢂ  
03%7ꢀꢁꢇꢀ  
Figure 3  
Notes  
Block Diagram RDIMM (x72, 2Ranks, x8)  
1. Unless otherwise noted, resistors are 22 Ω ± 5 %  
2. RS0 and RS1 alternate between the back and front sides of the DIMM.  
Data Sheet  
18  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin Configuration and Block DiagramsBlock Diagram  
#+ꢀ  
#+ꢀ  
0,,  
0#+ꢀꢊ0#+ꢅꢋ 0#+ꢂꢋ 0#+ꢌ  
0#+ꢀꢊ0#+ꢅꢋ 0#+ꢂꢋ 0#+ꢌ  
0#+ꢆ  
#+ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
-0"4ꢀꢃꢀꢁ  
6$$ꢍ 30$ %%02/- %ꢀ  
#+ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
#+ꢍ 2EGISTER  
6$$ꢋ30$  
6$$ꢉ6$$1  
62%&  
2%3%4  
/%  
0#+ꢆ  
#+ꢍ 2EGISTER  
6$$ꢉ6$$1ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
62%&ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
633ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
%ꢀ  
3ꢀ  
"!ꢀ ꢊ "!N  
!ꢀ ꢊ !N  
2!3  
23ꢀ  
#3ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
"!ꢀꢊ"!Nꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
ꢁꢍꢃ  
2"!ꢀꢊ2"!N  
2!ꢀꢊ2!N  
22!3  
633  
2
%
'
)
3
4
%
2
!ꢀꢊ!Nꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
2!3ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
#!3ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
7%ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
#+%ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
/$4ꢍ 3$2!-S $ꢀꢊ$ꢁꢆ  
#!3  
2#!3  
3#,  
3$!  
!ꢀ  
3#,  
3$!  
3!ꢀ  
3!ꢁ  
3!ꢃ  
633  
7%  
27%  
#+%ꢀ  
2#+%ꢀ  
2/$4ꢀ  
/$4ꢀ  
0#+ꢆ  
!ꢁ  
!ꢃ  
70  
0#+ꢆ  
2%3%4  
23ꢀ  
$ꢀ  
$ꢅ  
$ꢁꢃ  
$ꢁꢄ  
$ꢁꢇ  
$ꢁꢈ  
$ꢁꢅ  
$ꢁꢆ  
#3  
#3  
#3  
#3  
#3  
#3  
#3  
#3  
#3  
#3  
#3  
#3  
#3  
$13ꢀ  
$13ꢀ  
$1ꢀ  
$1ꢁ  
$1ꢃ  
$1ꢄ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢅ  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢁꢃ  
$13ꢁꢃ  
$1ꢃꢂ  
$1ꢃꢌ  
$1ꢄꢀ  
$1ꢄꢁ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
2EGISTER !  
0!2?).  
633  
6$$  
$13ꢅ  
$1ꢇꢂ  
$1ꢇꢌ  
$1ꢈꢀ  
$1ꢈꢁ  
633  
#ꢀ  
#ꢁ  
0!2?).  
00/  
1%22  
$ꢁ  
$ꢃ  
$ꢄ  
$ꢇ  
$ꢈ  
$ꢆ  
#3  
#3  
#3  
#3  
#3  
$13ꢁ  
$13ꢁ  
$1ꢂ  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢆ  
$13ꢆ  
$1ꢈꢅ  
$1ꢈꢆ  
$1ꢈꢂ  
$1ꢈꢌ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢁꢄ  
$13ꢁꢄ  
$1ꢄꢅ  
$1ꢄꢆ  
$1ꢄꢂ  
$1ꢄꢌ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
2EGISTER "  
6$$  
6$$  
#ꢀ  
#ꢁ  
0!2?).  
$1ꢌ  
$1ꢁꢀ  
$1ꢁꢁ  
633  
00/  
1%22  
$ꢂ  
%RR?/UT  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢂ  
$13ꢂ  
#"ꢀ  
#"ꢁ  
#"ꢃ  
#"ꢄ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢁꢇ  
$13ꢁꢇ  
$1ꢇꢇ  
$1ꢇꢈ  
$1ꢇꢅ  
$1ꢇꢆ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢃ  
$13ꢃ  
$1ꢁꢅ  
$1ꢁꢆ  
$1ꢁꢂ  
$1ꢁꢌ  
633  
$ꢌ  
$13ꢄ  
$13ꢄ  
$1ꢃꢇ  
$1ꢃꢈ  
$1ꢃꢅ  
$1ꢃꢆ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢌ  
$13ꢌ  
$1ꢇ  
$1ꢈ  
$1ꢅ  
$1ꢆ  
633  
$13  
$13  
)ꢉ/ ꢀ  
)ꢉ/ ꢁ  
)ꢉ/ ꢃ  
)ꢉ/ ꢄ  
$-  
$13ꢁꢈ  
$13ꢁꢈ  
$1ꢈꢃ  
$1ꢈꢄ  
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Figure 4  
Block Diagram RDIMM (x72, 1Rank, x4)  
Notes  
1. Unless otherwise noted, resistors are 22 Ω ± 5 %  
2. S0 connects to DCS of register1 and CSR of register2.  
3. CSR of register1 and DCS of register2 connects to VDD.  
4. RESET, PCK7 and PCK7 connect to both registers.  
Data Sheet  
19  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAbsolute Maximum Ratings  
3
Electrical Characteristics  
3.1  
Absolute Maximum Ratings  
Caution is needed not to exceed abolute maximum ratings of the DRAM device listed in Table 10 at any time.  
Table 10  
Absolute Maximum Ratings  
Parameter  
Symbol  
Values  
Min.  
–0.5  
–1.0  
–0.5  
5
Unit  
Max.  
2.3  
2.3  
2.3  
95  
Voltage on any pins relative to VSS  
Voltage on VDD relative to VSS  
VIN, VOUT  
VDD  
V
V
V
%
Voltage on VDDQ relative to VSS  
Storage Humidity (without condensation)  
VDDQ  
HSTG  
Attention: Stresses above the max. values listed here may cause permanent damage to the device.  
Exposure to absolute maximum rating conditions for extended periods may affect device  
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may  
cause irreversible damage to the integrated circuit.  
3.2  
DC Operating Conditions  
Table 11  
Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
0
Unit  
Notes  
Max.  
+65  
Operating temperature (ambient)  
DRAM Case Temperature  
TOPR  
TCASE  
TSTG  
°C  
°C  
°C  
kPa  
%
1)2)3)4)  
5)  
0
+95  
Storage Temperature  
– 50  
+69  
10  
+100  
+105  
90  
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
PBar  
HOPR  
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported  
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs  
4)When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh  
has to be enabled by setting EMR(2) bit A7 to 1. When the High Temperature Self Refresh is enabled there is an  
increase of IDD6 by approximately 50%.  
5) Up to 3000 m.  
Data Sheet  
20  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsDC Operating Conditions  
Table 12  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Notes  
Typ.  
Max.  
1.9  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
VDD  
1.7  
1.8  
V
1)  
2)  
VDDQ  
VREF  
1.7  
1.8  
1.9  
V
0.49 × VDDQ  
1.7  
0.5 × VDDQ  
0.51 × VDDQ  
3.6  
V
VDDSPD  
VIH(DC)  
VIL (DC  
IL  
—
—
—
—
V
DC Input Logic High  
V
REF + 0.125  
V
V
5
DDQ + 0.3  
V
DC Input Logic Low  
)
– 0.30  
– 5  
REF – 0.125  
V
3)  
In / Output Leakage Current  
µA  
1) Under all conditions, VDDQ must be less than or equal to VDD  
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ  
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
Data Sheet  
21  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
3.3  
AC Characteristics  
3.3.1  
Speed Grades Definitions  
Table 13  
Speed Grade Definition Speed Bins for DDR2–667D  
Speed Grade  
DDR2–667  
Unit  
Notes  
IFX Sort Name  
CAS-RCD-RP latencies  
Parameter  
–3S  
5–5–5  
Min.  
5
tCK  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Symbol  
tCK  
Max.  
8
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
3.75  
3
8
tCK  
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
45  
70000  
—
60  
15  
—
15  
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are  
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,  
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
4) The output timing reference voltage level is VTT.  
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is  
equal to 9 x tREFI  
.
Data Sheet  
22  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
Table 14  
Speed Grade Definition Speed Bins for DDR2–533C  
Speed Grade  
DDR2–533  
–3.7  
Unit  
Note  
IFX Sort Name  
CAS-RCD-RP latencies  
Parameter  
4–4–4  
tCK  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Symbol  
tCK  
Min.  
5
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
8
tCK  
3.75  
3.75  
45  
8
tCK  
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
70000  
—
60  
15  
—
15  
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are  
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,  
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
4) The output timing reference voltage level is VTT.  
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is  
equal to 9 x tREFI  
.
Table 15  
Speed Grade Definition Speed Bins for DDR2-400B  
Speed Grade  
DDR2–400B  
–5  
Unit  
Note  
IFX Sort Name  
CAS-RCD-RP latencies  
Parameter  
3–3–3  
tCK  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Symbol  
tCK  
Min.  
5
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
8
tCK  
5
8
tCK  
5
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
40  
55  
15  
15  
70000  
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are  
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,  
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
4) The output timing reference voltage level is VTT.  
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is  
equal to 9 x tREFI  
.
Data Sheet  
23  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
3.3.2  
AC Timing Parameters  
Table 16  
Timing Parameter by Speed Grade - DDR2-667  
Parameter  
Symbol  
DDR2-667  
Min.  
Unit Note  
1)2)3)4)5)6)  
Max.  
7)  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
tCCD  
tCH  
tCKE  
tCL  
tDAL  
tDELAY  
–450  
2
+450  
—
ps  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
0.45  
3
0.55  
—
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
—
Auto-Precharge write recovery + precharge time  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tIS + tCK + tIH ––  
DQ and DM input hold time (differential data strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDH(base)  
tDIPW  
175  
––  
ps  
tCK  
ps  
tCK  
ps  
0.35  
–400  
0.35  
240  
—
tDQSCK  
tDQSL,H  
tDQSQ  
tDQSS  
tDS(base)  
tDSH  
+400  
—
DQS input low (high) pulse width (write cycle)  
DQS-DQ skew (for DQS & associated DQ signals)  
Write command to 1st DQS latching transition  
DQ and DM input setup time (differential data strobe)  
DQS falling edge hold time from CK (write cycle)  
DQS falling edge to CK setup time (write cycle)  
Clock half period  
—
– 0.25  
100  
+ 0.25 tCK  
—
—
—
ps  
0.2  
tCK  
tCK  
tDSS  
0.2  
tHP  
MIN. (tCL, tCH)  
— tAC.MAX ps  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tIH(base)  
tIPW  
275  
—
—
ps  
Address and control input pulse width  
(each input)  
0.6  
tCK  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
200  
—
ps  
2 ξ tAC.MIN  
tAC.MAX ps  
tAC.MAX ps  
tAC.MIN  
2
0
—
tCK  
tOIT  
12  
—
ns  
Data output hold time from DQS  
Data hold skew factor  
tQH  
tHP – tQHS  
tQHS  
340  
—
—
ps  
µs  
µs  
ns  
ns  
tCK  
tCK  
ns  
ns  
8)  
9)  
Average periodic refresh Interval  
tREFI  
7.8  
3.9  
—
—
Auto-Refresh to Active/Auto-Refresh command period tRFC  
75  
Precharge-All (4 banks) command period  
Read preamble  
tRP  
t
RP + 1tCK  
—
tRPRE  
tRPST  
tRRD  
0.9  
0.40  
7.5  
10  
1.1  
0.60  
—
Read postamble  
10)  
11)  
Active bank A to Active bank B command period  
—
Data Sheet  
24  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
Table 16  
Timing Parameter by Speed Grade - DDR2-667  
Symbol  
Parameter  
DDR2-667  
Min.  
Unit Note  
1)2)3)4)5)6)  
Max.  
7)  
Internal Read to Precharge command delay  
Write preamble  
tRTP  
7.5  
—
ns  
tWPRE  
tWPST  
tWR  
0.35  
0.40  
15  
—
tCK  
tCK  
ns  
Write postamble  
0.60  
—
Write recovery time for write without Auto-Precharge  
Write recovery time for write with Auto-Precharge  
Internal Write to Read command delay  
WR  
t
WR/tCK  
tCK  
ns  
tWTR  
tXARD  
7.5  
2
—
—
Exit power down to any valid command  
(other than NOP or Deselect)  
tCK  
Exit active power-down mode to Read command (slow tXARDS  
exit, lower power)  
7 – AL  
2
—
—
tCK  
tCK  
Exit precharge power-down to any valid command (other tXP  
than NOP or Deselect)  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
t
RFC +10  
—
—
ns  
200  
tCK  
1) For details and notes see the relevant INFINEON component data sheet  
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)  
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be  
powered down and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.  
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
7) The output timing reference voltage level is VTT.  
8) 0 ≤ TCASE ≤ 85 °C  
9) 85 °C < TCASE ≤ 95 °C  
10) x4 & x8  
11) x16  
Data Sheet  
25  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
Table 17  
Timing Parameter by Speed Grade - DDR2-533  
Symbol  
Parameter  
DDR2–533  
Min.  
Unit Note1)2)  
3)4)5)6)7)  
Max.  
+500  
—
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–500  
2
ps  
tCCD  
tCH  
tCKE  
tCL  
tDAL  
tDELAY  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
0.45  
0.55  
—
CKE minimum high and low pulse width  
CK, CK low-level width  
3
0.45  
0.55  
—
Auto-Precharge write recovery + precharge time  
WR + tRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tIS + tCK + tIH ––  
DQ and DM input hold time (differential data  
strobe)  
tDH(base)  
225  
–25  
––  
—
ps  
ps  
DQ and DM input hold time (single ended data  
strobe)  
tDH1(base)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
DQS input low (high) pulse width (write cycle)  
tDIPW  
0.35  
–450  
0.35  
—
—
tCK  
ps  
tCK  
ps  
tCK  
ps  
tDQSCK  
tDQSL,H  
+450  
—
DQS-DQ skew (for DQS & associated DQ signals) tDQSQ  
300  
+0.25  
—
Write command to 1st DQS latching transition  
tDQSS  
–0.25  
100  
DQ and DM input setup time (differential data  
strobe)  
tDS(base)  
DQ and DM input setup time (single ended data  
strobe)  
t
DS1(base)  
–25  
—
ps  
DQS falling edge hold time from CK (write cycle) tDSH  
0.2  
—
—
tCK  
tCK  
DQS falling edge to CK setup time (write cycle)  
Clock half period  
tDSS  
0.2  
tHP  
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
—
tAC.MAX  
ps  
ps  
tCK  
tIH(base)  
tIPW  
375  
0.6  
—
Address and control input pulse width  
(each input)  
—
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
250  
—
ps  
ps  
ps  
tCK  
ns  
2 ° tAC.MIN  
tAC.MAX  
tAC.MAX  
—
tAC.MIN  
2
0
tOIT  
12  
Data output hold time from DQS  
Data hold skew factor  
tQH  
t
HP – tQHS  
—
tQHS  
—
—
—
75  
400  
7.8  
ps  
8)  
Average periodic refresh Interval  
tREFI  
µs  
9)  
3.9  
µs  
Auto-Refresh to Active/Auto-Refresh command  
period  
tRFC  
tRP  
—
ns  
Precharge-All (4 banks) command period  
t
RP + 1tCK  
—
ns  
Data Sheet  
26  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
Table 17  
Timing Parameter by Speed Grade - DDR2-533 (cont’d)  
Parameter  
Symbol  
DDR2–533  
Min.  
0.9  
Unit Note1)2)  
3)4)5)6)7)  
Max.  
1.1  
0.60  
—
Read preamble  
Read postamble  
tRPRE  
tRPST  
tCK  
tCK  
0.40  
7.5  
10)  
Active bank A to Active bank B command period tRRD  
ns  
1)11)  
10  
—
ns  
Internal Read to Precharge command delay  
Write preamble  
tRTP  
7.5  
—
ns  
tCK  
tCK  
ns  
tWPRE  
tWPST  
tWR  
0.35xtCK  
0.40  
15  
—
Write postamble  
0.60  
—
Write recovery time for write without Auto-  
Precharge  
Write recovery time for write with Auto-Precharge WR  
t
WR/tCK  
tCK  
ns  
Internal Write to Read command delay  
tWTR  
7.5  
2
—
—
Exit power down to any valid command  
(other than NOP or Deselect)  
tXARD  
tCK  
Exit active power-down mode to Read command tXARDS  
(slow exit, lower power)  
6 – AL  
2
—
—
tCK  
tCK  
Exit precharge power-down to any valid command tXP  
(other than NOP or Deselect)  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
t
RFC +10  
—
—
ns  
200  
tCK  
1) For details and notes see the relevant INFINEON component data sheet  
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)  
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be  
powered down and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,  
RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
7) The output timing reference voltage level is VTT.  
8) 0 ≤ TCASE ≤ 85 °C  
9) 85 < TCASE ≤ 95 °C  
10) x4 & x8  
11) x16  
Data Sheet  
27  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
Table 18  
Timing Parameter by Speed Grade - DDR2-400  
Symbol  
Parameter  
DDR2-400  
Min.  
Unit Note  
1)2)3)4)5)6)7)  
Max.  
+600  
—
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
tCCD  
tCH  
tCKE  
tCL  
tDAL  
tDELAY  
–600  
2
ps  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
0.45  
0.55  
—
CKE minimum high and low pulse width  
CK, CK low-level width  
3
0.45  
0.55  
—
Auto-Precharge write recovery + precharge time  
WR + tRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tIS + tCK + tIH ––  
DQ and DM input hold time (differential data strobe)  
DQ and DM input hold time (single-ended strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDH(base)  
275  
––  
ps  
ps  
tCK  
ps  
tCK  
ps  
tCK  
ps  
ps  
tCK  
tCK  
t
DH1(base) 25  
––  
tDIPW  
0.35  
–500  
0.35  
—
—
tDQSCK  
tDQSL,H  
tDQSQ  
tDQSS  
tDS(base)  
+500  
—
DQS input low (high) pulse width (write cycle)  
DQS-DQ skew (for DQS & associated DQ signals)  
Write command to 1st DQS latching transition  
DQ and DM input setup time (differential data strobe)  
DQ and DM input setup time (single-ended strobe)  
DQS falling edge hold time from CK (write cycle)  
DQS falling edge to CK setup time (write cycle)  
Clock half period  
350  
+0.25  
—
–0.25  
150  
t
DS1(base) 25  
—
tDSH  
tDSS  
tHP  
0.2  
—
0.2  
—
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
—
tAC.MAX ps  
tIH(base)  
tIPW  
475  
0.6  
—
—
ps  
Address and control input pulse width  
(each input)  
tCK  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
350  
—
ps  
2 ξ tAC.MIN  
tAC.MAX ps  
tAC.MAX ps  
tAC.MIN  
2
0
—
tCK  
tOIT  
12  
—
ns  
Data output hold time from DQS  
Data hold skew factor  
tQH  
tHP – tQHS  
tQHS  
—
—
—
75  
450  
7.8  
3.9  
—
ps  
µs  
µs  
ns  
ns  
tCK  
tCK  
ns  
ns  
ns  
8)  
9)  
Average periodic refresh Interval  
tREFI  
Auto-Refresh to Active/Auto-Refresh command period tRFC  
Precharge-All (4 banks) command period  
Read preamble  
tRP  
t
RP + 1tCK  
—
tRPRE  
tRPST  
tRRD  
0.9  
0.40  
7.5  
10  
1.1  
0.60  
—
Read postamble  
10)  
11)  
Active bank A to Active bank B command period  
—
Internal Read to Precharge command delay  
Data Sheet  
tRTP  
7.5  
—
28  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
Table 18  
Timing Parameter by Speed Grade - DDR2-400  
Symbol  
Parameter  
DDR2-400  
Min.  
Unit Note  
1)2)3)4)5)6)7)  
Max.  
—
Write preamble  
tWPRE  
tWPST  
tWR  
0.35  
tCK  
tCK  
ns  
Write postamble  
0.40  
0.60  
—
Write recovery time for write without Auto-Precharge  
Write recovery time for write with Auto-Precharge  
Internal Write to Read command delay  
15  
WR  
t
WR/tCK  
tCK  
ns  
tWTR  
tXARD  
7.5  
2
—
—
Exit power down to any valid command  
(other than NOP or Deselect)  
tCK  
Exit active power-down mode to Read command (slow tXARDS  
exit, lower power)  
6 – AL  
2
—
—
tCK  
tCK  
Exit precharge power-down to any valid command  
(other than NOP or Deselect)  
tXP  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
t
RFC +10  
—
—
ns  
200  
tCK  
1) For details and notes see the relevant INFINEON component data sheet  
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)  
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be  
powered down and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a  
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.  
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is  
recognized as low.  
7) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.  
8) 0 ≤ TCASE ≤ 85 °C  
9) 85 °C < TCASE ≤ 95 °C  
10) x4 & x8  
11) x16  
Data Sheet  
29  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsAC Characteristics  
3.3.3  
ODT AC Electrical Characteristics  
Table 19  
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667  
Symbol Parameter / Condition  
Values  
Min.  
2
Unit  
Note  
Max.  
tAOND  
tAON  
ODT turn-on delay  
2
tCK  
ns  
ns  
tCK  
ns  
1)  
ODT turn-on  
tAC.MIN  
t
AC.MAX + 0.7 ns  
AC.MAX + 1 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns 2 tCK +  
t
2.5  
2.5  
2)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns  
ODT to Power Down Mode Entry Latency 3  
ODT Power Down Exit Latency  
—
—
tCK  
tCK  
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time  
max is when the ODT resistance is fully on. Both are measure from tAOND  
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high  
impedance. Both are measured from tAOFD  
.
.
Table 20  
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400  
Symbol Parameter / Condition  
Values  
Min.  
2
Unit  
Note  
Max.  
tAOND  
tAON  
ODT turn-on delay  
2
tCK  
ns  
ns  
tCK  
ns  
1)  
ODT turn-on  
tAC.MIN  
t
AC.MAX + 1 ns  
AC.MAX + 1 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns 2 tCK +  
t
2.5  
2.5  
2)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns  
ODT to Power Down Mode Entry Latency 3  
ODT Power Down Exit Latency  
—
—
tCK  
tCK  
8
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time  
max is when the ODT resistance is fully on. Both are measure from tAOND  
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high  
impedance. Both are measured from tAOFD  
.
.
Data Sheet  
30  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsCurrents Specifications and Conditions  
3.4  
Currents Specifications and Conditions  
Table 21  
I
DD Measurement Conditions 1)2)3)4)5)6)  
Parameter  
Symbol  
Operating Current 0  
IDD0  
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH  
between valid commands. Address and control inputs are SWITCHING, Databus inputs are  
SWITCHING.  
Operating Current 1  
IDD1  
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN  
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and  
control inputs are SWITCHING, Databus inputs are SWITCHING.  
Precharge Standby Current  
IDD2N  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are  
SWITCHING, Data bus inputs are SWITCHING.  
Precharge Power-Down Current  
Other control and address inputs are STABLE, Data bus inputs are FLOATING.  
IDD2P  
IDD2Q  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,  
Data bus inputs are FLOATING.  
Active Standby Current  
IDD3N  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus  
inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);  
IDD3P(0)  
IDD3P(1)  
IDD4W  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus  
inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);  
Operating Current  
urst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING;  
Burst Refresh Current  
IDD5B  
IDD5D  
IDD6  
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Distributed Refresh Current  
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Self-Refresh Current  
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,  
Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.  
All Bank Interleave Read Current  
IDD7  
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control  
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.  
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
Data Sheet  
31  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsCurrents Specifications and Conditions  
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.  
3) Definitions for IDD see Table 22  
4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module  
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to  
HIGH.  
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P  
6) For details and notes see the relevant INFINEON component data sheet  
Table 22  
Parameter  
LOW  
Definitions for IDD  
Description  
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN  
inputs are stable at a HIGH or LOW level  
inputs are VREF = VDDQ /2  
STABLE  
FLOATING  
SWITCHING inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address  
and control signals, and inputs changing between HIGH and LOW every other data transfer (once  
per cycle) for DQ signals not including mask or strobes  
Data Sheet  
32  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsCurrents Specifications and Conditions  
Table 23  
I
DD Specification for HYS72T[32/64]×××HP–[3S/3.7]–A  
Product Type  
Unit  
Note1)  
Organization  
256 MByte 512 MByte 512 MByte 256 MByte 512 MByte 512 MByte  
1 Rank  
×72  
1 Rank  
×72  
2 Rank  
×72  
1 Rank  
×72  
1 Rank  
×72  
2 Rank  
×72  
–3S  
Max.  
940  
–3S  
–3S  
–3.7  
Max.  
830  
–3.7  
Max.  
1490  
1580  
1130  
570  
–3.7  
Max.  
860  
Symbol  
IDD0  
Max.  
1710  
1870  
1410  
690  
Max.  
990  
2)  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
1020  
790  
1070  
1200  
480  
870  
910  
3)  
IDD2N  
650  
960  
3)  
IDD2P  
430  
370  
400  
3)  
IDD2Q  
660  
1140  
1410  
940  
930  
560  
950  
780  
3)  
IDD3N  
790  
1200  
730  
650  
1130  
790  
960  
3)  
IDD3P.MRS=0  
IDD3P.MRS=1  
IDD4R  
560  
470  
620  
3)  
430  
690  
480  
370  
570  
400  
2)  
1380  
1420  
1240  
440  
2580  
2670  
2310  
700  
1420  
1470  
1290  
490  
960  
1760  
2030  
2030  
610  
1000  
1130  
1130  
440  
2)  
IDD4W  
IDD5B  
1100  
1100  
380  
2)  
3)4)  
3)4)  
2)  
IDD5D  
IDD6  
36  
72  
72  
36  
72  
72  
IDD7  
1630  
3080  
1670  
1550  
2930  
1580  
1) Module IDD is calculated on the basis of component IDD and includes currents of Registers and PLL. ODT disabled. IDD1  
DD4R and IDD7 are defined with the outputs disabled.  
,
I
2) The other rank is IDD2P Precharge Power-Down Standby Current mode.  
3) Both ranks are in the same IDD mode.  
4) Values for 0 °C ≤ TCASE ≤ 85 °C  
Data Sheet  
33  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Electrical CharacteristicsCurrents Specifications and Conditions  
3.4.1  
Currents Test Conditions  
For testing the IDD parameters, the following timing parameters are used:  
Table 24  
IDD Measurement Test Conditions for DDR2–667  
Parameter  
Symbol  
–3S  
Unit  
DDR2–667D  
CAS Latency  
CL(IDD)  
tCK(IDD)  
tRCD(IDD)  
tRC(IDD)  
tRRD(IDD)  
5
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
Clock Cycle Time  
3.75  
15  
60  
7.5  
Active to Read or Write delay  
Active to Active / Auto-Refresh command period  
Active bank A to Active bank B command delay  
Active to Precharge Command  
tRAS.MIN(IDD) 45  
tRAS.MAX(IDD) 70000  
Precharge Command Period  
tRP(IDD)  
tREFI  
15  
Average periodic Refresh interval  
7.8  
Table 25  
IDD Measurement Test Conditions for DDR2–533  
Parameter  
Symbol  
–3.7  
Unit  
DDR2–533C  
CAS Latency  
CL(IDD)  
4
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
Clock Cycle Time  
tCK(IDD)  
3.75  
15  
Active to Read or Write delay  
tRCD(IDD)  
tRC(IDD)  
Active to Active / Auto-Refresh command period  
Active bank A to Active bank B command delay  
Active to Precharge Command  
60  
tRRD(IDD)  
tRAS.MIN(IDD)  
tRAS.MAX(IDD)  
tRP(IDD)  
7.5  
45  
70000  
15  
Precharge Command Period  
Average periodic Refresh interval  
tREFI  
7.8  
3.4.2  
On Die Termination (ODT) Current  
The ODT function adds additional current consumption current consumption for any terminated input pin,  
to the DDR2 SDRAM when enabled by the EMRS(1). depends on the input pin is in tri-state or driving 0 or 1,  
Depending on address bits A[6,2] in the EMRS(1) a as long a ODT is enabled during a given period of time.  
“weak” or “strong” termination can be selected. The  
Table 26  
ODT current per terminated pin  
Parameter  
Symbol Min.  
Typ.  
6
Max. Unit  
EMRS(1) State  
Enabled ODT current per DQ  
IODTO  
5
7.5 mA/DQ A6 = 0, A2 = 1  
ODT is HIGH; Data Bus inputs are FLOATING  
2.5  
7.5  
10  
5
3
3.75 mA/DQ A6 = 1, A2 = 0  
11.25 mA/DQ A6 = 1, A2 = 1  
9
Active ODT current per DQ  
ODT is HIGH; worst case of Data Bus inputs are  
STABLE or SWITCHING.  
IODTT  
12  
6
15  
mA/DQ A6 = 0, A2 = 1  
mA/DQ A6 = 1, A2 = 0  
7.5  
15  
18  
22.5 mA/DQ A6 = 1, A2 = 0  
Data Sheet  
34  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
4
SPD Codes  
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet.  
SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined  
during production.  
Note:Self refresh rate is programmable via EMRS2 setting. The Refresh Period is 7.8 µs at a TCASE lower than 85  
°C, 3.9 µs between 85 °C and 95 °C  
List of SPD Code Tables  
•
•
Table 27 “SPD Codes for PC2–5300” on Page 35  
Table 28 “SPD Codes for PC2–4200” on Page 39  
Table 27  
SPD Codes for PC2–5300  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–5300R–  
555  
PC2–5300R–  
555  
PC2–5300R–  
555  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
80  
Rev. 1.2  
HEX  
80  
Rev. 1.2  
HEX  
80  
0
Programmed SPD Bytes in EEPROM  
1
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
08  
08  
08  
2
08  
08  
08  
3
0D  
0A  
60  
0E  
0A  
60  
0D  
0A  
61  
4
5
6
48  
48  
48  
7
Not used  
00  
00  
00  
8
Interface Voltage Level  
05  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
30  
30  
30  
10  
11  
12  
13  
14  
15  
16  
AC SDRAM @ CLMAX (Byte 18) [ns]  
45  
45  
45  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
06  
06  
06  
82  
82  
82  
08  
08  
08  
08  
08  
08  
00  
00  
00  
Burst Length Supported  
0C  
0C  
0C  
Data Sheet  
35  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
Table 27  
SPD Codes for PC2–5300 (cont’d)  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–5300R–  
555  
PC2–5300R–  
555  
PC2–5300R–  
555  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
04  
Rev. 1.2  
HEX  
04  
Rev. 1.2  
HEX  
04  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
38  
38  
38  
01  
01  
01  
01  
01  
01  
04  
04  
05  
Component Attributes  
03  
03  
03  
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
3D  
50  
3D  
50  
3D  
50  
50  
50  
50  
60  
60  
60  
3C  
1E  
3C  
2D  
40  
3C  
1E  
3C  
2D  
80  
3C  
1E  
3C  
2D  
40  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
20  
20  
20  
27  
27  
27  
10  
10  
10  
DH.MIN [ns]  
17  
17  
17  
WR.MIN [ns]  
3C  
1E  
1E  
00  
3C  
1E  
1E  
00  
3C  
1E  
1E  
00  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
00  
00  
00  
3C  
4B  
80  
3C  
69  
3C  
4B  
80  
RFC.MIN [ns]  
CK.MAX [ns]  
80  
DQSQ.MAX [ns]  
18  
18  
18  
Data Sheet  
36  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
Table 27  
SPD Codes for PC2–5300 (cont’d)  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–5300R–  
555  
PC2–5300R–  
555  
PC2–5300R–  
555  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
22  
Rev. 1.2  
HEX  
22  
Rev. 1.2  
HEX  
22  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
t
QHS.MAX [ns]  
PLL Relock Time  
CASE.MAX Delta / ∆T4R4W Delta  
0F  
0F  
53  
0F  
53  
T
53  
Psi(T-A) DRAM  
78  
78  
78  
∆T0 (DT0)  
4B  
4B  
2E  
26  
4B  
2E  
26  
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 2E  
∆T2P (DT2P)  
26  
26  
2B  
1B  
4A  
20  
22  
C4  
8C  
68  
94  
12  
E8  
C1  
00  
00  
00  
00  
00  
00  
00  
xx  
∆T3N (DT3N)  
26  
26  
∆T3P.fast (DT3P fast)  
2B  
1B  
4A  
20  
2B  
1B  
4A  
20  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)  
∆T5B (DT5B)  
∆T7 (DT7)  
22  
22  
Psi(ca) PLL  
C4  
8C  
68  
C4  
8C  
68  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
94  
94  
12  
12  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
47  
EA  
C1  
00  
C1  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
xx  
xx  
Data Sheet  
37  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
Table 27  
SPD Codes for PC2–5300 (cont’d)  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–5300R–  
555  
PC2–5300R–  
555  
PC2–5300R–  
555  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
37  
Rev. 1.2  
HEX  
37  
Rev. 1.2  
HEX  
37  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
Product Type, Char 1  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
32  
32  
32  
54  
54  
54  
33  
36  
36  
32  
34  
34  
30  
30  
30  
30  
30  
32  
30  
30  
30  
48  
48  
48  
50  
50  
50  
33  
33  
33  
53  
53  
53  
41  
41  
41  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
0x  
0x  
0x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
95 - 98 Module Serial Number  
99 - 127 Not used  
xx  
xx  
xx  
00  
00  
00  
Data Sheet  
38  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
Table 28  
SPD Codes for PC2–4200  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–4200R–  
444  
PC2–4200R–  
444  
PC2–4200R–  
444  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
80  
Rev. 1.2  
HEX  
80  
Rev. 1.2  
HEX  
80  
0
Programmed SPD Bytes in EEPROM  
1
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
08  
08  
08  
2
08  
08  
08  
3
0D  
0A  
60  
0E  
0A  
60  
0D  
0A  
61  
4
5
6
48  
48  
48  
7
Not used  
00  
00  
00  
8
Interface Voltage Level  
05  
05  
05  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
3D  
50  
3D  
50  
3D  
50  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
AC SDRAM @ CLMAX (Byte 18) [ns]  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
06  
06  
06  
82  
82  
82  
Primary SDRAM Width  
08  
08  
08  
Error Checking SDRAM Width  
Not used  
08  
08  
08  
00  
00  
00  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
0C  
04  
0C  
04  
0C  
04  
38  
38  
38  
01  
01  
01  
01  
01  
01  
04  
04  
05  
Component Attributes  
03  
03  
03  
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
3D  
50  
3D  
50  
3D  
50  
50  
50  
50  
60  
60  
60  
Data Sheet  
39  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
Table 28  
SPD Codes for PC2–4200 (cont’d)  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–4200R–  
444  
PC2–4200R–  
444  
PC2–4200R–  
444  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
3C  
1E  
3C  
2D  
40  
Rev. 1.2  
HEX  
3C  
1E  
3C  
2D  
80  
Rev. 1.2  
HEX  
3C  
1E  
3C  
2D  
40  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
t
t
t
t
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
25  
25  
25  
37  
37  
37  
10  
10  
10  
DH.MIN [ns]  
22  
22  
22  
WR.MIN [ns]  
3C  
1E  
1E  
00  
3C  
1E  
1E  
00  
3C  
1E  
1E  
00  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
00  
00  
00  
3C  
4B  
80  
3C  
69  
3C  
4B  
80  
RFC.MIN [ns]  
CK.MAX [ns]  
80  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
1E  
28  
1E  
28  
1E  
28  
PLL Relock Time  
CASE.MAX Delta / ∆T4R4W Delta  
0F  
0F  
0F  
T
51  
51  
51  
Psi(T-A) DRAM  
78  
78  
78  
∆T0 (DT0)  
3F  
3F  
3F  
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 22  
22  
22  
∆T2P (DT2P)  
1E  
1E  
24  
1E  
1E  
24  
1E  
1E  
24  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
Data Sheet  
40  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
Table 28  
SPD Codes for PC2–4200 (cont’d)  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–4200R–  
444  
PC2–4200R–  
444  
PC2–4200R–  
444  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
17  
Rev. 1.2  
HEX  
17  
Rev. 1.2  
HEX  
17  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)  
∆T5B (DT5B)  
34  
34  
34  
1E  
20  
1E  
20  
1E  
20  
∆T7 (DT7)  
Psi(ca) PLL  
C4  
8C  
61  
C4  
8C  
61  
C4  
8C  
61  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
78  
78  
78  
12  
12  
12  
Checksum of Bytes 0-62  
JEDEC ID Code of Infineon (1)  
JEDEC ID Code of Infineon (2)  
JEDEC ID Code of Infineon (3)  
JEDEC ID Code of Infineon (4)  
JEDEC ID Code of Infineon (5)  
JEDEC ID Code of Infineon (6)  
JEDEC ID Code of Infineon (7)  
JEDEC ID Code of Infineon (8)  
Module Manufacturer Location  
Product Type, Char 1  
BA  
C1  
00  
19  
BC  
C1  
00  
C1  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
xx  
xx  
xx  
37  
37  
37  
Product Type, Char 2  
32  
32  
32  
Product Type, Char 3  
54  
54  
54  
Product Type, Char 4  
33  
36  
36  
Product Type, Char 5  
32  
34  
34  
Product Type, Char 6  
30  
30  
30  
Product Type, Char 7  
30  
30  
32  
Product Type, Char 8  
30  
30  
30  
Data Sheet  
41  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
SPD Codes  
Table 28  
SPD Codes for PC2–4200 (cont’d)  
Product Type  
Organization  
Label Code  
256MB  
×72  
512MB  
×72  
512MB  
×72  
1 Rank (×8)  
1 Rank (×8)  
2 Ranks (×8)  
PC2–4200R–  
444  
PC2–4200R–  
444  
PC2–4200R–  
444  
JEDEC SPD Revision  
Byte# Description  
Rev. 1.2  
HEX  
48  
Rev. 1.2  
HEX  
48  
Rev. 1.2  
HEX  
48  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
50  
50  
50  
33  
33  
33  
2E  
37  
2E  
37  
2E  
37  
41  
41  
41  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
0x  
0x  
0x  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
xx  
95 - 98 Module Serial Number  
99 - 127 Not used  
xx  
xx  
xx  
00  
00  
00  
Data Sheet  
42  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
                                                                                                         
                                                                                                           
                                                                                                            
                                                                                                             
                                                       
                                                        
                                                          
                                                          
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WD  
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IꢄF  
Q
WD  
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ꢀꢏꢋꢄ  
                                                  
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HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Package Outlines  
5
Package Outlines  
ꢁ
ꢁ
                                                       
ꢅ
ꢈ
                                                        
ꢅꢏꢅ  
ꢋꢏꢇ  
                                                          
                                                          
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ꢆꢄ  
ꢈꢏꢂ  
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ꢉꢄ  
ꢈꢏꢆꢄ  
&ꢄ  
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%ꢄ  
ꢁꢄ  
Figure 5  
Notes  
Package Outline Raw Card F L-DIM-240-11  
1. General tolerances +/- 0.15  
2. Drawing according to ISO 8015  
Data Sheet  
43  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
                                                                                                          
                                                                                                           
                                                                                                            
                                                       
                                                        
                                                          
                                                          
ꢁꢄ  
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ꢁꢏꢆꢄ  
                                                                         
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ꢁ
                  
                   
ꢈꢉꢀꢄ  
                                                                                          
                                                                                           
ꢈ
ꢁꢄ  
ꢐꢅꢑꢄ  
                     
'
                   
H
                    
                    
                     
                     
                      
R
                       
                        
FR  
ꢁꢄ  
                         
                          
                           
                           
                            
                             
                             
WD  
L
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Iꢄ  
Q
WD  
FWVꢄ  
“
ꢀꢏꢋꢄ  
                                                  
ꢀꢏꢀꢆꢄ  
                                                    
                                                     
                                     
ꢀꢏꢁꢄ$ꢄ %ꢄ &ꢄ  
                                              
%
                    
                     
                     
ꢄ
                      
PD  
                        
                        
ꢏꢄ  
                          
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ꢄ
                             
D
                              
                              
                               
                                
                                 
                                  
*
                                                                                                                                         
                                                                                                                                          
                                                                                                                                            
                                                                                                                                             
                                                                                                                                             
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XUU  
[
OORZHGꢄ  
/'ꢀꢇ  
ꢄ
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Package Outlines  
ꢁ
ꢁ
                                                       
ꢅ
ꢈ
                                                        
ꢅꢏꢅ  
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ꢉꢄ  
ꢈꢏꢆꢄ  
&ꢄ  
ꢆꢄ  
$ꢄ  
%ꢄ  
Figure 6  
Notes  
Package Outline Raw Card G L-DIM-240-12  
1. General tolerances +/- 0.15  
2. Drawing according to ISO 8015  
Data Sheet  
44  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
                                                                                                          
                                                                                                           
                                                                                                            
                                                       
                                                        
                                                          
                                                          
ꢁꢄ  
ꢁꢈꢀꢄ  
                                                                                          
                                                                                          
                                                        
“
ꢂꢄ  
                                                                                                                                            
ꢀꢏꢁꢄ  
                                                                                                                                             
ꢁꢏ  
                                                                                                         
ꢈ
                                                                                                          
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ꢆꢆꢄ  
                                                                             
ꢅꢄ  
“ꢀꢏꢁꢄ  
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ꢁ
                  
                   
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'H  
                   
                    
                    
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%
                    
                     
                     
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[ꢏꢄꢀ  
/
ꢂꢄ  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Package Outlines  
ꢁ
ꢁ
                                                       
ꢅꢅ  
ꢈꢋ  
                                                        
ꢏ
ꢏ
                                                          
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ꢇ
                                                          
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&ꢄ  
ꢆꢄ  
$ꢄ  
%ꢄ  
ꢁꢄ  
Figure 7  
Notes  
Package Outline Raw Card H L-DIM-240-13  
1. General tolerances +/- 0.15  
2. Drawing according to ISO 8015  
Data Sheet  
45  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
HYS72T[32/64]xxxHP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type Nomenclature (DDR2 DRAMs and DIMMs)  
6
Product Type Nomenclature (DDR2 DRAMs and DIMMs)  
Infineon’s nomenclature uses simple coding combined description together with possible values and coding  
with some propriatory coding. Table 29 provides explanation is listed for modules in Table 30 and for  
examples for module and component product type components in Table 31.  
number as well as the field number. The detailed field  
Table 29  
Nomenclature Fields and Examples  
Field Number  
Example for  
1
2
3
T
T
4
5
6
7
0
0
8
9
10  
–5  
–5  
11  
Micro-DIMM  
DDR2 DRAM  
HYS  
HYB  
64  
18  
64  
512  
0
2
K
A
M
C
–A  
16  
1) Multiplying “Memory Density per I/O” with “Module Data  
Width” and dividing by 8 for Non-ECC and 9 for ECC  
modules gives the overall module memory density in  
MBytes as listed in column “Coding”.  
Table 30  
DDR2 DIMM Nomenclature  
Values Coding  
Field Description  
1
INFINEON  
HYS  
Constant  
Modul Prefix  
2
Module Data  
Width [bit]  
64  
72  
T
Non-ECC  
ECC  
Table 31  
DDR2 DRAM Nomenclature  
Values Coding  
Field Description  
3
4
DRAM  
Technology  
DDR2  
1
2
3
4
INFINEON  
Component Prefix  
HYB  
Constant  
SSTL_18  
DDR2  
Memory Density  
per I/O [Mbit];  
Module Density1)  
32  
256 MByte  
512 MByte  
1 GByte  
Interface Voltage 18  
[V]  
64  
DRAM  
Technology  
T
128  
256  
512  
0 .. 9  
2 GByte  
Component  
256  
512  
1G  
2G  
40  
256 Mbit  
512 Mbit  
1 Gbit  
2 Gbit  
×4  
4 GByte  
Density [Mbit]  
5
6
Raw Card  
Generation  
Look up table  
Number of Module 0, 2, 4 1, 2, 4  
Ranks  
5+6 Number of I/Os  
7
8
Product Variations 0 .. 9  
Look up table  
80  
×8  
Package,  
A .. Z  
Look up table  
16  
×16  
Lead-Free Status  
7
8
Product Variations 0 .. 9  
Look up table  
First  
9
Module Type  
Speed Grade  
Die Revision  
D
SO-DIMM  
Die Revision  
A
B
C
M
Micro-DIMM  
Registered  
Second  
R
9
Package,  
Lead-Free Status  
FBGA,  
lead-containing  
U
Unbuffered  
F
Fully Buffered  
PC2–6400 6–6–6  
PC2–5300 4–4–4  
PC2–5300 5–5–5  
PC2–4200 4–4–4  
PC2–3200 3–3–3  
First  
F
FBGA, lead-free  
DDR2-800 6-6-6  
DDR2-667 4-4-4  
DDR2-667 5-5-5  
DDR2-533 4-4-4  
DDR2-400 3-3-3  
10  
11  
–2.5  
–3  
–3S  
–3.7  
–5  
–A  
–B  
10  
Speed Grade  
–2.5  
–3  
–3S  
–3.7  
–5  
Second  
Data Sheet  
46  
Rev. 1.0, 2006-03  
02102006-0OKM-JLO7  
w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  
厂商 型号 描述 页数 下载

INFINEON

 		HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

INFINEON

 		HYS64-74V8200GU 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ] 17 页

INFINEON

 		HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

 		HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

 		HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

 		HYS64D128020GBDL-7-A ？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

 		HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

 		HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

 		HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

 		HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

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