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TZA3004HL/C3

型号：

TZA3004HL/C3

品牌：

NXP[ NXP ]

页数：

26 页

PDF大小：

335 K

下载PDF手册
INTEGRATED CIRCUITS  
DATA SHEET  
TZA3004HL  
SDH/SONET data and clock  
recovery unit STM1/4 OC3/12  
1998 Feb 09  
Objective specification  
File under Integrated Circuits, IC19  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
FEATURES  
DESCRIPTION  
• Data and clock recovery up to 622 Mbits/s (STM1/OC3  
and STM4/OC12)  
The TZA3004HL is a data and clock recovery IC intended  
for use in SDH (Synchronous Digital Hierarchy) and  
SONET (Synchronous Optical Network) systems.  
The circuit recovers data and extracts the clock signal from  
an incoming bitstream up to 622 Mbits/s. It can be  
configured for use in STM1/OC3 and STM4/OC12  
systems.  
• Differential data input with 2.5 mV peak-to-peak typical  
sensitivity  
• Differential CML (Current-Mode Logic) data and clock  
outputs with 50 Ω driving capability  
• Adjustable CML output level  
• Loop mode for system testing  
• BER related LOS detection  
• Few external components needed  
• LQFP48 plastic package  
APPLICATIONS  
• Data and clock recovery in STM1/OC3 and STM4/OC12  
transmission systems (up to 622 Mbits/s).  
• Power dissipation typical 370 mW  
• Single supply voltage.  
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
TZA3004HL  
LQFP48  
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm  
SOT313-2  
1998 Feb 09  
2
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
BLOCK DIAGRAM  
LOS  
SEL155  
30  
AREF ENL  
39  
48  
1
FREQUENCY  
DIVIDER 1  
4/16  
42  
DOUT  
43  
DOUTQ  
45  
COUT  
DATA  
AND  
CLOCK  
OUTPUT  
46  
33  
COUTQ  
DIN  
ALEXANDER  
PHASE  
DETECTOR  
6
DLOOP  
34  
7
DINQ  
DLOOPQ  
3
TZA3004HL  
CLOOP  
4
enable  
CLOOPQ  
21  
22  
CREF  
proportional  
FREQUENCY  
WINDOW  
DETECTOR  
(1000 ppm)  
path  
CREFQ  
VCRO  
+
integrating  
path  
∫ dt  
130 pF  
130 pF  
37  
POWER  
CONTROL  
PC  
FREQUENCY  
DIVIDER 2  
64/128  
17  
2, 5, 8, 10, 11, 14, 17,  
20, 23, 26, 29, 32, 35,  
38, 41, 44, 47  
2
12  
9
24  
16  
15  
25, 31  
MGK140  
V
LOCK  
REF19  
REF39 CAPDOQ  
GND  
EE  
CAPUPQ  
Fig.1 Block diagram.  
3
1998 Feb 09  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
PINNING  
SYMBOL  
ENL  
PIN  
DESCRIPTION  
1
loop mode enable input (active low)  
ground  
GND  
CLOOP  
CLOOPQ  
GND  
DLOOP  
DLOOPQ  
GND  
REF19  
GND  
GND  
LOCK  
i.c  
2
3
clock output in loop mode (differential)  
inverted clock output in loop mode (differential)  
ground  
4
5
6
data output in loop mode (differential)  
inverted data output in loop mode (differential)  
ground  
7
8
9
reference frequency select input (see Table 2)  
ground  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
ground  
phase lock detection output  
internally connected (leave open)  
ground  
GND  
CAPUPQ  
CAPDOQ  
GND  
i.c.  
external loop filter capacitor  
external loop filter capacitor return  
ground  
internally connected (leave open)  
internally connected (leave open)  
ground  
i.c.  
GND  
CREF  
CREFQ  
GND  
REF39  
VEE  
reference clock input (differential)  
inverting reference clock input (differential)  
ground  
reference frequency select input (see Table 2)  
negative supply voltage  
ground  
GND  
VEE  
negative supply voltage  
negative supply voltage  
ground  
VEE  
GND  
SEL155  
VEE  
STM mode select input (see Table 1)  
negative supply voltage  
ground  
GND  
DIN  
data input (differential)  
DINQ  
GND  
i.c.  
inverting data input (differential)  
ground  
internally connected (leave open)  
negative power supply control signal output  
ground  
PC  
GND  
LOS  
loss-of-signal detection output  
internally connected (leave open)  
i.c.  
1998 Feb 09  
4
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
SYMBOL  
GND  
PIN  
DESCRIPTION  
41  
42  
43  
44  
45  
46  
47  
48  
ground  
DOUT  
DOUTQ  
GND  
data output in normal mode (differential)  
inverted data output in normal mode (differential)  
ground  
COUT  
COUTQ  
GND  
clock output in normal mode (differential)  
inverted clock output in normal mode (differential)  
ground  
AREF  
reference voltage input for controlling voltage swing on data and clock outputs  
i.c.  
1
2
36
ENL  
GND  
35  
GND  
34 DINQ  
33  
CLOOP  
CLOOPQ  
GND  
3
4
DIN  
5
32 GND  
V
6
DLOOP  
DLOOPQ  
GND  
31  
30  
EE  
TZA3004HL  
7
SEL155  
29 GND  
8
V
28  
EE  
REF19  
GND  
9
V
27
10  
11  
12  
EE  
26  
GND  
GND  
LOCK  
25 V  
EE  
MGK139  
Fig.2 Pin configuration.  
5
1998 Feb 09  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
of the clock signal, while the integrating path adjusts the  
centre frequency.  
FUNCTIONAL DESCRIPTION  
The TZA3004HL recovers data and clock signals from an  
incoming high speed bitstream. The input signal on DIN,  
DINQ is buffered and amplified by the input circuitry.  
The frequency window detector checks that the VCRO  
frequency is within a 1000 ppm (parts per million) window  
around the required frequency. It compares the output of  
frequency divider 2 with the reference frequency at CREF,  
CREFQ (19.44 MHz or 38.88 MHz as available; see  
Table 2). If the VCRO frequency is found to be outside this  
window, the frequency window detector disables the  
Alexander phase detector and forces the VCRO output to  
a frequency within the window. The phase detector then  
starts acquiring lock again. Because of the loose coupling  
(1000 ppm), the reference frequency doesn’t need to be  
highly accurate or stable. Any crystal based oscillator that  
generates a reasonably accurate frequency (e.g. 100ppm)  
)will do.  
The signal is then fed to the Alexander phase detector  
where the phase of the incoming data is compared with  
that of the internal clock. If the signals are out of phase, the  
phase detector generates (UP or DOWN) correction  
pulses that shift the phase of the VCRO (Voltage  
Controlled Ring Oscillator) output in discrete amounts, ∆ϕ,  
until the clock and data signals are in phase.  
The technique used is based on principles first proposed  
by J.D.H. Alexander, hence the phase detector’s name.  
The eye pattern of the incoming data is sampled at three  
instants A, T and B (see Fig.3). When clock and data  
signals are synchronized (locked), A is in the centre of the  
data bit, T is in the vicinity of the next transition, and B is in  
the centre of the bit following the transition. If the same  
level is recorded at both A and B, a transition has not  
occurred and no action is taken regardless of the value  
at T. If A and B are different, however, a transition has  
occurred and the phase detector uses the value at T to  
determine whether the clock was too early or too late with  
respect to the data transition. If A and T are the same, but  
different from B, the clock was too early and needs to be  
slowed down a little. The Alexander phase detector then  
generates a DOWN pulse which stretches a single output  
pulse from the ring oscillator by approximately 0.25% (or  
4 ps in STM4 mode; 4 ps is 0.25% of the 1.608 ns bit  
period). This forces the VCRO to run at a slightly lower  
frequency for one bit period. The phase of the clock is thus  
shifted fractionally with respect to the data.  
Since sampling point A is always in the centre of the eye  
pattern when the data and clock signals are in phase  
(locked), the values recorded at this point are taken as the  
retrieved data. The data and clock signals are available at  
the CML output buffers, which are capable of driving a  
50 Ω load.  
handbook, halfpage  
DATA  
A
T
B
CLOCK  
MGK143  
Fig.3 Data sampling.  
If, on the other hand, B and T are the same but different  
from A, the clock was too late and needs to be speeded up  
for synchronization. The phase detector generates an UP  
pulse forcing the VCRO to run at a slightly higher  
frequency (+0.25%) for one bit period. The phase of the  
clock is shifted with respect to the data (as above, but in  
the opposite direction). Only the proportional path is active  
while these phase adjustments are being made. Because  
the instantaneous frequency of the VCRO can be changed  
only in one of two discrete steps (±0.25%), this type of loop  
is also known as a Bang/Bang PLL.  
Power Control (PC)  
The TZA3004HL contains an on-board voltage regulator.  
An external power transistor is needed to deliver supply  
current, IEE, to this circuit. The required external circuit is  
straightforward, and can be built using a few components.  
A suitable circuit is depicted in Fig.4. A different  
configuration could be used, as long as the power supply  
rejection ratio is greater than 60 dB for all frequencies.  
The inductor is a (lossy) 1 µH RF-choke (EMI) with an  
impedance greater than 50 Ω at frequencies higher than  
2 MHz. Any transistor with a β > 100 and enough current  
sink capability can be used.  
If not only the phase but also the frequency of the VCRO  
is incorrect, a long train of UP or DOWN pulses will be  
generated. This pulse train is integrated to generate a  
control voltage that is used to shift the centre frequency of  
the VCRO. Once the correct frequency has been  
The TZA3004HL can also be used with a -5V or -5.2V  
supply voltage. The only adaption that has to be made to  
the Power Control circuit is resistor R of 2Ω. This should  
be 6.8Ω with a -5V supply and 8.2Ω with a -5.2V supply.  
established, the phase will need to be adjusted for  
synchronization. The proportional path adjusts the phase  
1998 Feb 09  
6
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
BAND GAP  
REFERENCE  
POWER  
CONTROL  
V
PC  
EE  
100 nF  
2 Ω  
β > 100  
3.3  
nF  
1
kΩ  
1 µF  
1 µH  
1 kΩ  
2 Ω  
−4.5 V  
MGK141  
Fig.4 Schematic diagram of TZA3004HL power control loop.  
This can be achieved by connecting a 7.3 kΩ resistor  
between AREF and VEE  
Output amplitude reference (AREF)  
.
The voltage swing at the CML compatible output stages  
DOUT, DOUTQ; COUT, COUTQ; DLOOP, DLOOPQ and  
CLOOP, CLOOPQ can be controlled by adjusting the  
voltage at the AREF pin. An internal voltage divider of  
500 Ω and16 kΩ between GND and VEE initially fixes this  
level.  
The formulae for calculating the required voltage at AREF  
and the external resistance needed between AREF and  
VEE when the outputs are AC coupled are:  
RL + R  
1
2
VAREF = –  
o × V  
(1)  
------------------- --  
swing  
RL  
In most applications the outputs will be DC coupled to a  
load, which can be as low as 50 Ω (±0.20%). The output  
level regulation circuit will maintain a 200 mV  
peak-to-peak single-ended swing across this load.  
The voltage at AREF is half the single-ended peak-to-peak  
value of the output signal (or −100 mV in this case).  
No adjustments are necessary with DC coupling.  
and:  
VEE  
R1 ×  
– 1  
----------------  
VAREF  
RAREF  
=
----------------------------------------------------------------  
(2)  
V EE  
R1  
1 –  
×
– 1  
----------------  
-------  
R2  
VAREF  
If the outputs are AC coupled, however, the voltage at  
AREF is half the single-ended peak-to-peak value of the  
where R1 = 500 Ω, R2 = 16 kΩ and VEE = −3.3 V. RAREF  
is connected between AREF and VEE  
.
RL + Ro  
output signal multiplied by a factor  
-------------------  
RL  
where R L is the external load and Ro is the output  
impedance of the TZA3004HL.  
To maintain a 200 mV peak-to-peak single-ended swing  
across a 50 Ω AC coupled load, the voltage at AREF must  
–100 mV × (50 Ω + 100 Ω)  
be  
= –300 mV .  
-------------------------------------------------------------------------  
50 Ω  
1998 Feb 09  
7
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
Loop mode enable (ENL)  
Loss-of-signal detection (LOS)  
Loop mode is provided for system testing. Loop mode is  
enabled by applying a voltage lower than 0.8 V (TTL LOW)  
to the ENL pin. This selects loop mode outputs DLOOP,  
DLOOPQ and CLOOP, CLOOPQ. If a voltage greater than  
2.0 V (TTL HIGH) is applied to ENL, then DOUT, DOUTQ  
and COUT, COUTQ are switched in while DLOOP,  
DLOOPQ and CLOOP, CLOOPQ are disabled to minimize  
power consumption. If ENL is connected to VEE (−3.3 V),  
all outputs are enabled.  
The Loss of Signal (LOS) function is closely related to the  
Alexander Phase Detector functionality. Refer to Fig.3 for  
the meaning of A,B and T in this section.  
In the functional description it is described that the phase  
detector doesn’t take any action if the value at sample  
points A and B is the same, because there hasn’t been any  
transition. However, if the values at A and B are the same,  
but different from T, this still means there hasn’t been any  
transition, but somehow T got the wrong value. This is  
probably due to noise or bad signal integrity, which will  
lead to a Bit Error. Hence the occurrence of this particular  
situation is an indication for Bit Errors. If too many of these  
Bit Errors occur per time and the PLL is gradually losing  
lock, the LOS alarm is asserted. The LOS assert level is  
around a Bit Error Rate (BER) of 5 10-2 and the de-assert  
level is around BER of 1 10-3.  
External capacitor for loop filter (CAPUPQ; CAPDOQ)  
The loop filter is an integrator with a built in capacitance of  
2 × 130 pF. An external 200 nF capacitance must be  
connected between CAPUPQ and CAPDOQ to ensure  
loop stability while the frequency window detector is  
active.  
The LOS detection is BER related, but neither dependent  
of datastream content, nor protocol. Therefore, a  
SDH/SONET datastream is no prerequisite for a proper  
LOS function. Since the LOS function of the TZA3004HL  
is derived from digital signals, it is a good supplement to an  
analog, amplitude based, LOS indication.  
Lock detection (LOCK)  
The LOCK pin should be interpreted as an indication if the  
reference clock (CREF) is present and if the acquisition aid  
(frequency window detector) is working properly. The  
LOCK pin is an open collector TTL output and should be  
pulled up with a 10kΩ resistor to the positive supply. If the  
VCO frequency is within a 1000 ppm window around the  
desired frequency the LOCK pin will go HIGH. If no  
reference clock is present, or the VCO is outside the 1000  
ppm window, the LOCK pin will be LOW. The logic level of  
LOCK does not indicate if the PLL is locked onto the  
incoming data; this is indicated by the LOS signal.  
The LOS alarm is an open collector TTL compatible  
output. A pull-up resistor should be connected to a positive  
supply. LOS will be HIGH (TTL) if the data signal is absent  
at DIN, DINQ or BER is > 5 10-2, otherwise it will be LOW  
(BER < 1 10-3).  
Reference frequency select (REF19, REF39)  
A reference clock signal (either 19.44 MHz or 38.88 MHz,  
whichever is available) must be connected to CREF and  
CREFQ. Pins REF19 and REF39 are used to select the  
appropriate output frequency at frequency divider 2. Since  
the reference clock is only used as acquisition aid for the  
PLL (Frequency Window Detector), the quality of the  
reference clock is not important. There is no phase noise  
specification imposed on the reference clock generator  
and even frequency stability may be in the order of 100  
ppm. In general most inexpensive crystal based oscillators  
are suitable.  
STM mode selection (SEL155)  
SEL155 should be connected to VEE for STM1/OC3  
(155.52 Mbits/s) operation. For STM4/OC12  
(622.08 Mbits/s) systems, SEL155 should be connected to  
GND. The connections to VEE and GND should have low  
resistance and inductance. Short PCB tracks are  
recommended.  
Table 1 STM Mode Select  
BIT RATE  
MODE  
STM1  
DIV #  
SEL155  
Mbits/s  
155.52  
622.08  
Table 2 Reference Frequency Select  
16  
4
VEE  
FREQUENCY  
STM4  
GND  
DIV #  
REF19  
REF39  
MHz  
38.88  
19.44  
64  
VEE  
VEE  
VEE  
128  
GND  
1998 Feb 09  
8
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
approximately 3.3V below VCC). Beware not to connect  
ENL to ground, this would destroy the IC. In the positive  
supply application the NORMAL MODE outputs can not be  
selected anymore.  
POSITIVE SUPPLY APPLICATION  
Due to the versatile design of the TZA3004HL, the device  
can also operate in a positive supply application, although  
some pins have a different mode of operation. This section  
deals with these differences and supports the user with  
successful application of the TZA3004HL in a +5V  
Loss of signal detect and Lock detect (LOS & LOCK)  
environment. A sample application diagram can be found  
in figure 4. Note that all GND pins are now connected to  
VCC. All VEE pins are not connected to ground, but to pin  
25, the regulated voltage from the power controller.  
In the negative supply application, LOS and LOCK are  
open collector outputs, that require pull-up resistors to a  
positive supply. In the positive supply application, the  
pull-up voltage would be higher then the positive supply  
and the LOS and LOCK signals would not be TTL  
compatible. The internal circuit at pins LOS and LOCK can  
however be used in a current mirror configuration. It  
requires only an external PNP transistor, BC857 or  
equivalent, to mirror the current. A 10kΩ pull-down resistor  
to ground yields a TTL compatible signal again, albeit  
inverted. The table below shows the meaning of the LOS  
and LOCK flag, when used according to the application  
schematic of figure 4.  
Loop mode and normal mode output select (ENL)  
In a positive supply application, the default RF output will  
be the LOOP MODE outputs. Due to the decoding logic at  
the ENL pin, it is only possible to select the pins  
DLOOP(Q) and CLOOP(Q) as outputs or enable all  
outputs. If ENL is connected to VCC (+5V), the LOOP  
MODE outputs are active. All outputs become active If  
ENL is connected to pin VEE (the voltage on pin 25 is  
Table 3 LOS and LOCK indication for positive supply  
SIGNAL  
LOS active  
LOS inactive  
LOCK active  
DESCRIPTION  
Loss-of-signal; BER >5 10-2  
No loss-of-signal; BER < 1 10-3  
LEVEL  
TTL  
0V (ground)  
+5V (VCC)  
0V (ground)  
+5V (VCC)  
LOW  
HIGH  
LOW  
HIGH  
Reference clock present and VCO in 1000 ppm window  
LOCK inactive No reference clock present or VCO outside 1000 ppm window  
pins GND. In the positive supply application, this means all  
RF signals are referenced to VCC. Therefore a clean VCC  
rail is of ultimate importance for proper RF performance.  
The best performance is obtained when the transmission  
line reference plane is also decoupled to the VCC. Careful  
design of VCC and good decoupling schemes should be  
taken into account. While designing the printed circuit  
board, bear in mind that the VCC has become what was  
formerly ground.  
Divider settings  
The reference frequency dividers and the STM mode  
selectors still operate the same in a positive supply  
application. The only difference is that pins formerly  
connected to GND (ground) should now be connected to  
VCC (+5V), whereas pins connected to VEE still should be  
connected to pin VEE (pin 25). Connection to ground (0V)  
will damage the IC.  
RF input/outputs  
All RF inputs, outputs and internal signals of the  
TZA3004HL are referenced to the most positive supply,  
1998 Feb 09  
9
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
VEE  
Vn  
PARAMETER  
negative supply voltage  
MIN.  
MAX.  
UNIT  
−6  
−1  
+0.5  
V
DC voltages  
pins 3, 4, 6, 7, 21, 22, 33, 34, 42, 43, 45, 46  
pins 1, 12, 39  
+0.5  
+5.5  
+0.5  
−0.5  
V
V
V
V
V
EE − 0.5  
EE − 0.5  
EE + 0.5  
V
V
pins 9, 24, 30, 37, 48  
pins 15, 16  
In  
input current  
pin 1  
−
1
mA  
mA  
mW  
°C  
pins 21, 22, 33, 34  
total power dissipation  
ambient temperature  
junction temperature  
storage temperature  
−20  
−
+10  
700  
+85  
+110  
+150  
Ptot  
Tamb  
Tj  
−40  
−40  
−65  
°C  
Tstg  
°C  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
VALUE  
UNIT  
K/W  
K/W  
Rth(j-s)  
Rth(j-a)  
thermal resistance from junction to solder point  
thermal resistance from junction to ambient  
46  
67  
in free air  
Note  
1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided  
57x57x1.6mm FR4 epoxy PCB with 35µm thick copper traces. The measurements are performed in free air.  
1998 Feb 09  
10  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
CHARACTERISTICS  
External supply voltage = −4.5 V; Tamb = -40°C to +85°C; Typical values at Tamb=25°C; all voltages referenced to GND.  
SYMBOL  
Supply  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
VEE  
IEE  
P
negative supply voltage  
negative supply current  
power dissipation  
note 1  
open outputs  
−3.50  
−3.30  
112  
−3.10  
155  
V
−
−
mA  
370  
550  
mW  
Data and Clock inputs: DIN, DINQ and CREF, CREFQ  
Vi(p-p)  
Vsens(p-p)  
VIO  
input voltage (peak-to-peak) (2)(3)  
input sensitivity (peak-to-peak) (2)(4)  
input offset voltage  
50 Ω measurement system  
7
200  
2.5  
0
450  
7
mV  
mV  
mV  
mV  
Ω
−
−3  
−600  
−
+3  
+250  
−
VI, VIQ  
Zi  
input voltages  
single ended input impedance(2)  
−200  
50  
Data and Clock outputs: DOUT, DOUTQ; DLOOP, DLOOPQ; COUT, COUTQ and CLOOP, CLOOPQ  
Vo(p-p)  
voltage swing (single ended)(6)  
voltage swing (single ended) (7)  
50 Ω measurement system 170  
200  
210  
400  
mV  
mV  
50  
−
VO, VOQ  
Zo  
output voltages  
−600  
−
0
mV  
single ended output impedance  
rise/fall time  
−
100  
−
Ω
tr, tf  
differential  
data outputs  
−
−
116  
54  
−
ps  
ps  
ps  
clock outputs  
−
td  
data to clock delay  
note 8  
50  
80  
110  
Output amplitude adjustment: AREF  
VAREF output amplitude reference voltage  
Power Control output: PC  
floating pin  
−110  
−100  
−90  
mV  
gm  
IO  
transconductance  
output current  
−84  
−60  
−42  
mA/V  
mA  
1
−
3.5  
Loop mode enable input: ENL  
VIL  
VIH  
LOW-level input voltage  
HIGH-level input voltage  
−
−
−
0.8  
V
V
2.0  
−
Phase lock and loss-of-signal indicators: LOCK and LOS  
VOL  
VOH  
HIGH-level output voltage  
LOW-level output voltage  
note 9  
note 9  
−0.6  
−
−
−
V
V
−
3.3  
1998 Feb 09  
11  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
SYMBOL  
ta  
PARAMETER  
LOS assert time  
CONDITIONS  
note 10  
MIN.  
TYP.  
0.1  
MAX.  
UNIT  
µs  
−
−
−
−
−
td  
LOS de-assert time  
10  
−
−
−
µs  
BERLOS  
LOS assert Bit Error Rate  
LOS de-assert Bit Error Rate  
5 10−2  
1 10−3  
BER  
BER  
PLL Characteristics  
tacq  
acquisition time  
CREF = 19.44 MHz  
CREF = 38.88 MHz  
STM1/OC3 mode  
f = 6.5 kHz  
−
−
50  
200  
200  
µs  
µs  
100  
(5)  
Jtol(p-p)  
jitter tolerance (peak-to-peak)  
1.5  
>5  
−
−
−
UI  
UI  
UI  
f = 65 kHz  
0.15  
0.15  
1.3  
0.8  
f = 1 MHz  
STM4/OC12 mode  
f = 25 kHz  
1.5  
>5  
−
−
−
−
−
−
UI  
UI  
UI  
UI  
UI  
bits  
f = 100 kHz  
0.7  
3
f = 250 kHz  
0.15  
0.15  
0.15  
−
1.3  
f = 1 MHz  
0.50  
0.35  
2000  
f = 5 MHz  
TDR  
transitionless data run  
note 6  
Notes  
1. Typical supply voltage for the voltage regulator is −4.5 V (see Fig.4).  
2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value. (true  
differential excitation)  
3. The specified input voltage range is the guaranteed and tested range for proper operation; BER <10-10  
.
4. An input sensitivity for BER <10-10 of 7 mVpp is guaranteed. Typical input sensitivity for BER <10-10 is 2.5mVpp.  
5. CML inputs are terminated internally using 50 Ω on-chip resistors to ground (GND).  
6. Output voltage range with default reference voltage on AREF (floating pin).  
7. Output voltage range with adjustment of voltage on AREF (see section “Output amplitude reference (AREF)”).  
8. Data to clock delay according to figure 7. Measured with 1010 data pattern, single ended output signals and rising  
edge of COUT to DOUT or CLOOP to DLOOP. Note that small deviations from specified value are possible if  
differentially measured.  
9. External 10 kΩ pull-up resistor to +3.3 V.  
10. LOS assert/de-assert timing and BER level are for indication only. The values are neither production tested nor  
guaranteed.  
11. Measured according ITU specification G.958 on the OM5800 STM4 demoboard.  
12. TDR is bitrate independent.  
1998 Feb 09  
12  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
CML INPUT  
CML OUTPUT  
V
I(max)  
GND  
GND  
V
O(max)  
V
V
IQH  
OQH  
V
V
OH  
IH  
V
V
i (p-p)  
o (p-p)  
V
V
V
IQL  
V
OQL  
OO  
IO  
V
V
OL  
IL  
V
V
O(min)  
I(min)  
MGK144  
Fig.5 Logic level symbol definitions for CML.  
GND  
COUT or  
CLOOP  
-200mV  
td  
GND  
-200mV  
DOUT or  
DLOOP  
Fig.6 Data to clock delay for CML outputs; COUT to DOUT or CLOOP to DLOOP.  
1998 Feb 09  
13  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)  
1.0E+0  
1.0E-1  
1.0E-2  
1.0E-3  
1.0E-4  
1.0E-5  
1.0E-6  
1.0E-7  
1.0E-8  
1.0E-9  
1.0E-10  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
Vin(p-p) in mV  
Fig.7 Bit Error Rate versus input signal on DI/DIQ in STM1 mode(155.52 Mbits/s).  
(A complementary input signal of the indicated value is applied to DI and DIQ).  
1998 Feb 09  
14  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)  
1.0E+0  
1.0E-1  
1.0E-2  
1.0E-3  
1.0E-4  
1.0E-5  
1.0E-6  
1.0E-7  
1.0E-8  
1.0E-9  
1.0E-10  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
Vin (p-p) in mV  
Fig.8 Bit Error Rate versus input signal on DI/DIQ in STM4 mode (622.08 Mbits/s).  
(A complementary input signal of the indicated value is applied to DI and DIQ..  
1998 Feb 09  
15  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)  
100  
10  
1
0.1  
10  
100  
1000  
10000  
Fig.9 Jitter Tolerance in STM4 mode (622.08 Mbits/s). Measured on OM5800 demoboard  
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)  
Fig.10 Output waveforms on Data and Clock outputs in STM4 mode (622.08 Mbits/s). (single ended)  
1998 Feb 09  
16  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
APPLICATION SCHEMATIC  
+3.3 V  
10 kΩ  
CAPUPQ  
15  
LOS  
39  
12  
+3.3 V  
10 kΩ  
100 nF  
100 nF  
16  
CAPDOQ  
LOCK  
DIN  
DOUT  
42  
43  
45  
46  
33  
34  
DINQ  
DOUTQ  
COUT  
PRE-  
AMP  
normal  
output  
DCSQ  
TZA3004HL  
COUTQ  
DLOOP  
6
7
3
4
DLOOPQ  
CLOOP  
loop  
output  
CREF  
21  
22  
38.88/19.44 MHz  
system clock  
CREFQ  
CLOOPQ  
ENL  
output  
select  
1
48  
30  
REF19  
REF39  
AREF  
9
SEL155  
V
EE  
24  
27,28  
25, 31  
37  
PC  
(1)  
V
GND  
EE  
17  
100  
nF  
β > 100  
2 Ω  
1
kΩ  
1
kΩ  
3.3  
nF  
1 µF  
2 Ω  
1 µH  
−4.5 V  
MGK142  
(1) All GND pins must be connected directly to the PCB ground plane (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47).  
Fig.11 Application diagram showing the TZA3004HL configured for 622.08 Mbits/s DCR mode (STM4/OC12).  
1998 Feb 09  
17  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
APPLICATION INFORMATION (POSITIVE SUPPLY)  
VCC  
CAPUPQ  
LOS  
39
15  
LOS  
100 nF  
100 nF  
10kΩ  
16  
CAPDOQ  
VCC  
LOCK  
12
LOCK  
10kΩ  
DIN  
DOUT  
DOUTQ  
COUT  
COUTQ  
DLOOP  
DLOOPQ  
CLOOP  
CLOOPQ  
42  
43  
45  
46  
6
7
3
4
1
48  
30  
33  
DINQ  
PRE-  
AMP  
34  
unused  
normal  
output  
=
output  
TZA3004HL  
main  
output  
loop  
output  
=
CREF  
CREFQ  
21  
22  
38.88/19.44 MHz  
s
y
s
t
e
m
c
lo  
c
k
ENL  
AREF  
SEL155  
output  
se ct  
le
REF19  
REF39  
VCC  
9
24  
V
VCC  
EE  
27,28  
25, 31  
37  
(1)  
V
PC  
GND  
EE  
17  
100  
nF  
β > 100  
VCC  
2 Ω  
1
1 µF  
2 Ω  
k
Ω
1 µH  
MGK142  
VCC VCC  
(1) All GND pins must be connected directly  
to the PCB +5V (VCC) plane (pins 2, 5, 8,  
10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38,  
41, 44 and 47).  
Fig.12 Application diagram showing the TZA3004HL configured for 622.08 Mbits/s positive supply application.  
Note that loopmode outputs are used as outputs. ENL=HIGH selects these outputs. ENL=LOW selects  
loopmode and normal mode outputs simultaneously.  
1998 Feb 09  
18  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
PACKAGE OUTLINE  
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm  
SOT313-2  
c
y
X
36  
25  
A
E
37  
24  
Z
E
e
H
E
A
2
A
(A )  
3
A
1
w M  
p
θ
pin 1 index  
b
L
p
L
13  
48  
detail X  
1
12  
Z
v M  
D
A
e
w M  
b
p
D
B
H
v M  
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 7.1  
0.17 0.12 6.9  
7.1  
6.9  
9.15 9.15  
8.85 8.85  
0.75  
0.45  
0.95 0.95  
0.55 0.55  
1.60  
mm  
0.25  
0.5  
1.0  
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
94-12-19  
97-08-01  
SOT313-2  
1998 Feb 09  
19  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
If wave soldering cannot be avoided, the following  
conditions must be observed:  
SOLDERING  
Introduction  
• A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave)  
soldering technique should be used.  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
situations reflow soldering is often used.  
• The footprint must be at an angle of 45° to the board  
direction and must incorporate solder thieves  
downstream and at the side corners.  
Even with these conditions, do not consider wave  
soldering LQFP packages LQFP48 (SOT313-2),  
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Reflow soldering  
Reflow soldering techniques are suitable for all LQFP  
packages.  
Maximum permissible solder temperature is 260 °C, and  
maximum duration of package immersion in solder is  
10 seconds, if cooled to less than 150 °C within  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
6 seconds. Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Several techniques exist for reflowing; for example,  
thermal conduction by heated belt. Dwell times vary  
between 50 and 300 seconds depending on heating  
method. Typical reflow temperatures range from  
215 to 250 °C.  
Repairing soldered joints  
Fix the component by first soldering two diagonally-  
opposite end leads. Use only a low voltage soldering iron  
(less than 24 V) applied to the flat part of the lead. Contact  
time must be limited to 10 seconds at up to 300 °C. When  
using a dedicated tool, all other leads can be soldered in  
one operation within 2 to 5 seconds between  
270 and 320 °C.  
Preheating is necessary to dry the paste and evaporate  
the binding agent. Preheating duration: 45 minutes at  
45 °C.  
Wave soldering  
Wave soldering is not recommended for LQFP packages.  
This is because of the likelihood of solder bridging due to  
closely-spaced leads and the possibility of incomplete  
solder penetration in multi-lead devices.  
1998 Feb 09  
20  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1998 Feb 09  
21  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
NOTES  
1998 Feb 09  
22  
Philips Semiconductors  
Objective specification  
SDH/SONET data and clock recovery unit  
STM1/4 OC3/12  
TZA3004HL  
NOTES  
1998 Feb 09  
23  
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© Philips Electronics N.V. 1998  
SCA57  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
425102/200/01/pp24  
Date of release: 1998 Feb 09  
Document order number: 9397 750 03271  
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TZA3004HL SDH/SONET data and clock recovery 09-Feb-98  
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