PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8Mx4
Crystal Oscillator: LVDS CLOCK OUTPUT
I C S 8 M x 4
LOW JITTER, HIGH FREQUENCY XTAL OSCILLATOR
• Stable, ultra low jitter, LVDS clock generation
• For Gigabit Ethernet, Fibre Channel, PCI-Express, other applications
• Clock output frequencies from 75 to 750 MHz
• One differential LVDS clock output
• Output Enable (OE) pin (tri-state – with ultra low current – when low)
• Small 6-pin 5 x 7 x 1.5mm SMT ceramic package
• Low profile package allows back-side PCB mounting
• Pb-free RoHS compliant (by default; no additional code required)
• 2.5V or 3.3V device power supply options
8Mx4
( T o p V ie w )
• Commercial (0 to +70 OC) and Industrial (-40 to +85 OC) temperatures
• Frequency stability of 50 or 100 ppm
(including initial accuracy, operating temperature variation,
supply voltage variation, load variation, reflow drift, and aging for 10 years)
6-pin CERHERMETIC 5 x 7 x 1.5mm SMT
• Low phase jitter < 1 ps rms maximum (12kHz to 20MHz)
ELECTRICAL SPECIFICATIONS
Unless stated otherwise, VDD = 2.5 Volts + 5% or 3.3 Volts + 5%, TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial)
Parameter
Min
Typ
Max
Unit
Conditions
DC CHARACTERISTICS
Power Supply Voltage
VDD
3.135
2.375
3.3
2.5
83
3.465
2.625
V
3.3V operation
2.5V operation
Power Supply
(VDD , VEE pins)
V
in 8MJ4 and 8MK4 only
Power Supply Current
IEE
mA
mA
pF
V
OE = VDD
OE = GND
Current with Output Disable IOED
<0.6
Input Capacitance
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Internal Pull-up Resistor
CIN
VIH
4
0.7 x VDD
-150
Output Enable
(OE pin)
LVCMOS/LVTTL
VIL
0.3 x VDD
V
IIH
5
µA
µA
kΩ
VDD = VIN = 2.625 or 3.465V
IIL
VDD = 2.625 or 3.465V, VIN = 0V
RPULLUP
51
VOD
350
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
Clock Output
Level
(OUT, nOUT)
LVDS
100Ω terminatation between OUT and nOUT.
∆ VOD
VOS
50
See PARAMETER MEASUREMENT INFORMATION.
1.25
VOS Magnitude Change
∆ VOS
150
mV
AC CHARACTERISTICS
Output Frequency Range
75
750
±100
±50
MHz
All conditions
Output
(OUT, nOUT)
Frequency Stability error
∆f/fO
Includes frequency set,
VDD, TA & load variation,
reflow drift, 10 yr. aging
ppm p-p
in 8MH4 and 8MK4
ppm p-p
%
in 8MG4 and 8MJ4
Output Duty Cycle
Output Rise Time
Output Fall Time
odc
tR
50
See Output Duty Cycle diagram
and Rise and Fall Time diagram
in PARAMETER MEASUREMENT
INFORMATION.
600
600
10
ps
20% to 80% of VOD
20% to 80% of VOD
tF
ps
tOSC
ms
Time at Min. VDD (3.135V or 2.375V) to be 0s
(design target
Oscillator Start-up Time
RMS Phase Jitter, (Random) 1
< 1
design target
ps rms
)
t jit(Ø)
1
Deterministic
0.2
3
ps
ps
ps
ps
ps
tDS
Jitter
2
Random
σ
σ
of Random jitter
tRS
2
Root Mean Square
Peak to Peak
Accumulated Jitter
of Total jitter distribution
3
tRMS
2
25
4
tP-P
2
n = 2 to 50,000 cycles
tacc
Note 1: Measured using an Aeroflex PN9500 with a 12 kHz to 20MHz integration range.
Note 2: Measured using a Wavecrest SIA-3000.
SUPPLY VOLTAGE & FREQUENCY ACCURACY
G
H
J
=
=
=
=
3.3V
±50 ppm
± 100 ppm
± 50 ppm
± 100 ppm
3.3V
2.5V / 3.3V
2.5V / 3.3V
K
ICS8Mx4 Datasheet Rev A
Revised 30Nov2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
