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HYS72V32300GU-7.5

型号：

HYS72V32300GU-7.5

品牌：

INFINEON[ Infineon ]

页数：

19 页

PDF大小：

130 K

下载PDF手册
HYS 64/72V32300GU  
SDRAM-Modules  
3.3 V 32M × 64/72-Bit SDRAM Modules  
168-pin Unbuffered DIMM Modules  
• 168 Pin unbuffered 8 Byte Dual-In-Line  
SDRAM Modules for PC main memory  
applications  
• Single + 3.3 V (± 0.3 V) power supply  
• Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
• PC100 and PC133 versions  
• One bank 32M × 64 and 32M × 72  
• Auto Refresh (CBR) and Self Refresh  
• Decoupling capacitors mounted on substrate  
• All inputs, outputs are LVTTL compatible  
• Serial Presence Detect with E2PROM  
organisation  
• Optimized for byte-write non-parity or ECC  
applications  
• Fully PC board layout compatible to INTEL’s  
Rev. 1.0 module specification  
• Uses Infineon 256 Mbit SDRAM components  
in 32M × 8 organization and TSOPII-54  
packages  
• JEDEC standard Synchronous DRAMs  
(SDRAM)  
• Gold contact pads, card size:  
• Programmed Latencies:  
133.35 mm × 31.75 mm × 4.00 mm  
Product Speed  
CL tRCD  
tRP  
3
-7.5  
-8  
PC133  
3
2
3
3
3
2
2
2
PC100  
PC100  
PC100  
2
-8A  
-8B  
2
3
• SDRAM Performance:  
-7.5  
-8  
-8A  
PC100  
100  
6
-8B  
PC100  
100  
6
Unit  
PC133  
133  
PC100  
100  
6
fCK  
tAC  
Clock Frequency (max.)  
Clock Access Time  
MHz  
ns  
5.4  
The HYS 64V32300 and HYS 72V32300 are industry standard 168-pin 8-byte Dual in-line Memory  
Modules (DIMMs) which are organized as 32M × 64 and 32M × 72 in 1 memory bank high speed  
memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC  
applications. The DIMMs use -7.5 speed sorted 32M × 8 SDRAM devices in TSOP54 packages to  
meet the PC133 requirement and -8,-8A & -8B components for the standard PC100 applications.  
Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s  
PC100 module specification. The DIMMs have a serial presence detect, implemented with a serial  
E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer  
and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high  
performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm) height.  
Data Book  
1
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
Ordering Information  
Type  
Code  
Package  
Descriptions  
Module  
Height  
HYS 64V32300GU-7.5  
HYS 72V32300GU-7.5  
HYS 64V32300GU-8  
HYS 72V32300GU-8  
HYS 64V32300GU-8A  
HYS 72V32300GU-8A  
HYS 64V32300GU-8B  
HYS 72V32300GU-8B  
PC133-333-520 L-DIM-168-33 PC133 32M × 64 1 bank 1.25“  
SDRAM module  
PC133-333-520 L-DIM-168-33 PC133 32M × 72 1 bank 1.25“  
SDRAM module  
PC100-222-620 L-DIM-168-33 PC100 32M × 64 1 bank 1.25“  
SDRAM module  
PC100-222-620 L-DIM-168-33 PC100 32M × 72 1 bank 1.25“  
SDRAM module  
PC100-222-620 L-DIM-168-33 PC100 32M × 64 1 bank 1.25“  
SDRAM module  
PC100-222-620 L-DIM-168-33 PC100 32M × 72 1 bank 1.25“  
SDRAM module  
PC100-323-620 L-DIM-168-33 PC100 32M × 64 1 bank 1.25“  
SDRAM module  
PC100-323-620 L-DIM-168-33 PC100 32M × 72 1 bank 1.25“  
SDRAM module  
Note: All part numbers end with a place code (not shown), designating the die revision. Consult  
factory for current revision. Example: HYS 64V32300GU-8-A, indicating Rev. A dies are  
used for SDRAM components.  
Data Book  
2
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
Pin Definitions and Functions  
A0 - A12  
Address Inputs  
Bank Selects  
CLK0 - CLK3  
Clock Input  
BA0, BA1  
DQMB0 - DQMB7 Data Mask  
DQ0 - DQ63 Data Input/Output  
CS0 - CS3  
Chip Select  
CB0 - CB7  
RAS  
Check Bits (x72 organisation only) VDD  
Power (+ 3.3 V)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
VSS  
CAS  
SCL  
SDA  
Clock for Presence Detect  
WE  
Serial Data Out for  
Presence Detect  
CKE0, CKE1 Clock Enable  
N.C./DU  
No Connection  
Address Format  
Part Number  
Rows Columns Bank Select Refresh Period Interval  
32M × 64/72 HYS64/72V32300GU 13  
10  
2
8k  
64 ms 7.8 µs  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
VSS  
2
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DU  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
CKE0  
CS3  
3
CS2  
4
DQMB2  
DQMB3  
DU  
DQMB6  
DQMB7  
N.C.  
5
6
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
VDD  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
VDD  
8
N.C.  
N.C.  
9
N.C.  
N.C.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
N.C. (CB2)  
N.C. (CB3)  
VSS  
CB6  
CB7  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
DQ16  
DQ17  
DQ18  
DQ19  
VDD  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
DQ48  
DQ49  
DQ50  
DQ51  
VDD  
DQ20  
DQ52  
Data Book  
3
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
Pin Configuration (cont’d)  
PIN# Symbol PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
DQ14  
DQ15  
N.C. (CB0)  
N.C. (CB1)  
VSS  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
N.C.  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
DQ46  
DQ47  
N.C. (CB4)  
N.C. (CB5)  
VSS  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
N.C.  
DU  
DU  
CKE1  
VSS  
N.C.  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
WE  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQMB0  
DQMB1  
CS0  
DU  
RAS  
VSS  
VSS  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
CLK2  
N.C.  
A9  
CLK3  
N.C.  
SA0  
A10  
BA0  
BA1  
WP  
A11  
VDD  
SDA  
SCL  
VDD  
SA1  
VDD  
CLK1  
A12  
SA2  
CLK0  
VDD  
VDD  
Note: Pin names in parantheses are for the x72 ECC versions; example: Pin 106 = (CB5)  
Data Book  
4
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
WE  
CS0  
CS  
DQM  
WE  
CS  
DQM  
WE  
DQMB0  
DQ(7:0)  
DQMB4  
DQ0-DQ7  
DQ(39:32)  
DQ0-DQ7  
D0  
D4  
CS  
DQM  
WE  
CS  
DQM  
WE  
DQMB1  
DQMB5  
DQ(15:8)  
DQ0-DQ7  
DQ(47:40)  
DQ0-DQ7  
D1  
D5  
CS  
WE  
DQM  
CB(7:0)  
CS2  
DQ0-DQ7  
D8  
CS  
DQM  
WE  
CS  
DQM  
WE  
DQMB2  
DQMB6  
DQ(23:16)  
DQ0-DQ7  
DQ(55:48)  
DQ0-DQ7  
D2  
D6  
CS  
DQM  
WE  
CS  
DQM  
WE  
DQMB3  
DQMB7  
DQ(31:24)  
DQ0-DQ7  
DQ(63:56)  
DQ0-DQ7  
D3  
D0-D7, (D8)  
D7  
E2PROM (256 Word x 8 Bit)  
A0-A11, (A12), BA0, BA1  
VCC  
SA0  
SA0  
SA1  
SA2  
SCL  
SA1  
SA2  
SCL  
SDA  
WP  
D0-D7, (D8)  
D0-D7, (D8)  
D0-D7, (D8)  
D0-D7, (D8)  
D0-D7, (D8)  
C
VSS  
47 k  
Ω
RAS  
CAS  
CKE0  
Clock Wiring  
32 M x 64  
32 M x 72  
5 SDRAM  
Termination  
4 SDRAM + 3.3 pF  
Termination  
CLK0  
4 SDRAM + 3.3 pF  
Termination  
4 SDRAM + 3.3 pF  
Termination  
CLK1  
CLK2  
CLK3  
Note: D8 is only used in the x72 ECC version.  
SPB03970  
Block Diagram: 32M × 64/72 One Bank SDRAM DIMM Modules  
Data Book  
5
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
V
DD + 0.3  
V
Input Low Voltage  
– 0.5  
2.4  
0.8  
–
V
Output High Voltage (IOUT = – 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
–
0.4  
40  
V
Input Leakage Current, any input  
– 40  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
– 40  
40  
µA  
(DQ is disabled, 0 V < VOUT < VDD)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
max.  
32M × 64  
32M × 72  
Input Capacitance  
CI1  
65  
72  
pF  
(A0 to A11, BA0, BA1, RAS, CAS, WE)  
Input Capacitance (CS0 - CS3)  
Input Capacitance (CLK0 - CLK3)  
Input Capacitance (CKE0, CKE1)  
Input Capacitance (DQMB0 - DQMB7)  
CI2  
CICL  
CI3  
CI4  
CIO  
32  
38  
65  
13  
10  
40  
40  
72  
13  
10  
pF  
pF  
pF  
pF  
pF  
Input/Output Capacitance  
(DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0-2)  
Input/Output Capacitance  
CSC  
CSD  
8
8
8
8
pF  
pF  
Data Book  
6
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
Operating Currents per SDRAM Component 1)  
TA = 0 to 70 oC, VDD = 3.3 V ± 0.3 V  
(Recommended Operating Conditions unless otherwise noted)  
Parameter  
Test  
Symbol -7.5 -8/-8A/-8B Unit Note  
Condition  
max.  
2)  
Operating current  
–
ICC1  
270 210  
mA  
tRC = tRCMIN., tCK = tCKMIN.  
Outputs open, Burst Length = 4, CL = 3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
2)  
2)  
Precharge stand-by current  
in Power Down Mode  
t
CK = min.  
CK = min.  
ICC2P  
2
2
mA  
mA  
CS = VIH(MIN.), CKE ≤ VIL(MAX.)  
Precharge Stand-by Current  
in Non-Power Down Mode  
t
ICC2N  
25 19  
CS = VIH (MIN.), CKE ≥ VIH(MIN.)  
2)  
2)  
No operating current  
CKE ≥ VIH(MIN.) ICC3N  
CKE ≤ VIL(MAX.) ICC3P  
50 45  
10 10  
mA  
mA  
tCK = min., CS = VIH(MIN.),  
active state (max. 4 banks)  
2), 3)  
Burst operating current  
–
–
ICC4  
ICC5  
ICC6  
80 70  
140 130  
2.5 2.5  
mA  
mA  
mA  
tCK = min.,  
Read command cycling  
2)  
Auto refresh current  
tCK = min.,  
Auto Refresh command cycling  
2)  
Self refresh current  
Self Refresh Mode, CKE = 0.2 V  
Notes  
1. All values are shown per one SDRAM component.  
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation  
frequency for -7.5 and at 100 MHz for -8, -8A and -8B modules.  
Input signals are changed once during tCK, excepts for ICC6 and for stand-by currents when  
t
CK = infinity.  
3. These parameters are measured with continuous data stream during read access and all DQ  
toggling. CL = 3 and BL = 4 are assumed and the VDDQ current is excluded.  
Data Book  
7
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
1), 2)  
AC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-7.5  
-8  
PC133-333  
PC100-222  
min.  
max.  
min.  
max.  
Clock and Access Time  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
tCK  
fCK  
tAC  
–
7.5  
12  
–
–
10  
10  
–
–
ns  
ns  
System Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
MHz  
–
–
133  
83  
–
–
100  
100  
MHz  
2), 3)  
Clock Access Time  
CAS Latency = 3  
CAS Latency = 2  
–
–
5.4  
6
–
–
6
6
ns  
ns  
4)  
Clock High Pulse Width  
Clock Low Pulse Width  
tCH  
tCL  
2.5  
2.5  
–
–
3
3
–
–
ns  
4)  
ns  
Setup and Hold Parameters  
Input Setup Time  
5)  
tIS  
1.5  
0.8  
–
–
–
1
–
–
–
2
1
–
1
2
1
–
–
1
–
–
–
ns  
5)  
Input Hold Time  
tIH  
tSB  
ns  
6)  
Power Down Mode Entry Time  
CLK  
7)  
Power Down Mode Exit Setup Time tPDE  
1
CLK  
Mode Register Setup Time  
Transition Time (rise and fall)  
tRSC  
tT  
2
CLK  
1
ns  
–
Common Parameters  
RAS to CAS Delay  
Precharge Time  
tRCD  
tRP  
tRAS  
tRC  
20  
20  
45  
67.5  
15  
1
–
20  
20  
50  
70  
16  
1
–
ns  
–
–
–
–
–
–
–
–
ns  
Active Command Period  
Cycle Time  
100k  
100k  
ns  
–
–
–
–
–
–
ns  
Bank to Bank Delay Time  
tRRD  
ns  
CAS to CAS Delay Time (same bank) tCCD  
CLK  
Data Book  
8
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
AC Characteristics (cont’d) 1), 2)  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-7.5  
-8  
PC133-333  
PC100-222  
min.  
max.  
min.  
max.  
Refresh Cycle  
Refresh Period (8192 cycles)  
Self Refresh Exit Time  
tREF  
–
1
64  
–
–
1
64  
–
ms  
–
8)  
tSREX  
CLK  
Read Cycle  
2)  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns  
Data Out to Low Impedance  
Data Out to High Impedance  
DQM Data Out Disable Latency  
ns  
–
9)  
tHZ  
ns  
tDQZ  
CLK  
–
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
CLK  
CLK  
–
–
DQM Write Mask Latency  
tDQW  
Data Book  
9
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
1), 2)  
AC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-8A  
-8B  
PC100-322  
PC100-323  
min.  
max.  
min.  
max.  
Clock and Clock Enable  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
tCK  
fCK  
tAC  
–
10  
12  
–
–
10  
15  
–
–
ns  
ns  
System Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
MHz  
–
–
100  
83  
–
–
100  
66  
MHz  
2), 3)  
Access Time from Clock  
CAS Latency = 3  
–
–
6
6
–
–
6
7
ns  
ns  
CAS Latency = 2  
4)  
Clock High Pulse Width  
Clock Low Pulse Width  
tCH  
tCL  
3
3
–
–
3
3
–
–
ns  
4)  
ns  
Setup and Hold Times  
Input Setup Time  
5)  
tIS  
2
–
2
–
ns  
5)  
Input Hold Time  
tIH  
tSB  
1
–
1
–
ns  
6)  
Power Down Mode Entry Time  
–
1
–
1
CLK  
7)  
Power Down Mode Exit Setup Time tPDE  
1
–
1
–
CLK  
Mode Register Setup Time  
Transition Time  
tRSC  
tT  
2
–
2
–
CLK  
ns  
–
–
0.5  
10  
0.5  
10  
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
5)  
5)  
5)  
5)  
5)  
tRCD  
tRP  
tRAS  
tRC  
20  
20  
50  
70  
16  
–
20  
30  
60  
80  
20  
–
ns  
ns  
ns  
ns  
ns  
–
–
100k  
100k  
Row Cycle Time  
–
–
–
–
Activate (a) to Activate (b) Command tRRD  
Period  
CAS(a) to CAS(b) Command Period tCCD  
1
–
1
–
CLK  
–
Data Book  
10  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
AC Characteristics (cont’d) 1), 2)  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-8A  
-8B  
PC100-322  
PC100-323  
min.  
max.  
min.  
max.  
Refresh Cycle  
Refresh Period (8192 cycles)  
Self Refresh Exit Time  
tREF  
–
64  
–
–
64  
–
ms  
ns  
–
8)  
tSREX  
10  
10  
Read Cycle  
2)  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
8
2
3
0
3
–
–
ns  
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
–
ns  
–
9)  
tHZ  
10  
2
ns  
tDQZ  
CLK  
–
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
CLK  
CLK  
–
–
DQM Write Mask Latency  
tDQW  
Data Book  
11  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
Notes  
1. All AC characteristics are shown for device level.  
An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must  
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation  
can begin.  
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters  
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/  
ns edge rate between 0.8 V and 2.0 V.  
3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns must be added to this parameter.  
4. Rated at 1.4 V.  
5. If tT is longer than 1 ns, a time (tT − 1) ns must be added to this parameter.  
6. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh  
commands must be given to “wake-up” the device.  
7. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal  
is assumed latched on the next cycle.  
8. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
9. This is referenced to the time at which the output achieved the open circuit condition, not to  
output voltage levels.  
tCH  
2.4 V  
0.4 V  
CLOCK  
tT  
tCL  
tHOLD  
tSETUP  
INPUT  
1.4 V  
tAC  
tAC  
I/O  
tLZ  
tOH  
50 pF  
OUTPUT  
1.4 V  
Measurement conditions for  
AC and tOH  
tHZ  
t
SPT03404  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information  
about the module configuration, speed, etc. is written into the E2PROM device during module  
production using a serial presence detect protocol (I2C synchronous 2-wire bus).  
Data Book  
12  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
SPD-Table for PC133 Modules  
Byte# Description  
SPD Entry Value  
Hex  
32M × 64 32M × 72  
-7.5  
80  
08  
04  
0D  
0A  
-7.5  
80  
08  
04  
0D  
0A  
0
1
2
3
4
Number of SPD Bytes  
Total Bytes in Serial PD  
Memory Type  
128  
256  
SDRAM  
Number of Row Addresses (without BS bits) 13  
Number of Column Addresses (for  
8M × 8 SDRAMs)  
10  
5
Number of DIMM Banks  
Module Data Width  
1
01  
40  
00  
01  
75  
54  
00  
01  
48  
00  
01  
75  
54  
02  
82  
08  
08  
01  
6
64/72  
0
7
Module Data Width (cont’d)  
Module Interface Levels  
SDRAM Cycle Time at CL = 3  
8
LVTTL  
7.5 ns  
9
10  
11  
12  
13  
14  
15  
SDRAM Access Time from Clock at CL = 3 5.4 ns  
DIMM Config  
none/ECC  
Refresh Rate/Type  
Self-Refresh, 7.8 µs 82  
SDRAM Width, Primary  
x8  
08  
00  
01  
Error Checking SDRAM Data Width  
Minimum Clock Delay for Back-to-Back  
Random Column Address  
Burst Length Supported  
n/a/x8  
tCCD = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
1, 2, 4 & 8  
4
0F  
04  
0F  
04  
06  
01  
01  
00  
0E  
C0  
60  
Number of SDRAM Banks  
Supported CAS Latencies  
CS Latencies  
CAS latency = 2 & 3 06  
CS latency = 0  
01  
01  
WE Latencies  
Write latency = 0  
SDRAM DIMM Module Attributes  
SDRAM Device Attributes: General  
Min. Clock Cycle Time at CAS Latency = 2  
Max. Data Access Time from Clock for  
CL = 2  
non buffered/non reg. 00  
V
12.0 ns  
6.0 ns  
DD tol +/– 10%  
0E  
C0  
60  
25  
26  
Minimum Clock Cycle Time at CL = 1  
not supported  
FF  
FF  
FF  
FF  
Maximum Data Access Time from Clock at not supported  
CL = 1  
27  
28  
Minimum Row Precharge Time  
Minimum Row Active to Row Active Delay  
tRRD  
20 ns  
15 ns  
14  
0F  
14  
0F  
29  
30  
31  
32  
33  
Minimum RAS to CAS Delay tRCD  
Minimum RAS Pulse Width tRAS  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
20 ns  
14  
2D  
40  
15  
08  
14  
2D  
40  
15  
08  
45 ns  
256 MByte  
1.5 ns  
0.8 ns  
Data Book  
13  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
SPD-Table for PC133 Modules (cont’d)  
Byte# Description  
SPD Entry Value  
Hex  
32M × 64 32M × 72  
-7.5  
15  
08  
FF  
12  
56  
XX  
-7.5  
15  
08  
FF  
12  
68  
XX  
34  
35  
SDRAM Data Input Hold Time  
SDRAM Data Input Setup Time  
1.5 ns  
0.8 ns  
62-61 Superset Information (may be used in future) –  
62  
63  
SPD Revision  
Revision 1.2  
Checksum for Bytes 0 - 62  
–
–
64-125 Manufacturers Information (optional)  
(FFH if not used)  
126  
Frequency Specification  
Support Details  
64  
64  
127  
–
–
AD  
FF  
AD  
FF  
128+  
Unused Storage Locations  
Data Book  
14  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
SPD-Table for PC100 Modules  
Byte# Description SPD Entry  
Hex  
Value  
0
1
Number of SPD  
Bytes  
128  
80  
08  
80  
08  
80  
08  
80  
08  
80  
08  
80  
08  
Total bytes in Serial 256  
PD  
2
3
Memory Type  
Number of Row  
Addresses (without  
BS bits)  
SDRAM  
13  
04  
04  
04  
04  
04  
04  
0D  
0D  
0D  
0D  
0D  
0D  
4
5
Number of Column 10  
Addresses (for  
32M × 8 SDRAMs)  
0A  
01  
0A  
01  
0A  
01  
0A  
01  
0A  
01  
0A  
01  
Number of DIMM  
Banks  
1
6
7
Module Data Width 64/72  
40  
40  
40  
48  
48  
48  
Module Data Width  
(cont’d)  
0
00  
00  
00  
00  
00  
00  
8
Module Interface  
Levels  
LVTTL  
01  
A0  
60  
01  
01  
A0  
60  
01  
A0  
60  
01  
A0  
60  
01  
A0  
60  
9
SDRAM Cycle Time 10.0 ns  
at CL = 3  
A0  
6.0  
10  
SDRAM Access  
Time from Clock at  
CL = 3  
6.0 ns  
11  
12  
DIMM Config  
none/ECC  
00  
00  
82  
00  
82  
02  
82  
02  
82  
02  
82  
Refresh Rate/Type Self-Refresh, 82  
7.8 µs  
13  
14  
15  
SDRAM Width,  
Primary  
x8  
08  
00  
08  
00  
01  
08  
00  
01  
08  
08  
01  
08  
08  
01  
08  
08  
01  
Error Checking  
SDRAM Data Width  
Minimum Clock  
Delay for Back-to-  
Back Random  
Column Address  
Burst Length  
n/a/x8  
tCCD = 1 CLK 01  
16  
17  
1, 2, 4 & 8  
4
0F  
04  
0F  
04  
0F  
04  
0F  
04  
0F  
04  
0F  
04  
Supported  
Number of SDRAM  
Banks  
Data Book  
15  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
SPD-Table for PC100 Modules  
Byte# Description SPD Entry  
Hex  
Value  
18  
19  
20  
21  
22  
23  
Supported CAS  
Latencies  
CAS  
latency = 2 &3  
06  
01  
06  
01  
01  
00  
0E  
F0  
06  
01  
01  
00  
0E  
F0  
06  
01  
01  
00  
0E  
A0  
06  
01  
01  
00  
0E  
F0  
06  
01  
01  
00  
0E  
F0  
CS Latencies  
CS  
latency = 0  
WE Latencies  
Write latency 01  
= 0  
SDRAM DIMM  
Module Attributes  
SDRAM Device  
non buffered/ 00  
non reg.  
V
DD tol  
0E  
Attributes: General +/– 10%  
Min. Clock Cycle  
Time at CAS  
10.0/15.0 ns A0  
Latency = 2  
24  
25  
26  
Max. Data Access  
Time from Clock for  
CL = 2  
6.0/7.0 ns  
60  
60  
FF  
FF  
70  
FF  
FF  
60  
FF  
FF  
60  
FF  
FF  
70  
FF  
FF  
Minimum Clock  
Cycle Time at  
CL = 1  
not supported FF  
not supported FF  
Maximum Data  
Access Time from  
Clock at CL = 1  
Minimum Row  
Precharge Time  
Minimum Row  
Active to Row Active  
Delay tRRD  
27  
28  
20/30 ns  
16/20 ns  
14  
10  
14  
14  
1E  
14  
14  
10  
14  
14  
1E  
14  
29  
30  
31  
32  
33  
34  
Minimum RAS to  
CAS Delay tRCD  
Minimum RAS Pulse 50/60 ns  
Width tRAS  
Module Bank  
20 ns  
14  
32  
40  
20  
10  
20  
14  
32  
40  
20  
10  
20  
14  
3C  
40  
20  
10  
20  
14  
32  
40  
20  
10  
20  
14  
32  
40  
20  
10  
20  
14  
3C  
40  
20  
10  
20  
256 MByte  
Density (per bank)  
SDRAM Input Setup 2 ns  
Time  
SDRAM Input Hold 1 ns  
Time  
SDRAM Data Input 2 ns  
Setup Time  
Data Book  
16  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
SPD-Table for PC100 Modules  
Byte# Description SPD Entry  
Hex  
Value  
35  
SDRAM Data Input 1 ns  
Hold Time  
62-61 Superset  
Information (may be  
10  
10  
10  
10  
10  
10  
–
FF  
FF  
FF  
FF  
FF  
FF  
used in future)  
62  
63  
SPD Revision  
Revision 1.2 12  
12  
12  
11  
12  
12  
FF  
12  
23  
Checksum for Bytes –  
0 - 62  
99  
XX  
64  
AF  
FF  
ED  
AB  
64-125 Manufacturers  
Information  
–
XX  
64  
XX  
64  
XX  
64  
XX  
64  
XX  
64  
126  
Frequency  
100 MHz  
Specification  
100 MHz Support  
Details  
127  
–
–
AD  
FF  
AD  
FF  
AF  
FF  
AD  
FF  
AD  
FF  
128+  
Unused Storage  
Locations  
Data Book  
17  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
Package Outlines  
L-DIM-168-33  
SDRAM DIMM Module Package  
HYM 64/72V32300GU  
133.35  
127.35  
4 max.  
*)  
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
91 x 1.27 = 115.57  
124 125  
66.68  
2
85 94  
95  
168  
3 min.  
Detail of Contacts  
*) on ECC modules only  
1±  
0.05  
1.27  
GLD09264  
Data Book  
18  
12.99  
HYS 64/72V32300GU  
SDRAM-Modules  
Change List:  
14.1.1999  
Input capacitances adjusted  
18.4.1999  
-8A speed sort added  
Infineon logo added  
SPD codes updated according to new 256M speedsorts  
12.5.99  
21.7.99  
Some ICC current values changed due to new inputs  
HYS64/72V32200GU changed to HYS64/72V32300GU due to the use of L-  
DIM168-33 instead of L-DIM168-30  
23.8.99  
6.9.99  
Byte 126 changed to 64h for PC133 modules  
Template from R&L  
29.9.99  
20.10.99  
2.12.99  
Some minor errors corrected  
CL=2 max. frequency for -7.5 modules changes to 83 MHz  
Some timing parameters according to INTEL’S PC133 specification  
Data Book  
19  
12.99  
厂商 型号 描述 页数 下载

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