HYS64T32000HDL / HYS64T64020HDL
Small Outline DDR2 SDRAM-Modules
4.3 IDD Measurement Conditions
( VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
Symbol
Parameter/Condition
Operating Current - One bank Active - Precharge
tRC = tRCmin; tCK =tCKmin. ; Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH
between valid commands.
IDD0
IDD1
Operating Current - One bank Active - Read - Precharge
One bank is accessed with tRCmin, BL = 4, tCK = tCKmin, AL = 0, CL = CLmin.;
Address and control inputs are SWITCHING,CS = HIGH between valid commands; lout = 0 mA.
Precharge Power-Down Current: all banks idle; power-down mode; CKE is LOW; tCK = tCKmin.; Data Bus inputs are
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
FLOATING.
Precharge Floating Standby Current: all banks idle; CS is LOW; CKE is HIGH; tCK = tCKmin.; Address and control
inputs are SWITCHING; Data Bus inputs are FLOATING.
Precharge Quiet Standby Current: all banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Address and control inputs
are STABLE; Data Bus inputs are FLOATING.
Active Power-Down Current: all banks open; CKE is LOW; Address and control inputs are STABLE; Data Bus inputs are
FLOATING. MRS A12 bit is set to “0”( Fast Power-down Exit);
Active Power-Down Current: all banks open; CKE is LOW; Address and control inputs are STABLE; Data Bus inputs are
FLOATING. MRS A12 bit is set to “1”( Slow Power-down Exit);
Active Standby Current: all banks open; CS is HIGH; CKE is HIGH; tRC = tRASmax; tCK = tCKmin.;
Address and control inputs are SWITCHING; Data Bus inputs are SWITCHING.
Operating Current - Burst Read: all banks active; continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.;
Address and control inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write: all banks active; continuous burst writes; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.;
Address and control inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
Burst Auto-Refresh Current: Refresh command at tRFC = tRFCmin, tCK = tCKmin, CS is HIGH between valid com-
mands
Distributed Auto-Refresh Current: Refresh command at tREFI; tCK = tCKmin, CS is HIGH between valid commands;
CKE is LOW except during tRFCmin.
Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and CK at 0V; tCK = tCKmin; Address and control inputs are
FLOATING;Data Bus inputs are FLOATING.
Operating Bank Interleave Read Current:
1. All bank interleaving with BL = 4; BL = 4, CL = CLmin.;tRCD = tRCDmin.; tRRD = tRRDmin.;AL = tRCD - 1, Iout = 0 mA.
Address and control inputs are stable during DESELECT; Data Bus inputs are SWITCHING.
2. Timing pattern:
IDD7
- DDR2 -400 (200Mhz, CL=3) : tck = 5 ns, BL = 4, tRCD = 3 * tck, AL = 2 * tck, tRC = 12 * tck
Read : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
- DDR2 -533 (266Mhz, CL=4) : tck = 3.7 ns, BL = 4, tRCD = 4 * tck, AL = 3 * tck, tRC = 16 * tck
Read
- DDR2 -667 (333Mhz, CL=4) : tck = 3 ns, BL = 4, tRCD = 4 * tck, AL = 3 * tck, tRC = 19 * tck
Read A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
:
Notes:
1. Definitions for IDD :
LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.);
STABLE is defined as inputs are stable at a HIGH or LOW level
FLOATING is defined as inputs are VREF
SWITCHING is defined as inputs are changing between HIGH and LOW every other clock for adress and control signals,
and inputs changing 50% of each data trasnfer for DQ signals.
2. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT
3. For two rank modules : For all active current measurements the other rank is in Precharge Power-Down Mode
4. IDD1, IDD4R, IDD4W and IDD7A current measurements are defined with the outputs disabled (Iout = 0 mA). To achive this on
module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command). For details see the
DDR2 component datasheets.
INFINEON Technologies
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4.03
