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A-S7C33512NTD36A-166BI

型号：

A-S7C33512NTD36A-166BI

品牌：

ALSC[ ALLIANCE SEMICONDUCTOR CORPORATION ]

页数：

22 页

PDF大小：

446 K

下载PDF手册
April 2004  
AS7C33512NTD32A  
AS7C33512NTD36A  
®
3.3V 512K × 32/36 SRAM with NTDTM  
Features  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 165-ball BGA package  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Organization: 524,288 words × 32 or 36 bits  
™1  
• NTD architecture for efficient bus operation  
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.4/3.8 ns  
• Fast OE access time: 3.4/3.8 ns  
• Fully synchronous operation  
• Flow-through or pipelined mode  
DDQ  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
1. NTDTM is a trademark of Alliance Semiconductor Corporation. All trade-  
marks mentioned in this document are the property of their respective owners.  
Logic block diagram  
19  
19  
A[18:0]  
Q
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
19  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
FT  
512K x 32/36  
SRAM  
LBO  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
275  
80  
Units  
ns  
Minimum cycle time  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166  
3.4  
300  
90  
MHz  
ns  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
40  
40  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 1 of 22  
Copyright © Alliance Semiconductor. All rights reserved.  
AS7C33512NTD32A/36A  
®
100-pin TQFP - top view  
NC/DQPc  
DQc0  
DQc1  
1
2
3
4
5
6
7
8
9
DQPb/NC  
DQb7  
DQb6  
V
DDQ  
V
SSQ  
DQb5  
DQb4  
DQb3  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
V
V
DDQ  
SSQ  
DQc2  
DQc3  
DQc4  
DQc5  
DQb2  
V
V
10  
11  
12  
SSQ  
SSQ  
DDQ  
V
V
DDQ  
DQc6  
DQc7  
FT  
V
DD  
NC  
TQFP 14 x 20mm  
DQb1  
DQb0  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
V
NC  
SS  
V
ZZ  
DD  
V
SS  
DQd0  
DQd1  
DQa7  
DQa6  
V
V
V
DDQ  
DDQ  
SSQ  
V
SSQ  
DQd2  
DQd3  
DQd4  
DQd5  
DQa5  
DQa4  
DQa3  
DQa2  
V
V
V
DQa1  
SSQ  
DDQ  
SSQ  
DDQ  
V
27  
28  
29  
30  
DQd6  
DQd7  
NC/DQPd  
DQa0  
DQPa/NC  
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36  
configuration.  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 2 of 22  
AS7C33512NTD32A/36A  
®
Pin and ball assignment  
165-ball BGA - top view  
1
2
3
4
5
6
7
8
9
10  
A
11  
NC  
A
B
C
D
E
F
NC  
A
CE0  
CE1  
BWc  
BWd  
BWb  
BWa  
CE2  
CLK  
CEN  
R/W  
ADV/LD  
OE  
A
A
NC  
A
A
NC  
DQPc  
DQc  
DQc  
DQc  
DQc  
FT  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
DQb  
DQb  
DQb  
DQb  
NC  
DQa  
DQa  
DQa  
DQa  
NC  
A
DQPb  
DQb  
DQb  
DQb  
DQb  
ZZ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DQc  
DQc  
DQc  
DQc  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
G
H
J
NC  
NC  
DQd  
DQd  
DQd  
DQd  
DQPd  
NC  
DQd  
DQd  
DQd  
DQd  
NC  
V
V
DQa  
DQa  
DQa  
DQa  
DQPa  
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
K
L
M
N
P
V
V
V
V
V
V
V
V
V
NC  
TDI  
TMS  
NC  
NC  
V
SS  
DDQ  
SS  
DDQ  
1
NC  
A
A
A1  
A0  
TDO  
TCK  
A
A
1
R
LBO  
NC  
A
A
A
A
A
A
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 3 of 22  
AS7C33512NTD32A/36A  
®
Functional Description  
The AS7C33512NTD32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory  
(SRAM) organized as 524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.  
™
This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD ) architecture, featuring an enhanced  
write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data,  
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,  
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce  
overall bandwidth for applications requiring random access or read-modify-write operations.  
™
NTD devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or  
one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read  
™
pipeline to clear. With NTD , write and read operations can be used in any order without producing dead bus cycles.  
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18  
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied  
to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for  
write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected  
by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write operations  
to be completed.  
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip  
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any  
device operations, including burst, can be stalled using the CEN=1, the clock enable input.  
The AS7C33512NTD32A/36A operates with a 3.3V ± 5% power supply for the device core (V ). DQ circuits use a separate  
DD  
power supply (V  
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package and  
DDQ  
165 BGA Ball Grid Array package.  
TQFP and BGA Capacitance  
Parameter  
Input capacitance  
I/O capacitance  
Symbol  
Test conditions  
V = 0V  
Min  
Max  
Unit  
pF  
C
-
-
5
7
IN  
in  
C
V = V = 0V  
pF  
I/O  
in  
out  
TQFP and BGA thermal resistance  
Description  
Conditions  
Symbol  
Typical  
40  
Units  
°C/W  
°C/W  
1–layer  
4–layer  
θJA  
θJA  
Thermal resistance  
(junction to ambient)1  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance,  
per EIA/JESD51  
22  
Thermal resistance  
θJC  
8
°C/W  
(junction to top of case)1  
1 This parameter is sampled  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 4 of 22  
AS7C33512NTD32A/36A  
®
Signal descriptions  
Signal  
CLK  
I/O Properties  
Description  
I
I
I
CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.  
CEN  
SYNC  
SYNC  
SYNC  
Clock enable. When de-asserted high, the clock input signal is masked.  
Address. Sampled when all chip enables are active and ADV/LD is asserted.  
Data. Driven as output when the chip is enabled and OE is active.  
A, A0, A1  
DQ[a,b,c,d] I/O  
CE0, CE1,  
CE2  
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.  
Are ignored when ADV/LD is high.  
I
SYNC  
Advance or Load. When sampled high, the internal burst address counter will increment in  
the order defined by the LBO input value. (refer to table on page 2) When low, a new  
address is loaded.  
ADV/LD  
R/W  
I
I
SYNC  
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE  
operation. Is ignored when ADV/LD is high.  
SYNC  
SYNC  
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE  
command and BURST WRITE.  
BW[a,b,c,d]  
OE  
I
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.  
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When  
STATIC  
LBO  
driven Low, device follows linear Burst order. This signal is internally pulled High.  
Selects Pipeline or Flow-through mode. When tied to VDD or left floating, enables Pipeline mode.  
STATIC  
FT  
I
When driven Low, enables single register Flow-through mode. This signal is internally pulled High.  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA  
TDO  
TDI  
O
I
SYNC  
only)  
SYNC  
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)  
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.  
(BGA only)  
TMS  
I
SYNC  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA  
only)  
TCK  
O
SYNC  
ZZ  
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.  
No connects.  
NC  
-
Burst order  
Interleaved burst order LBO = 1  
A1 A0 A1 A0 A1 A0 A1 A0  
Linear burst order LBO = 0  
A1 A0 A1 A0 A1 A0 A1 A0  
Starting address  
First increment  
Second increment  
Third increment  
0 0  
0 1  
1 0  
1 1  
0 1  
0 0  
1 1  
1 0  
1 0  
1 1  
0 0  
0 1  
1 1  
1 0  
0 1  
0 0  
Starting Address  
First increment  
Second increment  
Third increment  
0 0  
0 1  
1 0  
1 1  
0 1  
1 0  
1 1  
0 0  
1 0  
1 1  
0 0  
0 1  
1 1  
0 0  
0 1  
1 0  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 5 of 22  
AS7C33512NTD32A/36A  
®
Synchronous truth table[5,6,7,8,9]  
Address  
CE0 CE1 CE2 ADV/LD R/W  
BWn  
X
OE CEN source  
CLK  
Operation  
DQ  
High-Z  
High-Z  
High-Z  
High-Z  
Q
Notes  
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
NA  
NA  
NA  
NA  
L to H  
L to H  
L to H  
L to H  
DESELECT Cycle  
X
DESELECT Cycle  
X
DESELECT Cycle  
X
H
X
H
X
H
X
H
X
CONTINUE DESELECT Cycle  
READ Cycle (Begin Burst)  
READ Cycle (Continue Burst)  
1
X
External L to H  
Next L to H  
X
L
X
L
X
L
Q
1,10  
2
X
H
H
X
X
X
External L to H NOP/DUMMY READ (Begin Burst) High-Z  
X
L
X
L
X
Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10  
L
External L to H  
WRITE CYCLE (Begin Burst)  
D
D
3
X
L
X
L
X
L
L
Next L to H WRITE CYCLE (Continue Burst)  
1,3,10  
H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3  
1,2,3,  
10  
4
X
X
X
H
X
H
X
L
Next L to H WRITE ABORT (Continue Burst)  
High-Z  
-
X
X
X
X
X
X
X
H
Current L to H  
INHIBIT CLOCK  
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or  
more byte write signals are LOW.  
Notes:  
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial  
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.  
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a  
WRITE command is given, but no operation is performed.  
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE  
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.  
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will  
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.  
5 BWa enables WRITEs to byte “a” (DQa pins/balls); BWb enables WRITEs to byte “b” (DQb pins/balls); BWc enables WRITEs to byte “c” (DQc pins/  
balls); BWd enables WRITEs to byte “d” (DQd pins/balls).  
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.  
7 Wait states are inserted by setting CEN HIGH.  
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.  
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.  
10 The address counter is incremented for all CONTINUE BURST cycles.  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 6 of 22  
AS7C33512NTD32A/36A  
®
State diagram for NTD SRAM  
Burst  
Read  
Burs  
Read  
Burst  
Read  
Dsel  
Dsel  
Burst  
Burst  
Write  
Burst  
Burst  
Write  
Writ  
Absolute maximum ratings  
Parameter  
Power supply voltage relative to GND  
Input voltage relative to GND (input pins)  
Input voltage relative to GND (I/O pins)  
Power dissipation  
Symbol  
DD, VDDQ  
VIN  
Min  
–0.5  
–0.5  
–0.5  
–
Max  
+4.6  
Unit  
V
V
VDD + 0.5  
VDDQ + 0.5  
1.8  
V
VIN  
V
Pd  
W
Short circuit output current  
IOUT  
–
20  
mA  
oC  
oC  
oC  
Storage temperature (TQFP)  
Storage temperature (BGA)  
T
stg (TQFP)  
stg (BGA)  
Tbias  
–65  
–65  
–65  
+150  
T
+125  
Temperature under bias  
+135  
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional  
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to  
absolute maximum rating conditions may affect reliability.  
Recommended operating conditions at 3.3V I/O  
Parameter  
Supply voltage for inputs  
Supply voltage for I/O  
Ground supply  
Symbol  
VDD  
Min  
3.135  
3.135  
0
Nominal  
Max  
3.465  
3.465  
0
Unit  
V
3.3  
3.3  
0
VDDQ  
Vss  
V
V
Recommended operating conditions at 2.5V I/O  
Parameter  
Supply voltage for inputs  
Supply voltage for I/O  
Ground supply  
Symbol  
VDD  
Min  
3.135  
2.375  
0
Nominal  
Max  
3.465  
2.625  
0
Unit  
V
3.3  
2.5  
0
VDDQ  
Vss  
V
V
4/30/04, v 2.5  
Alliance Semiconductor  
P. 7 of 22  
AS7C33512NTD32A/36A  
®
DC electrical characteristics for 3.3V I/O operation  
Parameter  
Input leakage current1  
Output leakage current  
Sym  
Conditions  
Min  
-2  
Max  
Unit  
µA  
|ILI|  
VDD = Max, OV < VIN < VDD  
OE ≥ VIH, VDD = Max, OV < VOUT < VDDQ  
Address and control pins  
I/O pins  
2
2
|ILO  
|
-2  
µA  
2
VDD+0.3  
Input high (logic 1) voltage  
Input low (logic 0) voltage  
VIH  
VIL  
V
V
2
V
DDQ+0.3  
Address and control pins  
I/O pins  
-0.3  
-0.5  
2.4  
–
0.8  
0.8  
–
Output high voltage  
Output low voltage  
VOH  
VOL  
IOH = –4 mA, VDDQ = 3.135V  
IOL = 8 mA, VDDQ = 3.465V  
V
V
0.4  
1 FT, LBO, and ZZ pins and the 165 BGA JTAG pins (TMS, TDI, and TCK) have an internal pull-up or pull-down, and input leakage = ±10 µa.  
DC electrical characteristics for 2.5V I/O operation  
Parameter  
Input leakage current  
Output leakage current  
Sym  
Conditions  
VDD = Max, OV < VIN < VDD  
OE ≥ VIH, VDD = Max, OV < VOUT < VDDQ  
Address and control pins  
I/O pins  
Min  
-2  
Max  
Unit  
µA  
µA  
V
|ILI|  
2
2
|ILO  
|
-2  
1.7  
1.7  
-0.3*  
-0.3*  
1.7  
–
VDD+0.3  
Input high (logic 1) voltage  
Input low (logic 0) voltage  
VIH  
VIL  
V
DDQ+0.3  
V
Address and control pins  
I/O pins  
0.7  
0.7  
–
V
V
Output high voltage  
Output low voltage  
VOH  
VOL  
IOH = –4 mA, VDDQ = 2.375V  
IOL = 8 mA, VDDQ = 2.625V  
V
0.7  
V
*V min = -1.5 for pulse width less than 0.2 X t  
IL  
CYC  
IDD operating conditions and maximum limits  
Parameter  
Sym  
Conditions  
-166  
-133  
Unit  
Operating power supply  
current1(pipelined mode)  
ICC  
300  
275  
mA  
CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax  
IOUT = 0 mA  
,
ICC  
Operating power supply  
250  
230  
mA  
mA  
current1(flow-through mode)  
(FT)  
ISB  
Deselected, f = fMax, ZZ < VIL  
90  
40  
80  
40  
Deselected, f = 0, ZZ < 0.2V,  
all VIN ≤ 0.2V or ≥ VDD – 0.2V  
ISB1  
Standby power supply current  
Deselected, f = f , ZZ  
≥
V
– 0.2V,  
Max  
DD  
ISB2  
40  
40  
all VIN ≤ VIL or ≥ VIH  
1 I given with no output loading. I increases with faster cycle times and greater output loading.  
CC  
CC  
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Timing characteristics over operating range  
166  
133  
1
Parameter  
Clock frequency  
Sym Min Max Min Max  
Unit Notes  
F
–
166  
–
–
133  
–
MHz  
ns  
MAX  
CYC  
CYCF  
CD  
Cycle time (pipelined mode)  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6
7.5  
12  
–
Cycle time (flow-through mode)  
Clock access time (pipelined mode)  
Clock access time (flow-through mode)  
Output enable low to data valid  
Clock high to output low Z  
8.5  
–
–
–
ns  
3.4  
8.5  
3.4  
–
3.8  
10  
3.8  
–
ns  
–
–
ns  
CDF  
OE  
–
–
ns  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2,3,4  
2
LZC  
OH  
Data output invalid from clock high (pipelined mode)  
Data Output invalid from clock high (flow-through mode)  
Output enable low to output low Z  
Output enable high to output high Z  
Clock high to output high Z  
1.5  
3.0  
0
–
1.5  
3.0  
0
–
–
–
2
OHF  
LZOE  
HZOE  
HZC  
OHOE  
CH  
–
–
2,3,4  
2,3,4  
2,3,4  
–
3.4  
3.4  
–
–
3.8  
3.8  
–
–
–
Output enable high to invalid output  
Clock high pulse width  
0
0
2.4  
2.3  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
0.5  
1.5  
0.5  
–
2.4  
2.4  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
0.5  
1.5  
0.5  
–
5
5
Clock low pulse width  
–
–
CL  
Address and Control setup to clock high  
Data setup to clock high  
–
–
6
AS  
–
–
6
DS  
Write setup to clock high  
–
–
6, 7  
6, 8  
6
WS  
Chip select setup to clock high  
Address hold from clock high  
Data hold from clock high  
–
–
CSS  
–
–
AH  
–
–
6
DH  
Write hold from clock high  
–
–
6, 7  
6, 8  
6
WH  
Chip select hold from clock high  
Clock enable setup to clock high  
Clock enable hold from clock high  
ADV setup to clock high  
–
–
CSH  
CENS  
CENH  
ADVS  
ADVH  
–
–
–
–
6
–
–
6
ADV hold from clock high  
–
–
6
1 See “Notes” on page 19.  
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IEEE 1149.1 serial boundary scan (JTAG)  
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard  
1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would  
place an added delay in the critical speed path of the SRAM. The TAP controller functionality does not conflict with the  
operation of other devices using 1149.1 fully compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels.  
The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.  
Disabling the JTAG feature  
If the JTAG function is not being implemented, TCK should be tied to VSS, TMS and TDI can be left unconnected. At power-up, the device  
will come up in a reset state which will not interfere with the operation of the device. TDO should be left unconnected.  
TAP controller state diagram  
TAP controller block diagram  
TEST-LOGIC  
RESET  
1
0
0
1
SELECT  
DR-SCAN  
1
1
SELECT  
IR-SCAN  
RUN-TEST/  
IDLE  
Bypass Register  
0
Selection  
Circuitry  
Selection  
Circuitry  
2
1 0  
0
0
Instruction Register  
TDI  
TDO  
1
1
.
. .  
2
3130 29  
Identification Register  
1 0  
1 0  
CAPTURE-DR  
0
CAPTURE-IR  
0
x
. . . . .  
2
1
Boundary Scan Register  
SHIFT-DR  
1
0
SHIFT-IR  
1
0
1
1
EXIT1-IR  
0
EXIT1-DR  
0
TCK  
TMS  
TAP Controller  
PAUSE-IR  
1
PAUSE-DR  
1
0
0
1
x = 50 for x18 configuration, x = 69 for x36 configuration.  
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-IR  
UPDATE-DR  
1
0
1
0
Note: The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.  
Test access port (TAP)  
Test clock (TCK)  
The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Test mode select (TMS)  
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball  
unconnected if the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.  
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Test data-in (TDI)  
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The  
register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on  
loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if  
the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register.  
Test data-out (TDO)  
The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of  
the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of  
any register. (See the TAP Controller State Diagram.)  
Performing a TAP RESET  
You can perform a RESET by forcing TMS high (V ) for five rising edges of TCK. This RESET does not affect the  
DD  
operation of the SRAM and can be performed while the SRAM is operating.  
TAP registers  
Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/  
ball on the rising edge of TCK. Data is output on the TDO pin/ball on the falling edge of TCK.  
Instruction register  
You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the  
TDI and TDO pins/balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE  
instruction at power up and also if the controller is placed in a reset state, as described in the previous section.  
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow  
for fault isolation of the board-level series test data path.  
Bypass register  
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through  
the SRAM with minimal delay. The bypass register is set low (Vss) when the BYPASS instruction is executed.  
Boundary scan register  
The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has  
a 70-bit-long register and the x18 configuration has a 51-bit-long register.  
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The  
EXTEST, SAMPLE/RELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring.  
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on  
the SRAM package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is  
connected to TDO.  
Identification (ID) register  
The ID register has a vendor code and other information described in the Identification register definitions table. The ID  
register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in  
the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the  
Shift-DR state.  
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TAP instruction set  
Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes  
table. Three of these instructions are reserved and should not be used.  
Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the  
mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control  
signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or  
INTEST or the PRELOAD portion of SAMPLE/PRELOAD. Instead, it performs a capture of the I/O ring when these  
instructions are executed.  
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI  
and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To  
execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.  
EXTEST  
The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this  
SRAM TAP controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is  
loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the  
SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high-Z state. EXTEST is a mandatory 1149.1  
instruction. this device, therefore, is not compliant with 1149.1.  
IDCODE  
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test  
logic reset state. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It  
also places the instruction register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device  
when the TAP controller enters the Shift-DR state.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the  
TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high-Z state.  
SAMPLE/PRELOAD  
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction, but the PRELOAD portion of this instruction is not implemented in  
this device. The TAP controller, therefore, is not fully 1149.1 compliant.  
Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more  
than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the  
Capture-DR state, an input or output can undergo a transition. The TAP may then try to capture a signal while in transition  
(metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable  
results may not be possible.  
To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long  
enough to meet the TAP controller’s capture setup plus hold time (t plus t ). The SRAM clock input might not be captured  
CS  
CH  
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue,  
it is possible to capture all other signals and ignore the value of the CK and CK# captured in the bounder scan register.  
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not  
implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the  
same effect as the Pause-DR command.  
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BYPASS  
The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected  
together on a board. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR  
state, the bypass register is placed between TDI and TDO.  
Reserved  
Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.  
TAP timing diagram  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
THTH  
THTL  
TLTH  
Test Mode Select  
(TMS)  
t
t
MVTH THMX  
Test Data-In  
(TDI)  
t
TLOV  
TLOX  
t
t
DVTH  
THDX  
t
Test Data-Out  
(TDO)  
Undefined  
Don’t care  
TAP AC electrical characteristics  
o
o
For notes 1 and 2, +10 C ≤ T ≤ +110 C and +2.4V ≤ V ≤ +2.6V.  
J
DD  
Description  
Symbol Min Max Units  
Clock  
Clock cycle time  
Clock frequency  
Clock high time  
Clock low time  
Output Times  
t
100  
ns  
THTH  
f
10 MHz  
TF  
t
t
40  
40  
ns  
ns  
THTL  
TLTH  
TCK low to TDO unknown  
TCK low to TDO valid  
TDI valid to TCK high  
TCK high to TDI invalid  
Setup Times  
t
t
t
t
0
ns  
TLOX  
TLOV  
DVTH  
THDX  
20  
ns  
ns  
ns  
10  
10  
TMS setup  
t
t
10  
10  
ns  
ns  
MVTH  
1
Capture setup  
CS  
Hold Times  
TMS hold  
t
t
10  
10  
ns  
ns  
THMX  
1
Capture hold  
CH  
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1 tCS and tCH refer to the setup and hold time requirements of latching data  
from the boundary scan register.  
2 Test conditions are specified using the load in the figure TAP AC output  
load equivalent.  
TAP AC test conditions  
TAP AC output load equivalent  
1.25  
Input pulse levels. . . . . . . . . . . . . . . Vss to  
2.5V  
50Ω  
Input rise and fall times. . . . . . . . . . . . . . .  
1 ns  
TDO  
20pF  
Z =50  
O
Input timing reference levels. . . . . . . . . .  
3.3V VDD, TAP DC electrical characteristics and operating conditions  
o
o
(+10 C < T < +110 C and +3.135V < V < +3.465V unless otherwise noted)  
J
DD  
Description  
Conditions  
Symbol  
VIH  
Min  
2.0  
Max  
VDD + 0.3  
0.8  
Units  
V
Notes  
1, 2  
Input high (logic 1) voltage  
Input low (logic 0) voltage  
Input leakage current  
VIL  
-0.3  
-5.0  
V
1, 2  
0V ≤ V ≤ V  
ILI  
5.0  
µA  
IN  
DD  
Outputs disabled,  
0V ≤ V  
Output leakage current  
≤
ILO  
-5.0  
5.0  
µA  
IN  
V
(DQx)  
DDQ  
Output low voltage  
Output low voltage  
Output high voltage  
Output high voltage  
I
= 100µA  
= 2mA  
VOL1  
VOL2  
VOH1  
VOH2  
0.7  
0.8  
V
V
V
V
1
1
1
1
OLC  
I
I
I
OLT  
OHS  
OHT  
= -100µA  
= -2mA  
2.9  
2.0  
2.5V VDD, TAP DC electrical characteristics and operating conditions  
o
o
(+10 C < T < +110 C and +2.4V < V < +2.6V unless otherwise noted)  
J
DD  
Description  
Conditions  
Symbol  
VIH  
Min  
1.7  
Max  
VDD + 0.3  
0.7  
Units  
V
Notes  
1, 2  
Input high (logic 1) voltage  
Input low (logic 0) voltage  
Input leakage current  
VIL  
-0.3  
-5.0  
V
1, 2  
0V ≤ V ≤ V  
ILI  
5.0  
µA  
IN  
DD  
Outputs disabled,  
0V ≤ V  
Output leakage current  
≤
ILO  
-5.0  
5.0  
µA  
IN  
V
(DQx)  
DDQ  
Output low voltage  
Output low voltage  
Output high voltage  
Output high voltage  
I
= 100µA  
= 2mA  
VOL1  
VOL2  
VOH1  
VOH2  
0.2  
0.7  
V
V
V
V
1
1
1
1
OLC  
I
I
I
OLT  
OHS  
OHT  
= -100µA  
= -2mA  
2.1  
1.7  
1. All voltage referenced to V (GND).  
SS  
t
2. Overshoot: V (AC) ≤ V + 1.5V for t ≤ KHKH/2  
IH  
DD  
t
Undershoot:V (AC) ≥ -0.5 for t ≤ KHKH/2  
IL  
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Power-up:V ≤ +2.6V and V ≤ 2.4V and V  
≤ 1.4V for t ≤ 200ms  
IH  
DD  
DDQ  
During normal operation, V  
must not exceed V . Control input signals (such as LD, R/W, etc.) may not have pulsed  
DD  
DDQ  
widths less than t  
(Min) or operate at frequencies exceeding f (Max).  
KHKL  
KF  
Identification register definitions  
Instruction field  
Revision number (31:28)  
Device depth (27:23)  
512K x 32/36  
Description  
xxxx  
Reserved for version number.  
xxxxx/xxxxx Defines the depth of 512K words.  
xxxxx/xxxxx Defines the width of x32 or x36 bits.  
Device width (22:18)  
Device ID (17:12)  
xxxxxx  
Reserved for future use.  
JEDEC ID code (11:1)  
ID register presence indicator (0)  
00001010010 Allows unique identification of SRAM vendor.  
1
Indicates the presence of an ID register.  
Scan register sizes  
Register name  
Instruction  
Bit size  
3
1
Bypass  
ID  
32  
Boundary scan  
x18:51  
x36:70  
Instruction codes  
Instruction  
Code  
Description  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.  
EXTEST  
IDCODE  
000  
001  
Loads the ID register with the vendor ID code and places the register between TDI  
and TDO. This operation does not affect SRAM operations.  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a high-Z state.  
SAMPLE Z  
Reserved  
010  
011  
Do not use. This instruction is reserved for future use.  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation. This instruction does not implement 1149.1 preload  
function and is therefore not 1149.1-compliant.  
SAMPLE/  
PRELOAD  
100  
Reserved  
Reserved  
101  
110  
Do not use. This instruction is reserved for future use.  
Do not use. This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect  
SRAM operations.  
BYPASS  
111  
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165-ball BGA boundary exit order (x36)  
Bit #s  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
Signal Name  
R/W  
CEN  
OE  
Ball ID  
7B  
Bit #s  
1
Signal Name  
SA0  
SA1  
SA  
Ball ID  
6R  
6P  
7A  
2
8B  
3
4R  
4P  
ADV/LD  
SA  
8A  
4
SA  
10B  
9A  
5
SA  
3R  
3P  
SA  
6
SA  
SA  
10A  
9B  
7
LBO  
DQPd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
FT  
1R  
1N  
2M  
2L  
2K  
2J  
SA  
8
DQPb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
ZZ  
10C  
10D  
10E  
10F  
10G  
11D  
11E  
11F  
11G  
11H  
10J  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
1M  
1L  
1K  
1J  
1H  
2G  
2F  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQPc  
SA  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQPa  
SA  
10K  
10L  
10M  
11J  
2E  
2D  
1G  
1F  
11K  
11L  
11M  
11N  
8R  
1E  
1D  
1C  
2B  
2A  
3A  
3B  
4B  
5A  
4A  
5B  
6A  
6B  
SA  
SA  
11R  
10P  
10R  
9P  
CE0  
CE1  
BWd  
BWb  
BWc  
BWa  
CE2  
CLK  
SA  
SA  
SA  
SA  
9R  
SA  
8P  
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Key to switching waveforms  
Rising input  
Falling input  
Undefined/don’t care  
Timing waveform of read/write cycle  
tCH tCL  
tCYC  
CLK  
tCENS  
tCENH  
CEN  
CE1  
tCSS  
tCSH  
CE0, CE2  
tADVS  
tADVH  
ADV/LD  
tWS  
tWH  
R/W  
tWS  
tWH  
BWn  
tAS  
tAH  
A3  
A4  
A5  
A6  
A7  
A1  
A2  
ADDRESS  
tCD  
tLZC  
tDS tDH  
tOH  
tOE  
tHZC  
D/Q  
pipelined  
D(A5)  
Q(A6)  
D(A1)  
D(A2)  
Q(A3)  
Q(A4)  
Q(A4Ý01)  
D(A2Ý01)  
tHZOE  
tLZOE  
OE  
D/Q  
flow-through  
Q(A4Ý01)  
D(A5)  
Q(A6)  
Q(A7)  
D(A1)  
D(A2)  
D(A2Ý01)  
Q(A3)  
Q(A4)  
BURST  
READ  
Q(A4Ý01  
Command  
READ  
Q(A3)  
DSEL  
WRITE WRITE BURST  
D(A1) D(A2) WRITE  
D(A2Ý0  
WRITE READ WRITE  
D(A5) Q(A6) D(A7)  
READ  
Q(A4)  
Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:b] is don’t care.  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 17 of 22  
AS7C33512NTD32A/36A  
®
NOP, stall and deselect cycles  
CLK  
CEN  
CE1  
CE0, CE2  
ADV/LD  
R/W  
BWn  
A1  
A2  
A3  
Address  
Q(A1Ý01)  
Q(A1  
Ý10)  
D(A2)  
Q(A1)  
DQ  
pipelined  
Q(A1Ý01)  
Q(A1Ý10)  
Q(A1)  
D(A2)  
DQ  
flow-through  
Command  
BURST  
NOP  
WRITE  
NOP  
READ  
Q(A1)  
STALL  
DSEL  
BURST  
Q(A1 01  
BURST  
Q(A1 10  
BURST WRITE  
DSEL D(A2)  
BURST  
D(A2Ý10  
Ý
Ý
D(A2Ý0  
D(A3)  
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low.  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 18 of 22  
AS7C33512NTD32A/36A  
®
AC test conditions  
• Output load: For tLZC, tLZOE, tHZOE, and tHZC, see Figure C. For all others, see Figure B.  
• Input pulse level: GND to 3V. See Figure A.  
Thevenin equivalent:  
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.  
• Input and output timing reference levels: 1.5V.  
+3.3V for 3.3V I/O;  
/+2.5V for 2.5V I/O  
319  
Ω
/1667  
Ω
50  
Ω
DOUT  
353 /1538  
+3.0V  
VL = 1.5V  
for 3.3V I/O;  
= VDDQ/2  
DOUT  
5 pF*  
90%  
10%  
GND  
Figure A: Input waveform  
90%  
Ω
Ω
30 pF*  
10%  
GND  
*including scope  
and jig capacitance  
for 2.5V I/O  
Figure B: Output load (A)  
Figure C: Output load(B)  
Notes  
1) For test conditions, see “AC test conditions”, Figures A, B, and C  
2) This parameter measured with output load condition in Figure C.  
3) This parameter is sampled, but not 100% tested.  
4) tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.  
5) tCH is measured high above VIH, and tCL is measured low below VIL  
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must  
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.  
7) Write refers to R/  
W
and BW[a,b,c,d]  
.
8) Chip select refers to CE0  
,
CE1, and CE2.  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 19 of 22  
AS7C33512NTD32A/36A  
®
Package dimensions  
100-pin quad flat pack (TQFP)  
TQFP  
Hd  
D
Min  
0.05  
1.35  
0.22  
0.09  
Max  
0.15  
1.45  
0.38  
0.20  
A1  
A2  
b
b
e
c
D
13.90 14.10  
19.90 20.10  
0.65 nominal  
15.85 16.15  
21.80 22.20  
He  
E
E
e
Hd  
He  
L
0.45  
0.75  
L1  
α
1.00 nominal  
0°  
7°  
α
Dimensions in  
millimeters  
c
L1  
L
A1 A2  
165-ball BGA (ball grid array)  
Top  
Bottom  
A1 corner index  
1 2 3 4 5 6 7 8 9 1 1  
1 109 8 7 6 5 4 3 2 1  
A
B
C
A
B
C
A
B
D
D
E
E
All measurements are in mm.  
F
F
G
H
G
H
Min  
14.90  
12.90  
Typ  
1.00  
Max  
A
B
C
D
E
F
J
J
K
L
M
N
P
K
L
M
N
P
15.00 15.10  
14.00  
C
13.00 13.10  
10.00  
R
R
0.26  
1.0  
A
13.00±0.1  
D
G
H
I
0.30  
0.40  
0.35  
0.40  
1.20  
0.50  
10.0  
E
13.00±0.1  
D
0.45  
0.20  
G
H
0.12  
F
/ 0.45±0.05 (165X)  
Ø
Ø
Z XY  
M
Z
M
Detail of Solder  
Side  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 20 of 22  
AS7C33512NTD32A/36A  
®
Ordering information  
Package & Width  
–166  
–133  
AS7C33512NTD32A-166TQC  
AS7C33512NTD32A-166TQI  
AS7C33512NTD36A-166TQC  
AS7C33512NTD36A-166TQI  
AS7C33512NTD32A-166BC  
AS7C33512NTD32A-166BI  
AS7C33512NTD36A-166BC  
AS7C33512NTD36A-166BI  
AS7C33512NTD32A-133TQC  
AS7C33512NTD32A-133TQI  
AS7C33512NTD36A-133TQC  
AS7C33512NTD36A-133TQI  
AS7C33512NTD32A-133BC  
AS7C33512NTD32A-133BI  
AS7C33512NTD36A-133BC  
AS7C33512NTD36A-133BI  
TQFP x32  
TQFP x36  
BGA x32  
BGA x36  
Notes: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33512NTD32A-166TQCN)  
Part numbering guide  
AS7C  
33  
512  
NTD  
32/36  
A
–XXX  
TQ or B  
C/I  
X
1
2
3
4
5
6
7
8
9
10  
1. Alliance Semiconductor SRAM prefix  
2. Operating voltage: 33 = 3.3V  
3. Organization: 512 = 512k  
4. NTD™ = No Turn-Around Delay. Pipelined/flow-through mode (each device works in both modes)  
5. Organization: 32 = x 32, 36 = x 36  
6. Production version: A = first production version  
7. Clock speed (MHz)  
8. Package type: TQ = TQFP; B = BGA  
9. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)  
10. N = Lead free part  
4/30/04, v 2.5  
Alliance Semiconductor  
P. 21 of 22  
AS7C33512NTD32A/36A  
®
®
Alliance Semiconductor Corporation  
2575, Augustine Drive,  
Santa Clara, CA 95054  
Tel: 408 - 855 - 4900  
Copyright © Alliance Semiconductor  
All Rights Reserved  
Part Number:AS7C33512NTD32A/36A  
Document Version: v 2.5  
Fax: 408 - 855 - 4999  
www.alsc.com  
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered  
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make  
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this  
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or  
correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are  
possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not  
intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising  
out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance  
products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights,  
except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made  
exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent  
rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its  
products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant  
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and  
agrees to indemnify Alliance against all claims arising from such use.  
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