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Data Sheet, Rev. 1.2, Jan. 2004

HYS72D16500GR-[7/8]-A

HYS72D32501GR-[7/8]-A

Low Profile DDR SDRAM-Modules

DDR SDRAM

Memory Products

N e v e r s t o p t h i n k i n g .

The information in this document is subject to change without notice.

Edition 2004-06

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Data Sheet, Rev. 1.2, Jan. 2004

HYS72D16500GR-[7/8]-A

HYS72D32501GR-[7/8]-A

Low Profile DDR SDRAM-Modules

DDR SDRAM

Memory Products

N e v e r s t o p t h i n k i n g .

HYS72D16500GR-[7/8]-A HYS72D32501GR-[7/8]-A

Revision History:

Rev. 1.2

2004-06

Previous Version:

Rev. 1.01

2004-01

Page

23,24

8,19

Subjects (major changes since last revision)

changed Package outline drawing

Editorial change

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc.mp@infineon.com

Template: mp_a4_v2.3_2004-01-14.fm

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Table of Contents

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1

3.2

3.3

4

5

6

SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Sheet

5

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Overview

1

Overview

1.1

Features

•

184-pin Registered 8 Byte Dual-In-Line DDR SDRAM Module for PC and Server main memory applications

One rank 16M × 72 and 32M × 72 organization

JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single +2.5 V (± 0.2 V) power

supply

•

Built with 128 Mbit DDR SDRAMs in 66-Lead TSOPII package

Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

All inputs and outputs SSTL_2 compatible

Re-drive for all input signals using register and PLL devices.

Serial Presence Detect with E²PROM

JEDEC standard MO-206 form factor:

133.35 mm x 30,48 mm (1.2”) x 4.00 mm

(6,80 mm with stacked components)

•

JEDEC standard reference layout:

Raw Cards L and M

Gold plated contacts

Table 1

Performance -8/-7

Part Number Speed Code

–7

–8

Unit

—

Speed Grade

Component

Module

DDR266A

PC2100-2033

143

DDR200

PC1600-2022

125

—

max. Clock Frequency

@CL2.5

@CL2

f_CK2.5

f_CK2

MHz

133

100

1.2

Description

The HYS 72D××0×0GR are industry standard 184-pin 8 byte Dual in-line Memory Modules (DIMMs) organized as

16M × 72 (128 MB)and 32M × 72 (256 MB). The memory array is designed with Double Data Rate Synchronous

DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices

and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the

SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial

presence detect based on a serial E²PROM device using the 2-pin I²C protocol. The first 128 bytes are

programmed with configuration data and the second 128 bytes are available to the customer.

Data Sheet

6

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Overview

Table 2

Type

Ordering Information

Compliance Code

Description

SDRAM Technology

PC2100 (CL=2)

HYS72D16500GR-7-A

HYS72D32501GR-7-A

PC2100R-20330-L

PC2100R-20330-M

one rank 128 MB Reg. DIMM 128 Mbit (×8)

one rank 256 MB Reg. DIMM 128 Mbit (×4)

PC1600 (CL=2)

HYS72D16500GR-8-A

HYS72D32101GR-8-A

PC1600R-20220-L

PC1600R-20220-M

one rank 128 MB Reg. DIMM 128 Mbit (×8)

one rank 256 MB Reg. DIMM 128 Mbit (×4)

Note:All part numbers end with a place code (not shown), designating the silicon-die revision. Reference

information available on request. Example: HYS72D16500GR-8-A, indicating Rev. A die are used for

SDRAM components The Compliance Code is printed on the module labels and describes the speed sort

for example “PC2100R”, the latencies (for example “20330” means CAS latency = 2, t_RCDlatency = 3 and

t

_RPlatency = 3 ) and the Raw Card used for this module.

Data Sheet

7

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Pin Configuration

2

Pin Configuration

The pin configuration of the Registered DDR SDRAM Table 3

DIMM is listed by function in Table 3 (184 pins). The

abbreviations used in columns Pin and Buffer Type are

explained in Table 4 and Table 5 respectively. The pin

Pin Configuration of RDIMM (cont’d)

Buffer Function

Type Type

Pin# Name Pin

125 A6

I

SSTL Address Bus 11:0

numbering is depicted in Figure 1.

29

122 A8

27 A9

A7

SSTL

Table 3

Pin Configuration of RDIMM

SSTL

Pin# Name Pin

Buffer Function

Type Type

141 A10

AP

SSTL

Clock Signals

137 CK0

SSTL

I

SSTL Clock Signal

118 A11

115 A12

SSTL

138 CK0

SSTL Complement Clock

SSTL Clock Enable Rank 0

SSTL Clock Enable Rank 1

Note: 2-rank module

SSTL Address Signal 12

21

CKE0

Note: Module based on

256 Mbit or larger

dies

111 CKE1

NC

I

–

Note: 128 Mbit based

module

NC

SSTL Note: 1-rank module

Control Signals

167 A13

SSTL Address Signal 13

157 S0

158 S1

I

SSTL Chip Select of Rank 0

SSTL Chip Select of Rank 1

Note: 2-ranks module

Note: 1 Gbit

module

based

NC

–

Note: Module based on

NC

–

Note: 1-rank module

512 Mbit

or

smaller dies

154 RAS

I

SSTL Row Address Strobe

Data Signals

65

CAS

SSTL Column Address

Strobe

2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

I/O

SSTL Data Bus 63:0

SSTL

63

10

WE

I

SSTL Write Enable

4

RESET I

LV-

Register Reset

CMO Forces registered

6

SSTL

8

SSTL

S

inputs low

94

95

98

99

12

13

19

20

SSTL

Note: For

detailed

SSTL

description of the

Power Up and

Power

Management see

the Application

Note at the end of

data sheet

SSTL

DQ10 I/O

DQ11 I/O

SSTL

Address Signals

SSTL

59

52

48

43

41

BA0

BA1

A0

I

SSTL Bank Address Bus

105 DQ12 I/O

106 DQ13 I/O

109 DQ14 I/O

110 DQ15 I/O

SSTL

1:0

SSTL

SSTL Address Bus 11:0

SSTL

A1

SSTL

A2

23

24

28

31

DQ16 I/O

DQ17 I/O

DQ18 I/O

DQ19 I/O

SSTL

130 A3

SSTL

37

32

A4

A5

SSTL

Data Sheet

8

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Pin Configuration

Table 3

Pin Configuration of RDIMM (cont’d)

Table 3

Pin Configuration of RDIMM (cont’d)

Pin# Name Pin

Buffer Function

Pin# Name Pin

Buffer Function

Type Type

114 DQ20 I/O

117 DQ21 I/O

121 DQ22 I/O

123 DQ23 I/O

SSTL Data Bus 63:0

SSTL

174 DQ60 I/O

175 DQ61 I/O

178 DQ62 I/O

179 DQ63 I/O

SSTL Data Bus 63:0

SSTL

33

35

39

40

DQ24 I/O

DQ25 I/O

DQ26 I/O

DQ27 I/O

44

45

49

51

CB0

CB1

CB2

CB3

I/O

SSTL Check Bits 7:0

SSTL

126 DQ28 I/O

127 DQ29 I/O

131 DQ30 I/O

133 DQ31 I/O

134 CB4

135 CB5

142 CB6

144 CB7

SSTL

53

55

57

60

DQ32 I/O

DQ33 I/O

DQ34 I/O

DQ35 I/O

5

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

SSTL Data Strobes 8:0

Note: See

diagram

block

for

14

25

36

56

67

78

86

47

97

SSTL

corresponding

DQ signals

146 DQ36 I/O

147 DQ37 I/O

150 DQ38 I/O

151 DQ39 I/O

SSTL Data Strobes 8:0

SSTL

61

64

68

69

DQ40 I/O

DQ41 I/O

DQ42 I/O

DQ43 I/O

SSTL

DM0

DQS9 I/O

107 DM1

DQS10 I/O

I

SSTL Data Mask 0

Note: ×8 based module

SSTL Data Strobe 9

Note: ×4 based module

SSTL Data Mask 1

Note: ×8 based module

SSTL Data Strobe 10

Note: ×4 based module

SSTL Data Mask 2

Note: ×8 based module

SSTL Data Strobe 11

Note: ×4 based module

SSTL Data Mask 3

Note: ×8 based module

SSTL Data Strobe 12

Note: ×4 based module

153 DQ44 I/O

155 DQ45 I/O

161 DQ46 I/O

162 DQ47 I/O

I

72

73

79

80

DQ48 I/O

DQ49 I/O

DQ50 I/O

DQ51 I/O

119 DM2

I

DQS11 I/O

165 DQ52 I/O

166 DQ53 I/O

170 DQ54 I/O

171 DQ55 I/O

129 DM3

I

DQS12 I/O

83

84

87

88

DQ56 I/O

DQ57 I/O

DQ58 I/O

DQ59 I/O

Data Sheet

9

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Pin Configuration

Table 3

Pin# Name Pin

Type Type

SSTL Data Mask 4

Note: ×8 based module

SSTL Data Strobe 13

Note: ×4 based module

SSTL Data Mask 5

Note: ×8 based module

SSTL Data Strobe 14

Note: ×4 based module

SSTL Data Mask 6

Note: ×8 based module

SSTL Data Strobe 15

Note: ×4 based module

SSTL Data Mask 7

Note: ×8 based module

SSTL Data Strobe 16

Note: ×4 based module

SSTL Data Mask 8

Note: ×8 based module

SSTL Data Strobe 17

Note: ×4 based module

Pin Configuration of RDIMM (cont’d)

Table 3

Pin# Name Pin

Type Type

PWR –

Pin Configuration of RDIMM (cont’d)

Buffer Function

149 DM4

I

15, V_DDQ

22,

I/O Driver Power

Supply

30,

54,

62,

77,

DQS13 I/O

159 DM5

I

96,

104,

112,

128,

136,

143,

156,

164,

172,

180

DQS14 I/O

169 DM6

I

DQS15 I/O

177 DM7

I

7,

V_DD

PWR –

Power Supply

38,

46,

70,

85,

108,

120,

148,

168

DQS16 I/O

140 DM8

I

DQS17 I/O

EEPROM

3,

V_SS

GND

–

Ground Plane

11,

18,

26,

34,

42,

50,

58,

66,

74,

81,

89,

93,

100,

116,

124,

132,

139,

145,

152,

160,

176

92

SCL

I

CMO Serial Bus Clock

S

91

SDA

I/O

I

OD

Serial Bus Data

181 SA0

182 SA1

183 SA2

CMO Slave Address Select

S

Bus 2:0

I

CMO

S

CMO

S

Power Supplies

AI

1

V_REF

–

I/O Reference Voltage

184 V_DDSPDPWR –

EEPROM Power

Supply

Data Sheet

10

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Pin Configuration

Table 3

Pin# Name Pin

Type Type

Pin Configuration of RDIMM (cont’d)

Table 4

Abbreviations for Pin Type

Buffer Function

Abbreviation Description

I

Standard input-only pin. Digital levels.

Other Pins

O

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

82

V_DDID

O

OD

V

_DDIdentification

Note: Pin in tristate,

indicating V_DD

and V_DDQnets

I/O

AI

PWR

GND

NU

NC

connected

PCB

on

Ground

Not Usable

9,

NC

–

Not connected

Not Connected

16,

17,

Pins not connected on

Infineon RDIMM’s

Table 5

Abbreviations for Buffer Type

71,

75,

Abbreviation Description

76,

90,

SSTL

Serial Stub Terminated Logic (SSTL2)

LV-CMOS

CMOS

OD

Low Voltage CMOS

CMOS Levels

101,

102,

103,

113,

163,

173

Open Drain. The corresponding pin has 2

operational states, active low and tristate,

and allows multiple devices to share as a

wire-OR.

Data Sheet

11

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Pin Configuration

V_REF- Pin 001

DQS0 - Pin 005

NC - Pin 009

DQ09 - Pin 013

NC - Pin 017

CKE0 - Pin 021

DQS2 - Pin 025

A7 - Pin 029

DQ24 - Pin 033

A4 - Pin 037

Pin 002 - DQ00

Pin 004 - DQ01

Pin 006 - DQ02

Pin 008 - DQ03

Pin 010 - RESET

Pin 012 - DQ08

Pin 014 - DQS1

Pin 016 - NC

V

_SS- Pin 003

_DD- Pin 007

V

_SS- Pin 011

V

_DDQ- Pin 015

DQ10 - Pin 019

DQ16 - Pin 023

A9 - Pin 027

Pin 018 - V_SS

Pin 020 - DQ11

Pin 022 - V_DDQ

Pin 024 - DQ17

Pin 026 - V_SS

Pin 028 - DQ18

Pin 030 - V_DDQ

DQ19 - Pin 031

DQ25 - Pin 035

DQ26 - Pin 039

Pin 032 - A5

V_SS

V_DD

Pin 034 -

Pin 038 -

Pin 036 - DQS3

Pin 040 - DQ27

A2 - Pin 041

CB01 - Pin 045

CB02 - Pin 049

DQ32 - Pin 053

DQ34 - Pin 057

DQ40 - Pin 061

CAS - Pin 065

DQ43 - Pin 069

DQ49 - Pin 073

V_DDQ- Pin 077

Pin 042 - V_SS

V_DD

A1 - Pin 043

DQS8 - Pin 047

CB03 - Pin 051

DQ33 - Pin 055

BA0 - Pin 059

WE - Pin 063

DQS5 - Pin 067

NC - Pin 071

Pin 044 - CB00

Pin 048 - A0

Pin 046 -

Pin 050 - V_SS

Pin 054 - V_DDQ

Pin 058 - V_SS

Pin 062 - V_DDQ

Pin 066 - V_SS

Pin 052 - BA1

Pin 056 - DQS4

Pin 060 - DQ35

Pin 064 - DQ41

Pin 068 - DQ42

Pin 072 - DQ48

Pin 076 - NC

Pin 080 - DQ51

Pin 084 - DQ57

Pin 088 - DQ59

Pin 092 - SCL

V_DD

Pin 070 -

Pin 074 - V_SS

Pin 078 - DQS6

V_DDID

Pin 082 -

NC - Pin 075

DQ50 - Pin 079

DQ56 - Pin 083

DQ58 - Pin 087

SDA - Pin 091

DQ05 - Pin 095

DQ07 - Pin 099

NC - Pin 103

V

_SS- Pin 081

V

_DD- Pin 085

Pin 086 - DQS7

Pin 090 - NC

Pin 094 - DQ04

Pin 098 - DQ06

Pin 102 - NC

Pin 106 - DQ13

Pin 110 - DQ15

Pin 114 - DQ20

Pin 118 - A11

Pin 122 - A8

Pin 126 - DQ28

Pin 130 - A3

Pin 134 - DQ04

Pin 138 - CK0

Pin 142 - CB06

Pin 146 - DQ36

Pin 150 - DQ38

Pin 154 - RAS

Pin 158 - S1 /NC

Pin 162 - DQ47

Pin 166 - DQ53

Pin 170 - DQ54

Pin 174 - DQ60

Pin 178 - DQ62

Pin 182 - SA1

V

_SS- Pin 089

_SS- Pin 093

V_DDQ

V_SS

V_DDQ

V_DD

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

V_SS

Pin 096 -

Pin 100 -

Pin 104 -

Pin 108 -

Pin 112 -

Pin 116 -

Pin 120 -

Pin 124 -

Pin 128 -

Pin 132 -

Pin 136 -

DM00/DQS9 - Pin 097

NC - Pin 101

DQ12 - Pin 105

DQ14 - Pin 109

NC - Pin 113

DQ21 - Pin 117

DQ22 - Pin 121

A6 - Pin 125

DM1/DQS10 - Pin 107

CKE1/NC - Pin 111

A12/NC - Pin 115

DM2/DQS11 - Pin 119

DQ23 - Pin 123

DQ29 - Pin 127

DQ30 - Pin 131

CB5 - Pin 135

DM3/DQS12 - Pin 129

DQ31 - Pin 133

CK0 - Pin 137

V_DDQ

V

_SS- Pin 139

Pin 140 - DM8/DQS17

Pin 144 - CB07

A10/AP - Pin 141

V

_DDQ- Pin 143

DQ37 - Pin 147

DQ39 - Pin 151

DQ45 - Pin 155

DM5/DQS14 - Pin 159

NC - Pin 163

V

_SS- Pin 145

V_DD

V_SS

V_DDQ

V_SS

V_DDQ

V_DD

V_DDQ

V_SS

V_DDQ

Pin 148 -

Pin 152 -

Pin 156 -

Pin 160 -

Pin 164 -

Pin 168 -

Pin 172 -

Pin 176 -

Pin 180 -

DM4/DQS13 - Pin 149

DQ44 - Pin 153

S0 - Pin 157

DQ46 - Pin 161

DQ52 - Pin 165

DM6/DQS15 - Pin 169

NC - Pin 173

A13/NC - Pin 167

DQ55 - Pin 171

DQ61 - Pin 175

DQ63 - Pin 179

SA2 - Pin 183

DM7/DQS16 - Pin 177

SA0 - Pin 181

Pin 184 - V_DDSPD

MPPD0020

Figure 1

Pin Configuration 184 Pins, Reg

Address Format

Table 6

Density

Organization Memory

Ranks

SDRAMs # of

# of

Refresh Period Interval

SDRAMs

row/rank/

columns

bits

128 MB

256 MB

16M × 72

32M × 72

1

16M × 8

32M × 4

9

12/2/10

12/2/11

4K

64 ms 15.6 µs

18

Data Sheet

12

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Pin Configuration

CK0

PCK

PLL

S0

CKE0

BA0 - BA1

A0 - An

RAS

RS0

CS: SDRAMs D0- D8

RCKE0

RBA0 - RBA1

RA0-RAn

RRAS

CKE: SDRAMs D0 - D8

BA0 - BA1: SDRAMs D0 - D8

A0 - An: SDRAMs D0 - D8

RAS: SDRAMs D0 - D8

CAS: SDRAMs D0 - D8

WE: SDRAMs D0 - D8

R

E

G

I

CAS

RCAS

S

T

E

R

WE

RWE

PCK

RESET

S0

D3

D4

D5

D6

D7

D8

D0

D1

D2

DM0/DQS9

DQS0

DQ0

DM CS

DQS

I/O 0

DM3/DQS12

DQS3

DQ24

DM CS

DQS

I/O 0

DM6/DQS15

DQS6

DQ48

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ1

DQ25

I/O 1

DQ49

I/O 1

DQ2

DQ26

I/O 2

DQ50

I/O 2

DQ3

DQ27

I/O 3

DQ51

I/O 3

DQ4

I/O 4

DQ28

I/O 4

DQ52

DQ5

DQ29

I/O 5

DQ53

I/O 5

DQ6

DQ30

I/O 6

DQ54

I/O 6

DQ7

I/O 7

DQ31

I/O 7

DQ55

DM1/DQS10

DQS1

DQ8

DM CS

DQS

I/O 0

DM4/DQS13

DQS4

DQ32

DM CS

DQS

I/O 0

DM7/DQS16

DQS7

DQ56

DM CS

DQS

I/O 0

DQ9

I/O 1

DQ33

I/O 1

DQ57

I/O 1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 2

DQ34

I/O 2

DQ58

I/O 2

I/O 3

DQ35

I/O 3

DQ59

I/O 3

I/O 4

DQ36

I/O 4

DQ60

I/O 4

I/O 5

DQ37

I/O 5

DQ61

I/O 5

I/O 6

DQ38

I/O 6

DQ62

I/O 6

I/O 7

DQ39

I/O 7

DQ63

I/O 7

DM2/DQS11

DQS2

DQ16

DM CS

DQS

I/O 0

DM5/DQS14

DQS5

DQ40

DM CS

DQS

I/O 0

DM8/DQS17

DQS8

CB0

DM CS

DQS

I/O 0

DQ17

I/O 1

DQ41

I/O 1

CB1

I/O 1

DQ18

I/O 2

DQ42

I/O 2

CB2

I/O 2

DQ19

I/O 3

DQ43

I/O 3

CB3

I/O 3

DQ20

I/O 4

DQ44

I/O 4

CB4

I/O 4

DQ21

I/O 5

DQ45

I/O 5

CB5

I/O 5

DQ22

I/O 6

DQ46

I/O 6

CB6

I/O 6

DQ23

I/O 7

DQ47

I/O 7

CB7

I/O 7

E0

V_DD,SPD

V

_DD: SPD EEPROM E0

_DD/V_DDQ: SDRAMs D0 - D8

_REF: SDRAMs D0 - D8

_SS: SDRAMs D0 - D8

SCL

SAD

SA0

SA1

SA2

V_SS

SCL

SAD

A0

V

_DD/V_DDQ

V

V_REF

A1

V_SS

A2

V_DDID

WP

Strap: see Note 1

MPBD1101

Figure 2

Notes

Block Diagram Raw Card L ×72, 1Rank, ×8, ECC

3. BAn, An, RAS, CAS, WE resistors are 22 ohms

± 5%

1. V_DD= V_DDQ, therefore V_DDIDstrap open

2. DQ, DQS, DM resistors are 22 ohms ± 5%

Data Sheet

13

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Pin Configuration

CK0

PCK

PLL

S0

CKE0

BA0 - BA1

A0 - An

RAS

RS0

CS: SDRAMs D0- D17

RCKE0

RBA0 - RBA1

RA0-RAn

RRAS

CKE: SDRAMs D0 - D17

BA0 - BA1: SDRAMs D0 - D17

A0 - An: SDRAMs D0 - D17

RAS: SDRAMs D0 - D17

CAS: SDRAMs D0 - D17

WE: SDRAMs D0 - D17

R

E

G

I

CAS

RCAS

S

T

E

R

WE

RWE

PCK

RESET

RS0

D0

D1

D2

D3

D4

D5

D6

D12

D13

D14

D15

D16

D17

CS

DQS0

DQ0

DQ1

DQ2

DQ3

DQS

DQS6

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS12

DQ28

DQ29

DQ30

DQ31

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

D7

DQS1

DQ8

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS7

DQ56

DQ57

DQ58

DQ59

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS13

DQ36

DQ37

DQ38

DQ39

DQ9

DQ10

DQ11

D8

DQS2

DQ16

DQ17

DQ18

DQ19

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS8

CB0

CB1

CB2

CB3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS14

DQ44

DQ45

DQ46

DQ47

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D9

DQS3

DQ24

DQ25

DQ26

DQ27

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS9

DQ4

DQ5

DQ6

DQ7

DQS15

DQ52

DQ53

DQ54

DQ55

D10

D11

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS10

DQ12

DQ13

DQ14

DQ15

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS16

DQ60

DQ61

DQ62

DQ63

DQS4

DQ32

DQ33

DQ34

DQ35

DQS11

DQ20

DQ21

DQ22

DQ23

DQS17

CB4

DQS5

DQ40

DQ41

DQ42

DQ43

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CB5

CB6

CB7

E0

V_DD,SPD

SCL

SAD

SA0

SA1

SA2

V_SS

SCL

SAD

A0

V

_DD: SPD EEPROM E0

_DD/V_DDQ: SDRAMs D0 - D17

_REF: SDRAMs D0 - D17

_SS: SDRAMs D0 - D17

V

_DD/V_DDQ

V_REF

A1

V_SS

V_DDID

A2

WP

Strap: see Note 1

MPBD1901

Figure 3

Notes

Block Diagram Raw Card M ×72, 1Rank, ×4, ECC

3. BAn, An, RAS, CAS, WE resistors are 22 ohms

± 5%

4. Each Chip Select and CKE pair alternate between

decks for thermal enhancement.

1. V_DD= V_DDQ, therefore V_DDIDstrap open

2. DQ, DQS, DM resistors are 22 ohms ± 5%

Data Sheet

14

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Electrical Characteristics

3

Electrical Characteristics

3.1

Operating Conditions

Table 7

Absolute Maximum Ratings

Parameter

Symbol

Values

typ.

–

Unit Note/ Test

Condition

min.

V_IN, V_OUT–0.5

max.

Voltage on I/O pins relative to V_SS

V_DDQ

+

V

–

0.5

Voltage on inputs relative to V_SS

Voltage on V_DDsupply relative to V_SS

Voltage on V_DDQsupply relative to V_SS

Operating temperature (ambient)

Storage temperature (plastic)

V_IN

–0.5

0

–

+3.6

+70

+150

–

V

–

V_DD

V_DDQ

T_A

–

V

–

V

–

°C

W

mA

T_STG

P_D

-55

–

Power dissipation (per SDRAM component)

Short circuit output current

2.0

50

I_OUT

–

Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This

is a stress rating only, and functional operation should be restricted to recommended operation

conditions. Exposure to absolute maximum rating conditions for extended periods of time may

affect device reliability and exceeding only one of the values may cause irreversible damage to

the integrated circuit.

Table 8

Electrical Characteristics and DC Operating Conditions

Parameter

Symbol

Values

Typ.

Unit Note/Test Condition ¹⁾

Min.

2.3

Max.

2.7

3.6

0

Device Supply Voltage

Output Supply Voltage

EEPROM supply voltage

V_DD

2.5

V

2)

V_DDQ

2.3

V

V_DDSPD2.3

V

—

Supply Voltage, I/O Supply V_SS,

0

Voltage

V_SSQ

V_REF

V_TT

3)

4)

Input Reference Voltage

0.49 × V_DDQ0.5 × V_DDQ0.51 × V_DDQ

V

I/O Termination Voltage

(System)

V

_REF– 0.04

V

_REF+ 0.04 V

7)

Input High (Logic1) Voltage V_IH(DC)

Input Low (Logic0) Voltage V_IL(DC)

V

_REF+ 0.15

V

_DDQ+ 0.3

V

–0.3

_REF– 0.15 V

Input Voltage Level,

CK and CK Inputs

V_IN(DC)–0.3

_DDQ+ 0.3

_DDQ+ 0.6

V

7)5)

6)

Input Differential Voltage, V_ID(DC)0.36

CK and CK Inputs

V

VI-Matching Pull-up

Current to Pull-down

Current

VI_Ratio

0.71

–2

1.4

2

—

Input Leakage Current

I_I

µA Any input 0 V ≤ V_IN≤ V_DD;

All other pins not under test

= 0 V ⁷⁾⁸⁾

Data Sheet

15

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Electrical Characteristics

Table 8

Electrical Characteristics and DC Operating Conditions (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note/Test Condition ¹⁾

Min.

Max.

Output Leakage Current

I_OZ

I_OH

I_OL

–5

5

µA DQs are disabled;

7)

0 V ≤ V_OUT≤ V_DDQ

Output High Current,

Normal Strength Driver

—

–16.2

—

mA

V

_OUT= 1.95 V ⁷⁾

Output Low

16.2

V

_OUT= 0.35 V ⁷⁾

Current, Normal Strength

Driver

1) 0 °C ≤ T_A≤ 70 °C

2) Under all conditions, V_DDQmust be less than or equal to V_DD

3) Peak to peak AC noise on V_REFmay not exceed ± 2% V_{REF (DC)}. V_REFis also expected to track noise variations in V_DDQ

4) V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal

to V_REF, and must track variations in the DC level of V_REF

.

5) V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the

maximum difference between pull-up and pull-down drivers due to process variation.

7) Inputs are not recognized as valid until V_REFstabilizes.

8) Values are shown per component

Data Sheet

16

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Electrical Characteristics

3.2

Current Specification and Conditions

Table 9

I_DDConditions

Parameter

Symbol

Operating Current 0

I_DD0

one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

Operating Current 1

I_DD1

one bank; active/read/precharge; Burst Length = 4; see component data sheet.

Precharge Power-Down Standby Current

all banks idle; power-down mode; CKE ≤ V_IL,MAX

I_DD2P

I_DD2F

Precharge Floating Standby Current

CS ≥ V_IH,,MIN, all banks idle; CKE ≥ V_IH,MIN

;

address and other control inputs changing once per clock cycle; V_IN= V_REFfor DQ, DQS and DM.

Precharge Quiet Standby Current

I_DD2Q

CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IH,MIN; V_IN= V_REFfor DQ, DQS and DM;

address and other control inputs stable at ≥ V_IH,MINor ≤ V_IL,MAX

.

Active Power-Down Standby Current

one bank active; power-down mode; CKE ≤ V_ILMAX; V_IN= V_REFfor DQ, DQS and DM.

I_DD3P

I_DD3N

Active Standby Current

one bank active; CS ≥ V_IH,MIN; CKE ≥ V_IH,MIN; t_RC= t_RAS,MAX

DQ, DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle.

;

Operating Current Read

I_DD4R

one bank active; Burst Length = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; I_OUT= 0 mA

Operating Current Write

I_DD4W

one bank active; Burst Length = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B

Auto-Refresh Current

I_DD5

I_DD6

I_DD7

t

_RC= t_RFCMIN, burst refresh

Self-Refresh Current

CKE ≤ 0.2 V; external clock on

Operating Current 7

four bank interleaving with Burst Length = 4; see component data sheet.

Data Sheet

17

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Electrical Characteristics

Table 10

I_DDSpecifications and Conditions

Unit

Note ¹⁾²⁾

128MB

x72

128MB

x72

256MB

x72

256MB

x72

1 rank

–7

1 rank

–8

1 rank

–7

1 rank

–8

Symbol

I_DD0

max.

810

max.

765

max.

1620

1980

90,0

810

max.

1530

1800

81,0

630

3)

mA

3)4)

5)

I_DD1

990

900

I_DD2P

I_DD2F

I_DD2Q

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5

45,0

405

40,5

315

5)

405

315

810

630

5)

135

270

5)

405

315

810

630

3)4)

3)

990

810

1980

3420

45

1620

1710

3240

45

990

855

3)

1710

22,5

2520

1620

22,5

2430

5)

I_DD6

3)4)

I_DD7

5040

4860

1) Module I_DDvalues are calculated on the basis of component I_DDand can be measured differently according to DQ loading

capacity.

2) Test condition for maximum values: V_DD= 2.7 V, T_A= 10 °C

3) The module I_DDxvalues are calculated from the I_DDxvalues of the component data sheet as follows:

m × I_DDx[component] + n × I_DD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules

4) DQ I/O (I_DDQ) currents are not included in the calculations (see note 1)

5) The module I_DDxvalues are calculated from the corrponent I_DDxdata sheet values as: (m + n) × I_DDx[component]

Data Sheet

18

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Electrical Characteristics

3.3

AC Characteristics

Table 11

AC Timing - Absolute Specifications PC266A and PC2100

Symbol –8 –7

DDR200

Parameter

Unit Note/

Test Condition

DDR266A

1)

Min. Max.

–0.8 +0.8

0.45 0.55

Min. Max.

–0.75 +0.75

0.45 0.55

2)3)4)5)

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

t_AC

ns

t_CK

ns

t_DQSCK

t_CH

CK low-level width

t_CL

Clock Half Period

t_HP

min. (t_CL, t_CH)

7.5

Clock cycle time

t_CK2.5

t_CK2

t_DH

10

12

—

12

—

CL = 2.5 ^2)3)4)5)

CL = 2.0 ^2)3)4)5)

10

7.5

0.5

2.2

2)3)4)5)

DQ and DM input hold time

DQ and DM input setup time

0.6

2.5

2)3)4)5)

t_DS

2)3)4)5)6)

Control and Addr. input pulse width (each

input)

t_IPW

2)3)4)5)6)

2)3)4)5)7)

2)3)4)5)

DQ and DM input pulse width (each input)

Data-out high-impedance time from CK/CK

Data-out low-impedance time from CK/CK

t_DIPW

t_HZ

2.0

—

1.75

—

ns

t_CK

ns

–0.8 +0.8

0.75 1.25

–0.75 +0.75

0.75 1.25

t_LZ

Write command to 1^stDQS latching transition t_DQSS

DQS-DQ skew (DQS and associated DQ

signals)

t_DQSQ

—

+0.6

—

+0.5

TSOPII^2)3)4)5)

Data hold skew factor

t_QHS

t_QH

—

1.0

—

0.75

ns

TSOPII^2)3)4)5)

2)3)4)5)

DQ/DQS output hold time

t

_HP– t_QHS

t

_HP– t_QHS

ns

2)3)4)5)

DQS input low (high) pulse width (write cycle) t_DQSL,H0.35 —

0.35

0.2

—

t_CK

DQS falling edge to CK setup time (write cycle) t_DSS

0.2

—

DQS falling edge hold time from CK (write

cycle)

t_DSH

2)3)4)5)

Mode register set command cycle time

Write preamble setup time

Write postamble

t_MRD

2

0

—

2

0

—

t_CK

ns

2)3)4)5)8)

2)3)4)5)9)

2)3)4)5)

t_WPRES

t_WPST

t_WPRE

t_IS

0.40 0.60

0.25 —

0.40 0.60

t_CK

ns

Write preamble

0.25

0.9

—

Address and control input setup time

1.1

—

fast slew rate

3)4)5)6)10)

1.0

0.9

1.0

—

1.1

ns

slow slew rate

3)4)5)6)10)

Address and control input hold time

t_IH

fast slew rate

3)4)5)6)10)

slow slew rate

3)4)5)6)10)

Read preamble

t_RPRE

t_RPRES

t_RPST

t_RAS

0.9 1.1

1.5

0.40 0.60

50 120E+3 45

0.9

t_CKCL > 1.5 ^2)3)4)5)

2)3)4)5)11)

Read preamble setup time

Read postamble

—

NA

ns

2)3)4)5)

0.40 0.60

t_CK

2)3)4)5)

Active to Precharge command

120E+3 ns

Data Sheet

19

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Electrical Characteristics

Table 11

AC Timing - Absolute Specifications PC266A and PC2100

Parameter

Symbol –8

DDR200

Min. Max.

–7

Unit Note/

Test Condition

DDR266A

Min. Max.

1)

2)3)4)5)

Active to Active/Auto-refresh command period t_RC

70

80

—

65

75

—

ns

Auto-refresh to Active/Auto-refresh command t_RFC

period

2)3)4)5)

2)3)4)5)12)

Active to Read or Write delay

Precharge command period

Active to Autoprecharge delay

Active bank A to Active bank B command

Write recovery time

t_RCD

t_RP

20

—

20

—

ns

t_CK

t_RAP

t_RRD

t_WR

t_RCDor t_RAS

15

—

15

—

Auto precharge write recovery + precharge

time

t_DAL

(t_wr/t_CK) + (t_rp/t_CK)

Internal write to read command delay

Exit self-refresh to non-read command

Exit self-refresh to read command

Average Periodic Refresh Interval

t_WTR

t_XSNR

t_XSRD

t_REFI

1

—

1

—

t_CKCL > 1.5 ^2)3)4)5)

2)3)4)5)

80

200

—

75

200

—

ns

2)3)4)5)

—

t_CK

2)3)4)5)13)

15.6

µs

1) 0 °C ≤ T_A≤ 70 °C; V_DDQ= 2.5 V ± 0.2 V, V_DD= +2.5 V ± 0.2 V

2) Input slew rate ≥ 1 V/ns for DDR266, and = 1 V/ns for DDR200

3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference

level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.

4) Inputs are not recognized as valid until V_REFstabilizes.

5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.

6) These parameters guarantee device timing, but they are not necessarily tested on each device.

7) t_HZand t_LZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.

A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were

previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS

.

9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) degrades accordingly.

10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,

measured between V_OH(ac)and V_OL(ac)

.

11) t_RPRESis defined for CL = 1.5 operation only

12) For each of the terms, if not already an integer, round to the next highest integer. t_CKis equal to the actual system clock

cycle time.

13) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

Data Sheet

20

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

SPD Contents

4

SPD Contents

Table 12

Byte#

SPD Codes

Description

128MB 128MB 256MB 256MB

x72

1rank

-7

x72

1rank

-8

x72

1rank

-7

x72

1rank

-8

HEX.

80

HEX.

80

HEX.

80

HEX.

80

0

1

2

3

4

5

6

7

8

9

10

Number of SPD Bytes

Total Bytes in Serial PD

Memory Type

128

256

08

DDR-SDRAM

12

07

Number of Row Addresses

0C

0A

01

0C

0A

01

0C

0B

01

0C

0B

01

Number of Column Addresses 10/11

Number of DIMM Ranks

Module Data Width

1

×72

48

Module Data Width (cont’d)

Module Interface Levels

0

00

SSTL_2.5

04

SDRAM Cycle Time at CL = 2.5 7 ns/8 ns

70

80

70

80

Access Time from Clock at

CL = 2.5

0.75 ns/0.8 ns

75

80

75

80

11

12

13

14

DIMM config

ECC

02

80

08

02

80

08

02

80

04

02

80

04

Refresh Rate/Type

SDRAM Width, Primary

Self-Refresh 15.6 ms

×8/×4

Error Checking SDRAM Data

Witdh

na

15

Minimum Clock Delay for Back- t_CCD= 1 CLK

to-Back Random Column

Address

01

16

17

18

19

20

21

Burst Length Supported

Number of SDRAM Ranks

Supported CAS Latencies

CS Latencies

2, 4 & 8

0E

04

0C

01

02

26

0E

04

0C

01

02

26

0E

04

0C

01

02

26

0E

04

0C

01

02

26

4

CAS latency = 2 & 2.5

CS latency = 0

Write latency = 1

registered

WE Latencies

SDRAM DIMM Module

Attributes

22

23

24

25

26

SDRAM Device Attributes:

General

Concurrent Auto

Precharge

C0

75

00

C0

A0

80

00

C0

75

00

C0

A0

80

00

Min. Clock Cycle Time at CAS 7.5 ns/10 ns

Latency = 2

Access Time from Clock for

CL = 2

0.75 ns/0.8 ns

Minimum Clock Cycle Time for not supported

CL = 1.5

Access Time from Clock at

CL = 1.5

not supported

Data Sheet

21

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

SPD Contents

Table 12

Byte#

SPD Codes (cont’d)

Description

128MB 128MB 256MB 256MB

x72

1rank

-7

x72

1rank

-8

x72

1rank

-7

x72

1rank

-8

HEX.

50

HEX.

50

HEX.

50

HEX.

50

27

28

Minimum Row Precharge Time 20 ns

Minimum Row Act. to Row Act. 15 ns

3C

Delay t_RRD

29

Minimum RAS to CAS Delay t_RCD20 ns

50

2D

20

90

50

00

41

4B

50

32

20

B0

60

00

46

50

2D

40

90

50

00

41

4B

50

32

40

B0

60

00

46

50

30

Minimum RAS Pulse Width t_RAS45 ns/50 ns

Module Rank Density (per Rank) 128 MByte/256 Mbyte

Addr. and Command Setup Time 0.9 ns/1.1 ns

Addr. and Command Hold Time 0.9 ns/1.1 ns

31

32

33

34

Data Input Setup Time

Data Input Hold Time

Superset Information

0.5 ns/0.6 ns

–

35

36 to 40

41

Minimum Core Cycle Time t_RC65 ns/70 ns

42

Min. Auto Refresh Cmd Cycle

75 ns/80 ns

Time t_FRC

43

Maximum Clock Cycle Time t_CK12 ns

0C

32

75

00

A7

C1

0C

3C

A0

00

9C

C1

0C

32

75

00

C0

C1

0C

3C

A0

00

B5

C1

44

Max. DQS-DQ Skew tDQSQ

X-Factor tQHS

0.5 ns/0.6 ns

45

0.75 ns/1.0 ns

46 to 61

62

Superset Information

SPD Revision

–

Revision 0.0

–

63

Checksum for Bytes 0 - 62

64

Manufactures JEDEC ID Codes –

65 to 71

72

Manufactures

–

Infineon Infineon Infineon Infineon

Module Assembly Location

Module Part Number

Module Revision Code

Module Manufacturing Date

Module Serial Number

–

73 to 90

91 to 92

93 to 94

95 to 98

99 to 127

128 to 255 open for Customer use

Data Sheet

22

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Package Outlines

5

Package Outlines

133.35

128.95

0.15

A B C

4 MAX.

1)

A

1

2.5

92

B

C

6.62

2.175

±0.1

ø0.1

A B C

0.4

6.35

±0.1

1.27

64.77

49.53

95 x 1.27 = 120.65

±0.1

1.8

0.1

A B C

93

184

1)

3 MIN.

Detail of contacts

1.27

±0.05

1

0.1

A B C

1) On ECC modules only

Burr max. 0.4 allowed

Figure 4

Package Outline RDIMM Raw Card (L-DIM-184-12-3)

Data Sheet

23

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Package Outlines

133.35

128.95

0.15

A B C

4 MAX.

1)

A

1

2.5

92

B

C

6.62

2.175

±0.1

ø0.1

A B C

0.4

6.35

±0.1

1.27

64.77

49.53

95 x 1.27 = 120.65

±0.1

1.8

0.1

A B C

93

184

3 MIN.

Detail of contacts

1.27

±0.05

1

0.1

A B C

1) On ECC modules only

Burr max. 0.4 allowed

Figure 5

Package Outline RDIMM Raw Card (L-DIM-184-L13-2)

Data Sheet

24

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Application Note

6

Application Note

Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item

1173)

184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and

to minimize power consumption during low power mode. One feature is externally controlled via a system-

generated RESET signal; the second is based on module detection of the input clocks. These enhancements

permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations

and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked

Loop) when the memory is in Self-Refresh mode.

The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM

inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the

register outputs are forced to a low level, and all differential register input receivers are powered down, resulting

in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as

an asynchronous signal according to the attached details. Using this function also permits the system and DIMM

clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh

mode.

Table 13

RESET Truth Table

Register Inputs

Register

Outputs

RESET

CK

Data in (D)

Data out (Q)

H

Rising

L or H

Falling

L or H

High Z

H

L

H

L

X

Qo

High Z

Illegal input

conditions

L

X or Hi-Z

L

X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling

As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are

maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low

maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until

activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.

The DDR PLL devices automatically detect clock activity above 20 MHz. When an input clock frequency of 20 MHz

or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating

frequency at which all specifications will be met is 95 MHz). If the clock input frequency drops below 20 MHz

(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are

made High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less

than 1 mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it

is tied inactive on the DIMM. This application note describes the required and optional system sequences

associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer

to both CKE0 and CKE1 for a 2-rank DIMM. Because RESET applies to all DIMM register devices, it is therefore

not possible to uniquely control CKE to one physical DIMM rank through the use of the RESET pin.

Power-Up Sequence with RESET — Required

1. The system sets RESET at a valid low level.

This is the preferred default state during power-up. This input condition forces all register outputs to a low state

independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level

at the DDR SDRAMs.

Data Sheet

25

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Application Note

2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR

SDRAMs.

3. Stabilization of Clocks to the SDRAM

The system must drive clocks to the application frequency (PLL operation is not assured until the input clock

reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,

and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,

the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a

stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior to

SDRAM operation.

4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM

connector).

CKE must be maintained low and all other inputs should be driven to a known state. In general these

commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command

(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would

be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be

consistent with the state of the register outputs.

5. The system switches RESET to a logic ‘high’ level.

The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,

setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs

must remain stable).

6. The system must maintain stable register inputs until normal register operation is attained.

The registers have an activation time that allows their clock receivers, data input receivers, and output drivers

sufficient time to be turned on and become stable. During this time the system must maintain the valid logic

levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE

outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time

(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to

accept an input signal, is specified in the register and DIMM do-umentation.

7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-

pproved initialization sequence).

Self Refresh Entry (RESET low, clocks powered off) — Optional

Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down

and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.

Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption

(RESET low deactivates register CK and CK, data input receivers, and data output drivers).

1. The system applies Self Refresh entry command.

(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)

Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a

Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input

conditions to the SDRAM are Don’t Cares— with the exception of CKE.The system sets RESET at a valid

low level.

This input condition forces all register outputs to a low state, independent of the condition on the registerm

inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-

level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation

to a specific clock edge is not required.

2. The system turns off clock inputs to the DIMM. (Optional)

a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock

inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the

register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address

signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM

documentation.

b. The system may release DIMM address and control inputs to High-Z.

This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which

Data Sheet

26

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Application Note

the clocks and the control and the address signals must maintain valid levels after RESET low has been

applied. It is highly recommended that CKE continue to remain low during this operation.

3. The DIMM is in lowest power Self Refresh mode.

Self Refresh Exit (RESET low, clocks powered off) — Optional

1. Stabilization of Clocks to the SDRAM.

The system must drive clocks to the application frequency (PLL operation is not assured until the input clock

reaches ~ 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,

and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,

the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.

2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM

connector).

CKE must be maintained low and all other inputs should be driven to a known state. In general these

commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command

(with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this

would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to

be consistent with the state of the register outputs.

3. The system switches RESET to a logic ‘high’ level.

The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,

RESET timing relationship to a specific clock edge is not required (during this period, register inputs must

remain stable).

4. The system must maintain stable register inputs until normal register operation is attained.

The registers have an activation time that allows the clock receivers, input receivers, and output drivers

sufficient time to be turned on and become stable. During this time the system must maintain the valid logic

levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE

outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time

(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to

accept an input signal, is specified in the register and DIMM do-umentation.

5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.

Self Refresh Entry (RESET low, clocks running) — Optional

Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this

is an alternate operating mode for these DIMMs.

1. System enters Self Refresh entry command.

(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)

Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a

Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input

conditions to the SDRAM are Don’t Cares — with the exception of CKE.

2. The system sets RESET at a valid low level.

This input condition forces all register outputs to a low state, independent of the condition on the data and clock

register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.

3. The system may release DIMM address and control inputs to High-Z.

This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes

the time in which the clocks and the control and the address signals must maintain valid levels after RESET

low has been applied. It is highly recommended that CKE continue to remain low during the operation.

4. The DIMM is in a low power, Self Refresh mode.

Self Refresh Exit (RESET low, clocks running) — Optional

1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM

connector).

CKE must be maintained low and all other inputs should be driven to a known state. In general these

commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command

(with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be

Data Sheet

27

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

HYS72D[16500/32501]GR-[7/8]-A

Low Profile Registered DDR SDRAM-Modules

Application Note

a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent

with the state of the register outputs.

2. The system switches RESET to a logic 'high' level.

The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,

it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain

stable).

3. The system must maintain stable register inputs until normal register operation is attained.

The registers have an activation time that allows the clock receivers, input receivers, and output drivers

sufficient time to be turned on and become stable. During this time the system must maintain the valid logic

levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE

outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation

time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept

an input signal, is t (ACT ) as specified in the register and DIMM documentation.

4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.

Self Refresh Entry/Exit (RESET high, clocks running) — Optional

As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification

explains in detail the method for entering and exiting Self Refresh for this case.

Self Refresh Entry (RESET high, clocks powered off) — Not Permissible

In order to maintain a valid low level on the register output, it is required that either the clocks be running and the

system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the

sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,

the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM

state will result.

Data Sheet

28

Rev. 1.2, 2004-06

10292003-DNYO-BD9L

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

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